JPH02275549A - Intermediate buffer prefetch control system - Google Patents

Abstract

PURPOSE:To prevent an access from the same device to the succeeding main storage from being delayed by providing the intermediate buffer prefetch control system with a means for improving the priority order of access to the main storage device for prefetch when the succeeding read request arrives and its corresponding data are not stored in an intermediate buffer. CONSTITUTION:The control system is constituted of ports 1, 2, an address counting register 3, a GBS priority circuit 4, an MSU priority circuit 5, a regis ter 6 for setting up a fetch flag, an AND circuit 7, and a selector 8. When the succeeding read request arrives from a device generating a read request for a main storage device generating a chance for prefetch and its corresponding data are not stored in the intermediate buffer during the execution of prefetch for writing data in the intermediate buffer, the priority order of the prefetch access to the main storage device is improved by the means. Consequently, the delay of the access for prefetch to the main storage can be removed.

Description

[Detailed Description of the Invention] [Summary] Regarding prefetch control for writing data to an intermediate buffer in a main memory control device, depending on priority conditions related to prefetch processing, the next main memory from the same device is In a main memory control device that has an intermediate buffer and performs prefetching to the main memory in multiple times to obtain data written to the intermediate buffer, the purpose is to prevent delays in access to the intermediate buffer. While a prefetch is being performed, if the next read request arrives from the device that issued the main memory read request that triggered the prefetch, and the corresponding data does not exist in the intermediate buffer, the main memory of the prefetch is This is configured by providing means for increasing the priority of access to the device.

[Industrial Application Field] The present invention relates to a control system for a main memory control device, and in particular, it has an intermediate buffer (hereinafter also referred to as GBS) and is configured to control the hit rate of the intermediate buffer with respect to access requests to the main memory from other devices. The present invention relates to a control method for a main memory control device configured to perform prefetching in order to improve performance.

[Prior Art] FIG. 2 is a block diagram showing the configuration of a main storage control device having a CBS, in which 51 is a main storage device (hereinafter also referred to as MSU), 52 is a main storage control device, and 53 and 54 are CPUs.
, 55 is GBS, 56 is GBS priority circuit, 5
7 represents an MSU priority circuit, and 58.59 represents a selector.

In the figure, the CPU 53 or 54 is the main memory 5.
When an access request is issued to the main memory control device 52 to read data in the GBS 55, the main memory control device 52 checks whether the data in the corresponding area exists in the GBS 55 and reads out the data in the corresponding area. If data exists, the main storage device 51
The corresponding data is read from the GBS 55 without accessing it and transferred to the requesting CPU.

If the corresponding area has not been written to the GBS 55 and no data exists, the main storage device 51 is accessed and the data of the corresponding area is read, but at the same time, the data including the area is Data in a fixed unit area is read and written to the GBS 55. Information (programs and data) normally requested by the CPU is often stored in a contiguous area within the main memory, so this allows the next access request to be made without having to access the main memory. It becomes possible to immediately read data from the GBS 55 and pass it to the CPU, thereby reducing access time.

A CBS priority circuit 56 and an MSU priority circuit 57 are provided for access requests from each of the plurality of CPUs (CPU 53 and CPU 54), and are controlled to preferentially select access requests with a high priority. ing.

[Problems to be Solved by the Invention] In the main memory control device as described above, the data obtained from the main memory by one access is relatively small, so in order to obtain the necessary amount of data, multiple accesses are required. Access to main memory is required.

During these multiple accesses, priority is determined by the MSU priority circuit each time.

FIG. 3 is a diagram explaining such access to the main memory, where 60 and 61 are ports, 62 is a selector, 63 is an address count register, 64 is a register for setting a prefetch flag, and 65 is a CBS priority. The circuit 66 represents the MSU priority circuit.

Ports 61, 62, selector 62, address count register 63, and register 64 are each used by one CPU, and other CPUs have ports, registers, etc. that are equivalent to these. A fetch request from the CPU is set to one of ports 6061. Then, when priority is acquired by the GBS priority circuit 65, the CBS is accessed.

At this time, if the CBS does not have the desired data, the corresponding address value is set in the address count register 63, and when it acquires priority by the MSU priority circuit 66, the main memory is accessed and the desired data is read out.

Further, the value of the address count register 63 is counted up, and the prefetch data is written to the CBS through multiple accesses while gaining priority over the MSU priority circuit 66 and the CBS priority circuit 65.

For example, the read/write width of main memory is 8 bytes, and C
If one block of BS is 64 bytes, it will be accessed eight times.

The register 64 is set to “1” while prefetching is being performed.
is retained to indicate that it is being prefetched.

In such conventional control systems, access for prefetching is given the lowest priority so as not to interfere with main access that directly requires data.

Therefore, when a prefetch is being performed in response to an access to the main memory from a certain CPU, if there is an access to the main memory from another CPU, the t of the prefetch is
Access to the main storage device cannot be accepted immediately and will have to wait.

Therefore, at this time, the C
Even if PtJ issues the next access request, it will take a long time due to the address count register being in use and the prefetch main memory access priority conditions that are causing this. There was a problem.

In view of these conventional problems, the present invention provides control that does not cause a conflict in which fetching of data necessary for the current process is delayed due to prefetching performed in preparation for the next process. The purpose is to provide a method.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention
When it has an intermediate buffer and receives a read request from the main memory, it first checks the intermediate buffer, and if the data in the corresponding area does not exist, it accesses the main memory and reads the corresponding data. The device is configured to perform prefetching in which data in a certain area is read out from the main memory in multiple batches and written to the intermediate buffer, and a circuit for determining the priority order of access to the intermediate buffer and a circuit for determining access priority to the main memory are configured. In a main memory control device equipped with a circuit that determines access priority, a main memory read request that triggered the prefetch is issued while a prefetch is being performed to write data to an intermediate buffer. This intermediate 1<rough prefetch control system is provided with a means for increasing the priority of access to the main storage device for the prefetch when the next read request arrives from the device that has received the prefetch and the corresponding data does not exist in the intermediate buffer.

[Function] Conventionally, during CBS prefetch, the priority of access to the main memory for the prefetch was set low, so if there was conflict with other accesses, it was difficult to obtain the right to access the main memory. As a result, processing of the next access request from the tjl location that requested access to the main memory that caused the GBS prefetch may be delayed. However, in the present invention, the prefetch When there is a next access request from the same device during the prefetch, the priority of access to the main memory for the prefetch is raised, so the main memory access for the prefetch will not be stagnant.
It is possible to eliminate the inconvenience that acquisition of data directly necessary for the current CPU processing (current fetch) is delayed due to prefetch processing that is not directly related to the current CPU processing.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
2 is port, 3 is address count register, 4 is GB
An S priority circuit, 5 an MSU priority circuit, 6 a register for setting a prefetch flag, 7 an AND circuit, and 8 a selector are provided for each CPU.

In the figure, a boat 1 or 2 is provided corresponding to each CPU.

Therefore, when a 7 fetch request comes from the CPU, the fetch request is set to the port (1 or 2) corresponding to the CPU, and the CBS priority circuit 4 sets the fetch request to the port (1 or 2) corresponding to the CPU.
Participate in BS Priority.

As a result of acquiring access rights to the CBS and accessing the CBS, if there is no corresponding data in the GBS, a request is set in the address count register 3, and this is sent to the MS.
Join U Priority.

Then, it acquires access rights to the MSU and moves the read data into the GBS.

At this time, the read/write width of the main memory is 8 bytes,
If one block of CBS is 64 bytes, it must be accessed eight times, and it is necessary to obtain access rights each time.

Therefore, the address count register 3 is further counted up to participate in the MSU priority, and when the access right is obtained, the operation of accessing the MSU, reading data, and moving it into the CBS is repeatedly performed.

At this time, as mentioned above, if one block is 64 bytes and the read/write width of the MSU is 8 bits, then 8 times of 8 bytes for normal fetch, and 8 times of 8 bytes for prefetch, for a total of 16 times. The MSU must be accessed twice.

During this prefetch operation, if the next access request comes to the same port and the corresponding data does not exist in the CBS, the main memory will be accessed in response to this access request, but this is because the prefetch operation is completed. Until then, you cannot participate in MSU Priority.

Therefore, in the present invention, in such a case, the priority of the main memory access of the prefetch operation is raised so that the current prefetch operation can be processed immediately and the next access request can be responded to quickly. In this embodiment, this control is carried out by the output of the register 6 (indicated by letter group A in the figure) which holds a flag indicating prefetch, and the output of selector 8 (signal indicated by letter group B in the figure). The output signal C of the AND circuit 7 which inputs "1" when the next access to the main memory comes is applied to the MSU priority circuit 5, and the main memory for the prefetch operation is controlled by the signal C. control to increase priority of access.

The output signal C of the AND circuit 7 is "1" at the time of prefetch/next access, and the priority is low at this time.

In this embodiment, when accessing using the address count register 3, this priority is given "1" if it is a low priority, and "0'" if it is a high priority.

C Effects of the Invention] Conventionally, if a prefetch was in progress, the current fetch could not participate in the MSU priority until the prefetch was completed.

Furthermore, (1, the priority of BS prefetch is
Since it is the lowest, there was a problem that if there was an access from another processor, that processor would be processed first, resulting in a unilateral delay.

In the present invention, when a current fetch is sent during CBS prefetch, it is possible to raise the priority of the prefetch, for example, to give it the same access priority as other processors and to process it alternately. Therefore, there is no longer a unilateral delay in prefetch processing.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a CB
FIG. 3 is a block diagram showing the configuration of a main memory control device having S. FIG. 3 is a diagram illustrating access to the main memory.

Claims (1)

[Claims] When an intermediate buffer is provided and a read request from the main memory is received, the intermediate buffer is first checked, and if the data in the corresponding area does not exist, the main memory is accessed and the corresponding data is retrieved. In addition to reading data, the data storage device is configured to perform prefetching in which data in a certain area containing the data is read out from the main memory in multiple batches and written to the intermediate buffer, and the priority order of access to the intermediate buffer is determined. In a main memory device that is equipped with a circuit and a circuit that determines the priority order of access to the main memory device, while a prefetch is being performed to write data to an intermediate buffer, the main memory that triggered the prefetch is The present invention is characterized in that, when a next read request arrives from the device that issued the device read request and the corresponding data does not exist in the intermediate buffer, a means is provided for increasing the priority of access to the main memory of the prefetch. Intermediate buffer prefetch control method.