JPH02275513A - Reset circuit - Google Patents

Abstract

PURPOSE:To store a reset factor to analyze a reset generating factor afterword by providing a reset circuit with factor storage parts for temporarily storing reset pulse generating factors, a buffer for reading out information from the factor storage parts and an arithmetic processing part for storing the information of the factor storing parts through the buffer. CONSTITUTION:The reset circuit is provided with the factor storage parts 2a to 2n for storing reset pulse generating factors, the buffer 3 for reading out information by the arithmetic processing part 2, a reset control part 4 for restricting a reset factor, a factor storage part clearing part 5 for clearing the information stored in the factor storage parts, and a reset pulse generating part 6 for generating a reset pulse. When the system is restored from the reset state, the arithmetic processing part 2 reads out the information stored in the factor storage parts 2a to 2n. Thus, what is the reset generating factor can be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset circuit, and more particularly to a reset circuit having a function of storing reset occurrence factors and a function of limiting subsequent reset pulses.

[Conventional technology]

In conventional reset circuits, a reset pulse is generated immediately when a reset factor occurs, so when the device recovers from a reset state, it is very difficult to recognize the cause of the reset occurrence.

[Problem to be solved by the invention]

In the conventional reset circuit described above, it is very difficult to recognize what caused the reset to occur.
The need to reset the device often occurs when a fatal error occurs within the device. Therefore, it is necessary to promptly discover the location where the error occurs and take countermeasures. However, the conventional configuration has the disadvantage that it is difficult to discover the location where this error occurs, requiring a large amount of time and man-hours.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reset circuit that stores reset factors and can later analyze the reset occurrence factors.

[Means to solve the problem]

The reset circuit of the present invention includes a factor storage section for temporarily storing a reset pulse generation factor, a buffer for reading information from the factor storage section, and a reset control section for limiting subsequent successive reset pulses. a reset pulse generating section that generates a reset drive pulse based on a control signal limited by the reset control section; and an arithmetic processing section that stores information in the factor storage section via the buffer.
and a factor storage unit clearing unit that erases information in the cause storage unit using a control signal outputted when the calculation processing unit completes storage, and analyzes the storage contents of the calculation processing unit to recognize the cause of the reset occurrence.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system diagram of an embodiment of the present invention 4. The embodiment shown in FIG. , a factor storage clearing section 5, and a reset pulse generating section 6. In normal operation, factor 1 of the reset factor generation section
-n does not exist. When a reset factor occurs in the reset factor generating section 1 for some reason, this information is first stored in one of the factor storage sections 2a to 2n. For example, the factor storage unit 2a stores reset factor 1 as information. Next, the factor information C2a in the factor storage section 2a is transmitted to the reset control section 4. The reset control unit 4 transmits only the earliest reset/reset cause (for example, C2a) to the reset pulse generator 6. Here, if the reset control unit 4 inputs factors 2 to n one after another after reset factor 1, reset pulses are generated repeatedly, and in order to prevent the device from being reset multiple times, the reset pulse is generated as soon as possible. The device recovery time is minimized by validating only the reset factor information that has been reset and restricting other information. The reset pulse generator 6 generates a reset pulse e2 according to the signal d2 transmitted from the reset controller 4. These operations put the device into a reset state. after that,
The normal layer returns.

Next, the reset occurrence factor recognition process will be explained.

The arithmetic processing unit 2 that has recovered from the reset state stores the cause memory units 2a to 2 in order to recognize what was the cause of the reset.
The information stored in n is passed through the buffer 3 and read out. The buffer 3 is provided to control the order of reading and to perform the reading operation smoothly when there are a large number of factor storage units 2a to 2n. When the read operation of the arithmetic processing section 2 is completed, the factor storage section clearing section 5 automatically clears the information in the factor storage sections 2a to 2n. As a result, the factor storage units 2a to 2n start storing and accepting new factors.

〔Effect of the invention〕

As described above, the present invention provides a factor storage section for storing reset pulse generation factors, a buffer for the arithmetic processing section to read information in the factor storage section, a reset control section for limiting reset factors, and It is equipped with a factor memory clear section for clearing the information in the cause memory section and a reset pulse generation section for generating a reset pulse. This has the effect of making it possible to recognize what caused the reset to occur.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. 1... Reset factor generation section, 2... Arithmetic processing section, 3
. . . buffer, 4 . . . reset control section, 5 . . . factor storage unit clear section, 6 . . . reset pulse generation section.

Claims (1)

[Claims] A factor storage section for temporarily storing reset pulse generation factors, a buffer for reading information from the factor storage section, a reset control section for limiting successive firing of subsequent reset pulses, and a restriction by the reset control section. a reset pulse generating section that generates a reset driving pulse based on the control signal generated by the processing; an arithmetic processing section that stores information in the factor storage section via the buffer; and a control that outputs when the arithmetic processing section finishes storing the information. A reset circuit comprising: a factor storage section clearing section that erases information in the factor storage section in response to a signal, and analyzing the storage contents of the arithmetic processing section to recognize a reset occurrence factor.