JPH02271656A - Multilayered microwave integrated circuit - Google Patents

Multilayered microwave integrated circuit

Info

Publication number
JPH02271656A
JPH02271656A JP1093784A JP9378489A JPH02271656A JP H02271656 A JPH02271656 A JP H02271656A JP 1093784 A JP1093784 A JP 1093784A JP 9378489 A JP9378489 A JP 9378489A JP H02271656 A JPH02271656 A JP H02271656A
Authority
JP
Japan
Prior art keywords
circuit
lower layer
circuits
conductor layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1093784A
Other languages
Japanese (ja)
Inventor
Yukio Ikeda
幸夫 池田
Sunao Takagi
直 高木
Shuji Urasaki
修治 浦崎
Yoji Isoda
陽次 礒田
Mitsuru Mochizuki
満 望月
Kiyoharu Kiyono
清春 清野
Kenji Suematsu
憲治 末松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1093784A priority Critical patent/JPH02271656A/en
Publication of JPH02271656A publication Critical patent/JPH02271656A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Waveguides (AREA)

Abstract

PURPOSE:To prevent unnecessary electrical interference from being produced between an upper layer circuit and a lower layer circuit by shielding an electromagnetic field with a conductor layer by laminating said circuits with said conductor layer held between those circuits, said conductor layer being earthed keeping its state where it is insulated from parts of said circuits other than at least earthed portion of the same. CONSTITUTION:Circuits 2a, 2b of semiconductor substrates 1a, 1b are laminated with a conductor layer 7 held therebetween, the conductor layer 7 being earthed in its state where it is isolated from portions of said circuits other than at least earthed portions of the same. Accordingly, also when the circuit is operated in a microwave range, there are provided between the respective circuits and the earthed conductor layer 7 an electromagnetic field due to a current flowing through the upper layer circuit 2a and an electromagnetic field due to a current flowing through the lower layer circuit 2b. Hereby, there is eliminated electrical interference between the upper layer circuit 2a and the lower layer circuit 2b, and the upper and lower layer circuits 2a and 2b are connected at a connection line 4 so that desired operation is achieved as a whole. Hereby, there can be eliminated unnecessary electrical interference between the upper and lower layer circuits upon use in a microwave range.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は多層化マイクロ波集積回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a multilayer microwave integrated circuit.

〔従来の技術〕[Conventional technology]

第1)図は例えば古用靜二部編著、「SO工溝構造形成
技術、産業図書IP、193〜P、196に示された低
周波用の多層化集積回路の一例の断面図であり、 (I
a)はシリコンで成る下部層半導体基板。
Figure 1) is a cross-sectional view of an example of a multilayer integrated circuit for low frequencies, as shown in, for example, "SO Groove Structure Formation Technology, Sangyo Tosho IP, 193-P, 196, edited by Seibu Furuyo, (I
a) is a lower layer semiconductor substrate made of silicon;

(1b)はシリコンでなる下部層半導体基板、 (2a
)は下部層半導体基板(1a)上に形成された上部層回
路、 (2b)は下部層半導体基板(1b)上に形成さ
れた下部層回路である。上部層回路(2a)及び下部層
回路(2b)はそれぞれ電解効果トランジスタ(pET
と称す)等の能動同格素子と、抵抗やコンデンサ等の受
動回路素子及び線路とから構成される。また、(3)は
積層された下部層回路(2a)と下部層回路(2b) 
t−絶縁するポリイミドを用い次絶縁体層、(4)は積
層された状態で機能を持つよう下部層回路(2a)と下
部層回路(2b)の所定の個所を電気的に導通させるよ
う設けた接続線である。
(1b) is a lower layer semiconductor substrate made of silicon, (2a
) is an upper layer circuit formed on a lower layer semiconductor substrate (1a), and (2b) is a lower layer circuit formed on a lower layer semiconductor substrate (1b). The upper layer circuit (2a) and the lower layer circuit (2b) are each a field effect transistor (pET).
It consists of active equivalent elements such as (referred to as ), passive circuit elements such as resistors and capacitors, and lines. In addition, (3) is a stacked lower layer circuit (2a) and lower layer circuit (2b).
The next insulating layer (4) using polyimide for T-insulation is provided to electrically connect predetermined points of the lower layer circuit (2a) and the lower layer circuit (2b) so that they function in a laminated state. This is the connecting line.

以上のように従来の多層化集積回路は下部層回路(2a
)と下部層回路(2b)が向かい合うよう積層され2両
回路の電気的な分離は絶縁体NIt31のみで行なわれ
ている。また、十分周波数の低い低周波帯で動作させた
場合には、波長に対して回路構成物が小さく結合が小さ
いため下部層回路(2a)と下部層回路(2b)との不
必要な電気的干渉は無く9両回路は接続線(4)により
接続されているので。
As mentioned above, conventional multilayer integrated circuits have lower layer circuits (2a
) and the lower layer circuit (2b) are stacked so as to face each other, and the two circuits are electrically separated only by the insulator NIt31. In addition, when operating in a low frequency band with a sufficiently low frequency, unnecessary electrical connections between the lower layer circuit (2a) and the lower layer circuit (2b) are caused because the circuit components are small and the coupling is small relative to the wavelength. There is no interference as the 9 circuits are connected by the connecting wire (4).

全体でWr望の動作を行なう。Perform the desired operation as a whole.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の多層化集積回路は以上のように構成されているの
で、マイクロ波帯のような高周波帯で使用すると波長が
短いために結合量が増加し下部層回路と下部層回路の電
気的干渉が発生するという問題点があった。
Conventional multilayer integrated circuits are configured as described above, so when used in high frequency bands such as microwave bands, the amount of coupling increases due to the short wavelength and electrical interference between lower layer circuits and lower layer circuits occurs. There was a problem that occurred.

この発明はこのような問題点を解消するためになされた
もので、マイクロ仮借での使用において下部層回路と下
部層回路の不必要な電気的干渉が無い、多層化マイクロ
波集積回路を得ることを目的とする。
This invention has been made to solve these problems, and is to obtain a multilayer microwave integrated circuit that is free from unnecessary electrical interference between lower layer circuits and lower layer circuits when used in micro-transfers. With the goal.

〔課題を解決するための手段〕[Means to solve the problem]

この発明における多層化マイクロ波集積回路は一方の面
上に回路が形成された複数個の半導体基板を上記半導体
基板の回路の少なくとも接地部以外の部分とは絶縁され
た状態で接地され几導体層を挾んで積層したものである
The multilayer microwave integrated circuit according to the present invention includes a plurality of semiconductor substrates each having a circuit formed on one surface, and a conductor layer that is grounded and insulated from at least a portion other than the ground portion of the circuit of the semiconductor substrate. It is made by sandwiching and stacking.

〔作用〕[Effect]

この発明における多層化マイクロ波集積回路は。 The multilayer microwave integrated circuit in this invention is.

接地した導体層が電磁界を避へいするため、下部層回路
と下部層回路との電気的干渉が無くなる。
Since the grounded conductor layer avoids electromagnetic fields, there is no electrical interference between the lower layer circuits and the lower layer circuits.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は、この発明の多層化マイクロ波集a回路を示す
断面図であり、半導体基板の回路が形成されている面を
それぞれ外側にして積層した場合を示している。(1a
)は下部層半導体基板、 (lb)は下部層半導体基板
、 (2a)は下部層半導体基板(1a)上に形成され
た下部層回路、 (2b)は下部層半導体基板(1b)
上に形成された下部層回路、(4)は下部層回路(2a
)と下部層回路(2b)の所定個所を結合させる接続線
、 (5a)(5b)は回路素子、 (6a)(6b)
は導体よ構成る線路、(7)は下部層半導体基板(1a
)と下部層半導体基板(1b)に挾まれて配置され、接
地された導体層である。なお、接続線(4)は回路のグ
ランド部を接続するもの以外は導体層(7)と絶縁され
ている。
FIG. 1 is a cross-sectional view showing a multilayer microwave integrated circuit according to the present invention, in which semiconductor substrates are stacked with the circuit-formed surfaces facing outward. (1a
) is the lower layer semiconductor substrate, (lb) is the lower layer semiconductor substrate, (2a) is the lower layer circuit formed on the lower layer semiconductor substrate (1a), (2b) is the lower layer semiconductor substrate (1b)
The lower layer circuit (4) formed on the lower layer circuit (2a
) and a predetermined part of the lower layer circuit (2b), (5a) (5b) are circuit elements, (6a) (6b)
(7) is a line composed of a conductor, and (7) is a lower layer semiconductor substrate (1a
) and the lower layer semiconductor substrate (1b), and is a grounded conductor layer. Note that the connecting wires (4) are insulated from the conductor layer (7) except for those connecting the ground portion of the circuit.

このようにM床された多層化マイクロ波集積回路ではマ
イクロ波帯で動作させた場合にも上部層IgJ路(2a
)を苑れる電流による電磁界と下部層回路(2b)を流
れる電流による電磁界は、それぞれの回路と接地された
導体層(7)との間で生じるため・下部層回路(2a)
と下部層回路(2b)との電気的干渉は無く、下部層回
路(2a)と下部層回路(2b)は接続線(4)により
所定の個所で結合がとられているため、全体として所望
の動作をする。なお・上記接続線(4)は下部層回路(
2a)と下部層回路(2b)との間の電気的干渉が主じ
難い部位、または、!気的干渉の影響が少ない部位に設
けられているので、動作に支障はない。また、この発明
の多層化マイクロ波集積回路では下部層回路(2a)と
下部層回路(2b)のそれぞれの線路と導体層(7)と
によりマイクロストリップ線路が構成されるため、従来
のモノリシックマイクロ波集槓回路設計法がそのまま適
用できる。
In such a multilayer microwave integrated circuit with an M floor, even when operated in the microwave band, the upper layer IgJ path (2a
) and the electromagnetic field due to the current flowing through the lower layer circuit (2b) are generated between each circuit and the grounded conductor layer (7). ・The lower layer circuit (2a)
There is no electrical interference between the lower layer circuit (2b) and the lower layer circuit (2b), and the lower layer circuit (2a) and the lower layer circuit (2b) are coupled at predetermined points by the connecting wire (4), so the desired overall result is achieved. perform the following actions.・The above connection line (4) is connected to the lower layer circuit (
2a) and the lower layer circuit (2b) where electrical interference is unlikely to occur, or! Since it is installed in a location that is less affected by atmospheric interference, there is no problem with its operation. Furthermore, in the multilayer microwave integrated circuit of the present invention, a microstrip line is constituted by the respective lines of the lower layer circuit (2a) and the lower layer circuit (2b) and the conductor layer (7). The wave collecting circuit design method can be applied as is.

第2図はこの発明の他の実施例を示す断面図でおり、下
部層回路(2a)または下部層回路(2b)中に高出力
増幅器等の高出力能動回路素子を含む場合を示す。第2
図において、 (6b1)は下部層回路(2b)中のグ
ランドとなる細路、(8)は高出力能動回路素子、(9
)は導体層(7)とグランドとなる線路(6b、)とを
接続する熱抵抗の小さい導体層である。
FIG. 2 is a sectional view showing another embodiment of the present invention, in which the lower layer circuit (2a) or the lower layer circuit (2b) includes a high output active circuit element such as a high output amplifier. Second
In the figure, (6b1) is a narrow path that becomes the ground in the lower layer circuit (2b), (8) is a high output active circuit element, (9
) is a conductor layer with low thermal resistance that connects the conductor layer (7) and the ground line (6b, ).

なお、他は第1図に示した実施例と同様である。The rest is the same as the embodiment shown in FIG.

また、第3図は第2図に示した多層化マイクロ波集積回
路の実装状態を示す断面図であり、バツケ−ジαOは導
体より成るグランドとなるベースσυ。
Further, FIG. 3 is a cross-sectional view showing the mounting state of the multilayer microwave integrated circuit shown in FIG. 2, and the bag αO is a base συ which becomes a ground made of a conductor.

ベースaυに設けられた入出力端子α2と接続された導
体部α3をそなえたセラミックよ構成る側板0→。
A side plate 0→ made of ceramic is provided with a conductor portion α3 connected to the input/output terminal α2 provided on the base aυ.

蓋α9から構成されておシ、多層化マイクロ波集積回路
αeに、その入出力端子がそれぞれ上記導体部a3と接
続され、下部層回路(2b)中のグランドとなる線路(
6b )、 (6b2)部がベースiI])に接するよ
う実装されている。多層化マイクロ波集積回路は上記の
ように実装されるため導体層(9)は導体層(7)を接
地させる。また導体層+91)に設けることにより回路
を動作させた時に高出力能動回路素子で発生する熱を導
体/1m (71→導体塊(9)→線路(sb 、 )
→ベースaυの熱抵抗の小さい経路で効率よくヒートシ
ンクとなるベースaυへ放熱することができ、高出力能
動回路素子を含む多層化マイクロ波集積回路を安定に動
作させられる。なお、上記導体層(9)は導体層(7)
と同様に接地されているため、電気的干渉に対する影響
はない。また、第4図は第2図に示す実施例における放
熱効果を更に高める場合の一実施例を示す断面図であシ
、導体塊(9)を導体層(7)から下部層半導体基板(
1a)内へ拡張し、高出力能動回路素子(8)の近傍に
及ぶようにしたものを示す。なお、高出力能動回路素子
(8)がFETの場合にはITのソース端子と導体層(
9)とを直接接触させて放熱を良くすることも可能であ
る。また、上記実施例では導体層(9)と導体層(7)
とを接続して導通させ、導体層(9)に導体層(7)の
接地の役割もさせる場合について示したが、導体層(7
)の接地は別途性ない、導体層を導体層(7)に接続し
ない場合も同様の効果が得られる。
It consists of a lid α9, and a multilayer microwave integrated circuit αe, the input and output terminals of which are connected to the conductor part a3, respectively, and a line (2b) serving as a ground in the lower layer circuit (2b).
6b) and (6b2) are mounted so that they are in contact with the base iI]). Since the multilayer microwave integrated circuit is mounted as described above, the conductor layer (9) grounds the conductor layer (7). In addition, by providing the conductor layer +91), the heat generated by high-output active circuit elements when the circuit is operated is absorbed by the conductor/1m (71 → conductor block (9) → line (sb, )
→ Heat can be efficiently radiated to the base aυ, which serves as a heat sink, through a path with low thermal resistance of the base aυ, and a multilayer microwave integrated circuit including high-output active circuit elements can be stably operated. Note that the conductor layer (9) is the conductor layer (7).
Since it is similarly grounded, there is no effect on electrical interference. Furthermore, FIG. 4 is a sectional view showing an embodiment in which the heat dissipation effect in the embodiment shown in FIG. 2 is further enhanced.
1a), which extends into the vicinity of the high-power active circuit element (8). In addition, when the high output active circuit element (8) is an FET, the source terminal of the IT and the conductor layer (
It is also possible to improve heat dissipation by bringing them into direct contact with 9). In addition, in the above embodiment, the conductor layer (9) and the conductor layer (7)
The case where the conductor layer (9) also plays the role of grounding the conductor layer (7) is shown, but the conductor layer (7)
) is not separately grounded, and the same effect can be obtained even if the conductor layer is not connected to the conductor layer (7).

また、第5図はこの発明の他の実施例を示す断面図であ
シ、下部j−半導体基板(1b)では下部層回路(2b
)を導体層(7)側にし、下部層(ロ)路(2b)と導
体層(7)の間に絶縁体層−を依んで積層した場合を示
している。図において、(I8は下部層半導体基板(1
b〕の回路を形成しない面に設は友接地用の導体パター
ンであり、前述の第3図に示したと同様に多層化マイク
ロ波集積回路を実装する場合等に導体層(7)に接続さ
れる導線α!Jを介して導体層(7)全容易に接地する
役割を果たす。なお、他は第1図と同一の物を示す。上
記実施例においても接地された導体層(7)により上部
層回路(2a)と下部層回路(2b)との電気的干渉が
防止されるとともに、接続線(4)によシ所定の個所で
結合されているので全体として所望の動作をする。なお
、上記実施例においても上部層回路(2a)及び下部層
回路(2b)はいずれも導体層(7)との間でマイクロ
ストリップ線路を構成しておシ、従来のモノリシックマ
イクロ波集積回路設計法がそのまま適用できる。
Further, FIG. 5 is a sectional view showing another embodiment of the present invention, in which the lower layer circuit (2b) is
) is placed on the conductor layer (7) side, and an insulator layer is laminated between the lower layer (b) and the conductor layer (7). In the figure, (I8 is the lower layer semiconductor substrate (1
A conductive pattern for grounding is provided on the surface on which no circuit is formed, and is connected to the conductive layer (7) when a multilayer microwave integrated circuit is mounted, as shown in Fig. 3 above. Leading wire α! The conductor layer (7) through J serves to easily ground the entire conductor layer (7). The other parts are the same as in FIG. 1. In the above embodiment as well, the grounded conductor layer (7) prevents electrical interference between the upper layer circuit (2a) and the lower layer circuit (2b), and the connecting wire (4) Since they are combined, they perform the desired operation as a whole. In the above embodiment, both the upper layer circuit (2a) and the lower layer circuit (2b) constitute a microstrip line with the conductor layer (7), which is different from the conventional monolithic microwave integrated circuit design. The law can be applied as is.

また、上記実施例では下部層半導体基板(1b)側の回
路と導体層(7)との間に絶縁体層r1ηを設けた場合
について説明したが、これに限らず下部層半導体基板(
1a)側にも同様の構成を適用でき、同様の効果が得ら
れる。
Further, in the above embodiment, the case where the insulating layer r1η was provided between the circuit on the lower layer semiconductor substrate (1b) side and the conductor layer (7) was explained, but the present invention is not limited to this.
A similar configuration can be applied to the 1a) side, and similar effects can be obtained.

また、第6図及び第7図はこの発明のさらに他の実施例
を示すもので、第6図はその分解斜視図。
Further, FIGS. 6 and 7 show still another embodiment of the present invention, and FIG. 6 is an exploded perspective view thereof.

第7図はその断面図である。この実施例では下部層半導
体基板(1b)にこの発明による掘り込み■の中に下部
層回路(2b)を形成して積層した場合を示している。
FIG. 7 is a sectional view thereof. This embodiment shows a case in which a lower layer circuit (2b) is formed and laminated in a recess (2) according to the present invention on a lower layer semiconductor substrate (1b).

なお、他は第5図と同一の物を示す。第8図は第6図ま
たは第7図の掘シ込み翰部分の拡大断面図でアシ、線路
(6b)と導体層(7)とがそれぞれストリップ導体と
接地導体となりマイクロストリップ線路を形成する様子
を示してお夛。
The other parts are the same as those shown in FIG. 5. Figure 8 is an enlarged cross-sectional view of the dug-out part of Figure 6 or Figure 7, showing how the reed, line (6b) and conductor layer (7) become a strip conductor and a ground conductor, respectively, forming a microstrip line. Please show me.

図中の矢印は電界をモデル的に表わしている。上記実施
例では下部層半導体基板(1b)側に掘り込み(1)を
設けた場合を示したが、これに限らず下部層半導体基板
(1a)側にも同様の構成を適用でき。
The arrows in the figure represent the electric field as a model. In the above embodiment, the case where the recess (1) is provided on the lower layer semiconductor substrate (1b) side is shown, but the present invention is not limited to this, and a similar structure can be applied to the lower layer semiconductor substrate (1a) side.

いずれも前記同様の効果が得られる。また、上記のよう
に半導体基板に掘り込み(1)を設けた構造の場合には
マイクロストリップ線路以外にも方形同軸線路、コプレ
ナ線路等1種々の線路形成を実現でき1回路設計の自由
度が増加する効果がある。
In either case, the same effects as described above can be obtained. In addition, in the case of the structure in which the recess (1) is provided in the semiconductor substrate as described above, various line formations such as rectangular coaxial line and coplanar line can be realized in addition to the microstrip line, increasing the degree of freedom in circuit design. It has an increasing effect.

次に2〜30例を用い説明する。Next, explanation will be given using 2 to 30 examples.

第9図及び第10図は第6図またに第7図の掘り込み翰
部分の拡大断面図であυ、第9図は方形同軸線路を形成
した実施例を示し、第10図はコプレナ線路を形成した
実施例を示す。第9図及び第10図においてQυはスト
リップ導体、(至)は掘り込みω内に設けられた導体層
(7)に接続された接地導体、 c!:lは掘夛込み(
至)内に充填された誘電体でろ92図中の矢印は電界を
モデル的に表わしたものでおる。なお、誘電体(ハ)は
複数種類を用いても。
FIGS. 9 and 10 are enlarged sectional views of the dug-out part of FIGS. 6 and 7, FIG. 9 shows an example in which a rectangular coaxial line is formed, and FIG. An example is shown below. In FIGS. 9 and 10, Qυ is a strip conductor, (to) is a ground conductor connected to the conductor layer (7) provided in the recess ω, and c! :l includes digging (
92 The arrows in the figure represent the electric field as a model. Note that multiple types of dielectric materials (c) may be used.

また、無くてもよい。Also, it may be omitted.

上記実施例に示すようにス) IJツブ導体を接地導体
で囲んだ構造の線路を用いることによQ、同一半導体基
板上に形成されている隣接する線路間の電気的干渉を十
分防止することができるため。
As shown in the above embodiments, by using a line in which the IJ tube conductor is surrounded by a ground conductor, electrical interference between adjacent lines formed on the same semiconductor substrate can be sufficiently prevented. Because it can be done.

回路配線に自由度が増し、さらに回路設計が容易となる
効果を有する。
This has the effect of increasing the degree of freedom in circuit wiring and further facilitating circuit design.

なお1以上の第5図及び第6図または第7図に示した実
施例においては放熱に関して言及していないが、いずれ
も第2図及び第3図さらに第4図に実施例を示して説明
し九のと同様の手段が適用でき、放熱効果を得られるこ
とは自明である。また2以上で述べた上部I−半導体基
板(1a)と下部層半導体基板(1b)の材料は同一で
おっても、異なっていてもよい。さらに2以上の実施例
では導体層として板状に形成された導体を例示したが。
Although heat radiation is not mentioned in one or more of the embodiments shown in FIG. 5 and FIG. 6 or FIG. 7, the explanation is given by showing the embodiments in FIGS. It is obvious that the same means as above can be applied and a heat dissipation effect can be obtained. Further, the materials of the upper I-semiconductor substrate (1a) and the lower layer semiconductor substrate (1b) described above may be the same or different. Furthermore, in two or more embodiments, a plate-shaped conductor was used as the conductor layer.

これに限らす網目状等に形成された導体を用いてもよい
The conductor is not limited to this, but a conductor formed in a mesh shape or the like may also be used.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば回路が形成された下部
層半導体基板と下部層半導体基板を、上記半導体基板の
回路の少なくとも接地部以外の部分とは絶縁された状態
で接地された導体層を挾んで積層して多1−化マイクロ
波集積回路f:構戊したので、導体層が電磁界を遮へい
し、下部層回路と下部層回路との間の不要な電気的干渉
が防げる。
As described above, according to the present invention, a lower layer semiconductor substrate on which a circuit is formed and a lower layer semiconductor substrate are connected to a grounded conductor layer insulated from at least a portion other than the ground portion of the circuit of the semiconductor substrate. Since the multi-layer microwave integrated circuit f: is constructed by stacking the two layers in between, the conductor layer shields the electromagnetic field and prevents unnecessary electrical interference between the lower layer circuit and the lower layer circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す断面図、第2図はこ
の発明の他の実施例を示す断面図、第3図は第2図に示
したこの発明の多層化マイクロ波集積回路の実装状態を
示す断面図、第4図はこの発明のさらに他の実施例を丞
す断面図、第5図はこの発明のさらに他の実施例を示す
断面図、第6図はこの発明のさらに他の実施例を示す分
解斜視図、第7図はメロ図に示した実施例の断面図、第
8図は第6図1几は第7図に示した実施例の掘り込み部
分の拡大断面図、第9図及び第10図は第6図または第
7図に示した実施例の掘シ込み部分の拡大断面図であり
、第9図は方形同軸線路を形成した実施例を示す拡大断
面図、第10図はコプレナ線路を形成した実施例を示す
拡大断面図、第1)図は従来の多層化集積回路を示す断
面図である。図において、 (la) h下部層半導体
基板。 (1b)は下部層半導体基板、 (2a)は下部層回路
。 (2b)は下部層回路、(3)はポリイミドを用いた絶
縁体層、(4)は接続線、 (5a)(5b)は回路素
子。 (6a) (6b)は線路、(6b1)はゲランドとな
る線路、(7)は導体層、(8)は窩出力能動回路素子
、(9)は導体層、α1はパッケージ、αυはペース、
卸は入出力端子、α1は導体部、α4は側板、αりは蓋
、αQは多層化マイクロ波集積回路、a7)は絶縁体J
θ、α榎は導体パターン、+1’lは畳縁、(イ)は掘
り込み、Qυはストリップ導体、器は接地導体、@は誘
電体である。 なお、谷図中同−符号は同一または相当部分をボす。
FIG. 1 is a sectional view showing one embodiment of the invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3 is the multilayer microwave integrated circuit of the invention shown in FIG. FIG. 4 is a sectional view showing still another embodiment of the invention, FIG. 5 is a sectional view showing still another embodiment of the invention, and FIG. 6 is a sectional view showing still another embodiment of the invention. Further, an exploded perspective view showing another embodiment, FIG. 7 is a sectional view of the embodiment shown in the melodic diagram, and FIG. 8 is an enlarged view of the dug portion of the embodiment shown in FIG. 7. 9 and 10 are enlarged sectional views of the dug portion of the embodiment shown in FIG. 6 or 7, and FIG. 9 is an enlarged view of the embodiment in which a rectangular coaxial line is formed. 10 is an enlarged sectional view showing an embodiment in which a coplanar line is formed, and FIG. 1) is a sectional view showing a conventional multilayer integrated circuit. In the figure, (la) h lower layer semiconductor substrate. (1b) is a lower layer semiconductor substrate, (2a) is a lower layer circuit. (2b) is a lower layer circuit, (3) is an insulator layer using polyimide, (4) is a connection line, and (5a) and (5b) are circuit elements. (6a) (6b) is the line, (6b1) is the line that becomes Guerande, (7) is the conductor layer, (8) is the socket output active circuit element, (9) is the conductor layer, α1 is the package, αυ is the pace,
The wholesaler is the input/output terminal, α1 is the conductor part, α4 is the side plate, α is the lid, αQ is the multilayer microwave integrated circuit, a7) is the insulator J
θ and α are the conductor patterns, +1'l is the tatami edge, (a) is the digging, Qυ is the strip conductor, vessel is the ground conductor, and @ is the dielectric. Note that the same symbols in the valley diagram indicate the same or corresponding parts.

Claims (4)

【特許請求の範囲】[Claims] (1) 少くとも一方の面上に回路が形成された半導体
基板が,各半導体基板の回路の所定の個所を電気的に結
合させて,複数個積層され,上記各半導体基板間にその
半導体基板の回路の少なくとも接地部以外の部分とは絶
縁された状態で接地された導体層が設けられたことを特
徴とする多層化マイクロ波集積回路。
(1) A plurality of semiconductor substrates having a circuit formed on at least one surface are stacked by electrically coupling predetermined parts of the circuit on each semiconductor substrate, and the semiconductor substrate is placed between each of the semiconductor substrates. 1. A multilayer microwave integrated circuit characterized in that a conductor layer is provided which is grounded and insulated from at least a portion other than the ground portion of the circuit.
(2) 少くとも一方の面上に回路が形成された半導体
基板を,回路が形成されている面をそれぞれ外側にして
積層した請求項1記載の多層化マイクロ波集積回路。
(2) The multilayer microwave integrated circuit according to claim 1, wherein semiconductor substrates each having a circuit formed on at least one surface are stacked with the surface on which the circuit is formed facing outward.
(3) 少くとも一方の面上に回路が形成された半導体
基板の少なくとも一枚を回路が形成されている面を内側
にし,回路と導体層の間に絶縁体層を挾んで積層した請
求項1記載の多層化マイクロ波積層回路。
(3) A claim in which at least one semiconductor substrate with a circuit formed on at least one surface is stacked with the surface on which the circuit is formed facing inside, with an insulating layer interposed between the circuit and the conductor layer. 1. The multilayer microwave laminated circuit according to 1.
(4) 積層された半導体基板の少なくとも一枚では,
回路が導体層に接する半導体基板面の所定位置に設けら
れた堀り込み部に形成されている請求項1記載の多層化
マイクロ波積層回路。
(4) At least one of the stacked semiconductor substrates,
2. The multilayer microwave laminated circuit according to claim 1, wherein the circuit is formed in a recessed portion provided at a predetermined position on the surface of the semiconductor substrate in contact with the conductor layer.
JP1093784A 1989-04-13 1989-04-13 Multilayered microwave integrated circuit Pending JPH02271656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1093784A JPH02271656A (en) 1989-04-13 1989-04-13 Multilayered microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1093784A JPH02271656A (en) 1989-04-13 1989-04-13 Multilayered microwave integrated circuit

Publications (1)

Publication Number Publication Date
JPH02271656A true JPH02271656A (en) 1990-11-06

Family

ID=14092040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1093784A Pending JPH02271656A (en) 1989-04-13 1989-04-13 Multilayered microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPH02271656A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567919A (en) * 1991-07-25 1993-03-19 Nec Corp Millimeter microwave transmission/reception module
US5196920A (en) * 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JPH06125208A (en) * 1992-10-09 1994-05-06 Mitsubishi Electric Corp Microwave integrated circuit and its production
EP0740343A2 (en) * 1995-04-24 1996-10-30 Matsushita Electric Industrial Co., Ltd. Structure of chip on chip mounting preventing crosstalk noise
JP2002289774A (en) * 2001-03-27 2002-10-04 Furukawa Electric Co Ltd:The Multi-layer structure semiconductor, device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567919A (en) * 1991-07-25 1993-03-19 Nec Corp Millimeter microwave transmission/reception module
US5196920A (en) * 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JPH06125208A (en) * 1992-10-09 1994-05-06 Mitsubishi Electric Corp Microwave integrated circuit and its production
EP0740343A2 (en) * 1995-04-24 1996-10-30 Matsushita Electric Industrial Co., Ltd. Structure of chip on chip mounting preventing crosstalk noise
EP0740343A3 (en) * 1995-04-24 2000-04-05 Matsushita Electric Industrial Co., Ltd. Structure of chip on chip mounting preventing crosstalk noise
JP2002289774A (en) * 2001-03-27 2002-10-04 Furukawa Electric Co Ltd:The Multi-layer structure semiconductor, device

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