JPH02270430A - Digital signal transmission equipment - Google Patents

Abstract

PURPOSE:To improve an error detection capability of a data and to attain error correction by generating a code detecting or correcting an error of plural bits of digital information signal among digital signals in one unit, storing the signal to part of an auxiliary signal or a standby signal and sending the result. CONSTITUTION:A synthesis circuit 3 in a transmitter A rearranges a data fed to a digital audio signal input terminal 1 and a control signal supplied to a control signal input terminal 2 in a prescribed order, a coding circuit 4 generates an error detection and correction code and adds the result to a (Check) area. Moreover, a modulation synchronizing addition circuit 5 generates and adds at first a parity check bit (P), applies a biphase mark modulation, adds a preamble (SYNC) as a synchronizing signal and outputs the result as a formatting data. A synchronization detection/demodulation circuit 7 in a receiver B demodulates a data sent via a transmission line 6, and the demodulated data is subject to error detection by using the parity check bit (P). A decoding circuit 8 uses the error correction code check to correct an error caused in the transmission line 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal transmission device comprising a digital signal transmitting device and a receiving device that handle digital signals to transmit signals such as digital audio. be.

[Prior Art] Figure 9 shows a configuration diagram of a signal format disclosed in ``CP-34Or Digital Audio Interface'' published by the Electronics Industries Association of Japan (EIAJ) as a general format for transmitting digital audio data. As shown in the figure, one frame is a left channel (Lch) with a preamble of B or M.
The preamble consists of two subframes containing the right channel (Rch) audio data of W.
Each subframe has 32 time slots from O to 31,
In other words, it consists of 32 bits. The first 4 bits of each subframe are a synchronization preamble signal (SYNC), and the 0th-order 4 bits, which also serve as a subframe identification signal and a synchronization signal, are reserved bits, and are used as audio auxiliary information (AUX) or It is used for expanding audio data, which will be described later.

The next 20 bits are audio sample bits,
For example, when transmitting 16-bit audio data like a CD, it is stored in the (Dl) part, and the (DO) part is set to the "0" level. The last 4 bits of the subframe are control signals, and (V) is a validity flag. If the logic is "O", the audio data is correct, and if it is 'l', the audio data has been corrected. Show that.

(U) is a user data bit, and time information, a song start signal, etc. are transmitted. (C) is a channel status bit, and information such as sampling frequency, presence or absence of copy inhibition, presence or absence of emphasis is transmitted as a control signal related to audio data. Further, (P) is a parity bit, and this bit is determined so that the numbers of 28 bits IIO11 excluding the synchronous preamble signal (SYNC) and "loo" are even numbers.

On the transmission path, each data except the synchronous preamble signal (SYNC) is modulated using the biphase mark method, and the synchronous preamble signal (SYNC) can be detected by adopting a bit pattern that does not appear in modulation using the biphase mark method. It is possible.

[Problems to be Solved by the Invention] Since the transmission format of a conventional digital signal transmission device has the above-described configuration, it has the following problems.

That is, in the transmission of digital signals, bit errors in the signal occur due to disturbances such as external noise on the transmission path and signal attenuation during transmission. Therefore, error detection codes and error correction codes are used to detect or correct this error, but in the r digital interface format described above, a 1-bit parity bit (P) is used for error detection. Since it only detects an odd number of bit errors within an L subframe, it has no correction ability at all, and even if it can detect a bit error, it only corrects it. Therefore, if the transmission conditions are poor, such as when the transmission path is long, noise may occur in the reproduced audio signal or audio may be cut out. Furthermore, if digital data other than audio data is to be transmitted in this format in the future, this will pose a major obstacle in terms of reliability.

This invention was made in order to solve the above-mentioned problems, and provides a digital signal transmission device that not only improves the ability to detect errors in data, but also makes it possible to correct errors, thereby demonstrating extremely high reliability. The purpose is to provide.

[Means for Solving the Problems] A digital signal transmission device according to the present invention transmits data within one unit of a digital signal consisting of a multi-bit digital information signal and related auxiliary signals or preliminary signals for bit extension of the digital information signal. A digital signal transmitter configured to generate a code for detecting or correcting an error in the digital information signal, store and transmit the code, and a code stored corresponding to the transmitter. A digital signal receiving device configured to perform error detection or error correction of a digital information signal.

Further, the digital signal transmission device according to the invention described in claim 2 provides a unit of digital signal consisting of a multi-bit digital information signal, an auxiliary signal related thereto, and a 1-bit parity bit for detecting errors in the auxiliary signal. A digital signal transmitting device configured to generate a new code for detecting or correcting an error in the digital information signal, add this code, and transmit the new code, and the new code corresponding to the transmitting device. The present invention is characterized by comprising a digital signal receiving device configured to perform error detection or correction of a digital information signal using the added code.

[Operation] According to the present invention, within one unit of digital signal,
A code for detecting or correcting errors in a multi-bit digital information signal is generated, and this is stored as part of the auxiliary signal or preliminary signal and transmitted. On the receiving side, the stored code is used to detect or correct multiple errors. In the transmission of digital signals, it is possible to decode bits to detect or correct errors in the digital information signal.
Signal error detection ability and error correction ability can be improved.

Further, according to the invention as set forth in claim 2, a new code for detecting or correcting an error in a plurality of bits of digital information signal within one unit of digital signal string is generated and added, and while the new code is transmitted, the received On the side, the newly added error detection or correction code can be used to decode the multi-bit digital information signal to perform error detection or correction. It is possible to improve signal error detection ability and error correction ability during transmission.

[Embodiment of the Invention] An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing an example of the data structure of a subframe in a signal format in a digital signal transmission device according to an embodiment of the present invention. is and t, the bits of the audio sample (Dl), Figure 9 (AU
X) The 8 bits of the m-area check (DO) area are used as an area (Check) for storing a new code. At this time, the codes include 4 bits of the synchronous preamble signal (SYNC) area, 8 bits of the (Check) area, a validity flag (V), and a user data pin (U) out of the 32 bits of the subframe. , is an error detection code or error correction code generated for <17 bits of data excluding 3 bits of channel status bits (C), and is an error detection code or error correction code generated for data of <17 bits excluding 3 bits of channel status bits (C), and the parity bit at the end of the subframe (
P) is each bit (Check), (DI), (V
), (U).

It is generated for the 27-bit data in (C). Above (C
The generally known code for storing in the heck area is CRCC (Cyclic Redundant Code).
Various codes can be used, such as ancyCheck code) and BCH code.

Fig. 2 is a diagram showing another example of the data structure of a subframe, in which the bits of an audio sample are
c7) 20 bits, Figure 9 77) 4 bits of the (AUX) area are used as the (Check) area. 21-bit data excluding 4 bits in the synchronous preamble signal (SYNC) area, 4 bits in the (Check) area, and 3 bits in the control signal (7) (V), (U), and (C) areas. There is an error detection code or error correction code that is generated for In addition, 16~
Do not use 20 audio sample bits (
It is also possible to set the DO) area to logic "OII" and make the (Check) area 4 bits.

Next, a digital signal transmitting device and a receiving device as a signal transmitting device using the above-described transmission format will be explained.

FIG. 3 is a block diagram showing a schematic configuration diagram of a digital signal transmitting device and a receiving device according to an embodiment of the present invention. The supplied 16-bit length data and the m, (U), and (C) bit data supplied to the control signal input terminal (2) are rearranged in a predetermined order. (4) is an encoding circuit, and this encoding circuit (4) generates an 8-bit error detection and correction code for a total of 17 bits of data.
:heck) area to generate 25-bit serial data. (5) is the modulation/synchronization addition circuit (5),
While the above 25-bit serial data is input, the modulation Φ synchronization addition circuit (5) first generates and adds a parity check (CP), then biphase mark modulation, and then outputs it as a synchronization signal. 0 or more terminals (1), (2) and each circuit (3) that are output as data formatted as shown in Figures 1 and 2 with a preamble (SYNIII:) added.
, (4), and (5) constitute a digital signal transmitter (A).

(6) is a transmission line, which uses coaxial cable or optical fiber cable. (7) is a synchronization detection/demodulation circuit, into which data transmitted via the transmission line (6) is input. Here, a synchronous preamble signal (SYNC) is detected and a clock is extracted, and demodulation is performed using this clock. Error detection is performed on the demodulated data using a parity check pit (P). (8)
is a decoding circuit, and this decoding circuit (8) uses an error correction code check to correct errors that occur on the transmission path (8), and also detects errors that cannot be corrected. A flag for performing processing such as interpolation is output accordingly.

(8) is a separation circuit in which the digital audio sample and the control signal are separated and outputted from respective output terminals (to) and (tl).

Each of the above circuits (7), (8), (8) and the terminal (to
) and (11) constitute a digital signal receiving device (B).

Below, a digital signal transmitting device (A) and a receiving device (B
) will be explained in detail. Here, the shortened B CH(2
7, 19). This is B CH (
31, 23) shortened by 4 bits, and has the ability to correct one error and detect two errors. The generator polynomial is (X+1)(X'+d)-f+ X7+ )(4+
It is indicated as XJ+X+1.

FIG. 4 is a block diagram showing a specific configuration of the encoding circuit (4) included in the digital signal transmitting device (A).
In the figure, (411) is an input terminal to which the output from the synthesis circuit (3) is supplied, and audio samples and the like are serially input. 8 flip-flops (hereinafter referred to as FF) (412) to (419) 5J: and 5 (7) EX-OR game) (420) to (424)
) constitutes a division circuit and has a function of dividing input data by the above-mentioned generator polynomial. (428) is a register that holds the data divided by the above-mentioned division circuit. During this period, the switches (42B) and (427) are turned upward. After the 17-bit input data is shifted, the remaining data in F F (412) to (419) becomes the code, so the switch (42Et) is used.

(427) is pushed downward, and the 8-bit code is sequentially outputted via the output terminal (429). After that, the switch (427) is turned upward, and the 17-bit data in the register (42B) is output following the code, and the modulation and
It is sent to the synchronization addition circuit (5).

- Figure 5 shows the decoding circuit (8) in the receiving device (B).
) is a block diagram showing the configuration of (811
) is an input terminal to which received and demodulated data is serially supplied. (812) is a register that holds the 8-bit correction code that first enters the input terminal (811). (814) and (815) are division circuits, and when data following the 8-bit correction code is input, 17-bit data is supplied via a switch (813) that falls to the left in the figure. After this 17-bit data is supplied, the switch (813) is turned to the right side in the figure, and the correction code held in the register (812) is input to the division circuits (814) and (815). Ru. The division circuits (814) and (815) divide the input signal by polynomials of (X″+X3+1) and (×+1), respectively, and divide the input signal by the polynomials of (X″+X3+1) and (×+1), respectively.
Whether the bit correction code is divisible or not and the remainder value if not divisible are output as information. (8
1B) is a judgment circuit, and this judgment circuit (81B) judges whether there is no error, a 1-bit error, or a 2-bit error based on the results of division by the division circuits (814) and (815). In this case, the error is corrected by inputting the value of the erroneous bit to one of the EX-OR gates (818) and inverting it.

(81?) is a register, and this register (817) is for delaying bits until error correction is performed, and its output is input to the other side of the EX-OR gate (818).

The 1-bit corrected data is sent to the output terminal (819
) and sent to the next separation circuit (8). Further, in the case of a 2-bit error, flag information is outputted via the output terminal (82G). When this flag information is output, a correction circuit (not shown) included in the separation circuit (8) corrects the data to prevent abnormal noise from occurring in the audio signal.

In addition, although the example using the BCH code was shown in the said Example, the code used is not limited to this as mentioned above.

In addition, in this embodiment, since a correction code is added after the information signal, the decoding circuit of the receiving device is configured to temporarily hold the previously input correction code in a register, but depending on the code, when receiving It is also possible to perform corrections by sequentially calculating from the correction code.

Also, as shown in FIG. 2, it is clear that some of the 8 bits can be used for a new correction code area, and the rest can be used for other purposes.

Next, another embodiment of the invention will be described based on the drawings.

FIG. 6 shows a data configuration diagram of a new subframe format among signal formats in a digital signal transmission device according to another embodiment of the present invention. In the same figure, the difference from the subframe shown in FIG. , add an 8-bit code as a new (Check) area,
The point is that the bit length of the subframe is expanded to 40 bits. The code added to this (Check) area is newly generated for 28-bit data excluding the synchronization preamble signal (SYNC), and the types of codes are as follows:
CRC with only high error detection ability (C7c CR)
Various codes can be used, such as an edundancy check code and a BCH code with detection and correction capabilities. The modulation method, synchronization signal pattern, etc. are all the same as the format shown in FIG.

The frame frequency in the above transmission method is equal to the sampling frequency of audio data, and the highest bit frequency (transmission rate) on the transmission path is slightly higher than the format shown in Figure 9. If the sampling frequency is (Fs), then (180
Note that the number of bits in the (Check) area is not limited to 8 bits and can take any value.

FIG. 7 is a block diagram showing the schematic configuration of a digital signal transmitting device (A) and a receiving device (B) as digital signal transmitting devices that use the format shown in FIG. As such, the transmitting device (A)
is the same as the configuration shown in Figure 3, with input terminals (1) and (2
), a combining circuit (3), an encoding circuit (0), and a modulation/synchronization addition circuit (5).The difference from FIG. Generate an 8-bit error detection or error correction code from the bit data and add this after the 28-bit data,
This is the point where the data is sent to the modulation/synchronization addition circuit (5) as a series of subframe data excluding (SYNC) in FIG.

Furthermore, since the transmission path (8) and the receiving device (B) have the same configuration as shown in FIG. 3, the same reference numerals are given to the corresponding parts and detailed explanation thereof will be omitted.

Next, the shortened BCH (38, 28
) Digital signal transmitter using code (A)
The configurations of the encoding circuit (4) included in the receiver (B) and the decoding circuit (8) included in the receiver (B) will be described. Here, the above error correction code is BCH (83, 55) shortened by 27 bits, and the shortened data part can be treated as "ON data". , and has the capability of detecting two errors, and the generating polynomial is expressed by the following equation.

(X+1) (X'+Xj+1) -X9+ X7+
X'+ 1 < 1 ÷ Since the remaining 8 bits of data serve as a code, the remaining 8 bits of data are added to the 28 bits of data and output.

On the other hand, the decoding circuit (8) is as shown in FIG.

A register (817) and two division circuits (814), (
815), an error determination circuit (81B), and an EX-5R gate (81B). Then, the serial data supplied to the input terminal (811) is transmitted to the register (811).
17) and two division circuits (814) and (815). These division circuits (814) and (815) convert the input data into (xq+x'◆1) and (X+1), respectively.
If there are no errors in the input data, the input data can be divided by any polynomial. The remainder information resulting from this division is sent to the error determination circuit (81B), and it is determined whether there is no error, 1 bit error, or 2 bit error.If it is a 1 bit error, it is delayed via the register (817). Correction is performed by inverting the bits at a predetermined position of the data obtained by using an EX-OR gate (81fl). The corrected data is output via the output terminal (819), and in the case of a 2-bit error, flag information is output via the output terminal (820). When this flag is output, the separation circuit (13
) includes a correction circuit (not shown) that performs corrections such as pre-holding to prevent abnormal sounds and noise from occurring in the audio signal.

Although the BCH code is used as a new code in the other embodiments described above, the code is not limited to this as described above, and the bit length of the code is also arbitrary.

Furthermore, the above error detection or correction code does not need to be generated for all data except the synchronization preamble signal (SYNC) in a subframe; for example, it may detect or correct errors only in audio samples. You can also get it.

Furthermore, although the placement of the above-mentioned code within a subframe is not limited to the last part of the subframe, it is generally preferable to place it at the last part of the subframe in the process of code generation and decoding to simplify the circuit configuration. It is desirable because it can be done.

Further, in each of the above embodiments, the present invention is applied to the transmission of digital audio signals, but the present invention may be applied to the transmission of any other digital information signals.

[Effects of the Invention] As described above, according to the present invention, it is possible to improve the error detection ability and error correction ability of data such as digital audio interface format without increasing the transmission rate, so it is highly reliable. It is possible to achieve high-speed digital data transmission.

Further, by transmitting a signal with a new code generated and added to a fixed format, data error detection ability and error correction ability can be further improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a signal format in a digital signal transmission device according to an embodiment of the present invention, FIG. 2 is a block diagram showing another example of the signal format,
FIG. 3 is a block diagram showing the configuration of a digital signal transmitting device and a receiving device according to an embodiment of the present invention, FIG. 4 is a block diagram showing a specific configuration of an encoding circuit included in the digital signal transmitting device, and FIG. FIG. 5 is a block diagram showing a specific configuration of a decoding circuit included in a digital signal receiving device, FIG. 6 is a configuration diagram of a signal format according to another embodiment of the present invention, and FIG. FIG. 8 is a block diagram showing the configuration of a decoding circuit included in the receiving device shown in FIG. 7, and FIG. FIG. 2 is a configuration diagram of a signal format of a video interface format. (4)... Encoding circuit, (8)... Transmission line, (8)
... decoding circuit, (A) ... transmitter, (B) ...
・Receiving device. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A synchronization signal is added to the beginning of a unit of signal consisting of a multi-bit digital information signal and an auxiliary signal related to this digital information signal or a preliminary signal for bit extension of the digital information signal. A digital signal transmission device comprising a digital signal transmission device configured to transmit a digital signal and a digital signal reception device configured to receive and demodulate a unit of digital signal transmitted by the transmission device. The digital signal transmitting device includes an encoding means for generating a code for detecting or correcting an error in a plurality of bits of the digital information signal within the one unit digital signal, and a code generated by the encoding means for transmitting the code to the above-mentioned auxiliary unit. and means for transmitting the signal by storing it in a part of the auxiliary signal or the preliminary signal, and the digital signal receiving apparatus uses the error detection or error correction code stored in the part of the auxiliary signal or the preliminary signal to detect the error. A digital signal transmission device comprising a decoding means for detecting or correcting an error in a digital information signal. (2) A synchronization signal is added to the beginning of a unit string signal consisting of a multi-bit digital information signal, an auxiliary signal related to this digital information signal, and a 1-bit parity bit for detecting errors in the auxiliary signal. A digital signal transmitting device configured to transmit a unit digital signal string, and a digital signal receiving device configured to receive and demodulate the unit digital signal string transmitted by the transmitting device. The digital signal transmitting device generates a new code for detecting or correcting an error in a multi-bit digital information signal within the one unit digital signal string, and transmits the new code to one unit of the signal string. comprises an encoding means to add to the
Further, the digital signal receiving device is a digital signal transmitting device characterized in that the digital signal receiving device includes a decoding means for detecting or correcting an error in the digital information signal using the newly added error detection or correction code. .