JPH02270196A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prepare an area where data cannot be rewritten, and to completely protect the data from being erroneously written by providing a means which selectively rewrites only one part of the storage area of a storage element. CONSTITUTION:A memory matrix is divided into an area M10 rewritable once and an area M20 rewritable for plural times. To write the data to respective memory cells corresponding to the respective areas M10 and M20, write circuits 9 and 10 are provided. Further a control circuit 110 permits data write to the memory M10 only when a control signal at an 'H' level is applied. Thus even when the storage element is erroneously set in a write mode, since the rewritable area is limited, the data in the unrewritable area can be prevented from being destroyed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including an electrically rewritable nonvolatile semiconductor as a memory element.

[Prior Art] An EEPROM as an electrically rewritable non-volatile semiconductor memory device applies 20V to corresponding memory cells according to binary information according to a write mode signal given from a controller. When a high voltage is applied, the threshold value of the memory cell changes, charge is injected, and information is written. There are two ways to apply high voltage to memory cells: directly applying it from the power supply to the external terminal provided on each memory cell, and using a step-up circuit inside the IC to apply the normal applied voltage of 5V.
There is a method of increasing the pressure and applying it. As an example of the latter,
There is one described in JP-A-63-7599.

FIG. 5 is a block diagram showing the overall structure of a conventional EEFROM. Referring to FIG. 5, clock pulses are applied to input register 101, and data and addresses are serially input. Input register 101 serially reads data and addresses in response to clock pulses, loading data into data register 103 and loading addresses into address register/decoder 104. The clock pulse is generated by the timing generation circuit 102
The timing generation circuit 102 generates a timing signal in response to the clock pulse and supplies it to the mode register 105. Mode register 105 is provided for loading a write mode signal or an erase mode signal. The write mode signal or erase mode signal loaded into mode register 105 is applied to control circuit 1.

The data loaded into data register 103 and the address loaded into address register/decoder 104 are provided to memory cell 100.

A write mode signal or an erase mode signal is applied to the memory cell 100 from the control circuit 1. The write mode signal is also given to the boost circuit 2 and the write circuit 111, and the boost circuit 2 boosts the +5V power supply voltage to a high voltage of 20V in response to the write mode signal or erase mode signal, and performs writing. The signal is applied to the memory cell 100 via the input circuit 111. When a high voltage is applied to a cell at a designated address in the memory cell 100, information in that cell is written. Sense circuit 108 amplifies information read from memory cell 100 and provides it to output circuit 109.

FIG. 6 is a specific block diagram of the area around the memory cell shown in FIG. 5, FIG. 7 is a specific electrical circuit diagram of the booster circuit shown in FIG. 6, and FIG. FIG. 2 is a specific electrical circuit diagram of a voltage switch.

Next, the periphery of the memory cell will be described in more detail with reference to FIGS. 6 to 8. In order to rewrite 8-bit data at once, the memory matrix MA in FIG. 6 has memory cells Mll...Mln, M21...-M2n,
An example is shown in which M31=.M3n and M41.=M4n are arranged in a matrix of 2 rows and 2 columns. Memory cell M11 includes a selection transistor and a storage transistor, and other memory cells are similarly configured. Each memory cell M11=・Ml n, M21=−M2n, M31−・
-M3 n.

The selection transistors M41...M4n are connected to the word line W1
, W2 in the row direction, and the digit line Dll
...in, D21...D2n in the column direction. A high voltage switch 71. is connected to the word lines Wl and W2.
72 are connected, high voltage switches 52...5n are connected to the digit lines D11...Din, and high voltage switches 62...6 are connected to the digit lines D21...D2n.
n is connected. The transistors 81 and 82 transfer the high voltage of the control gate line CG1 to the memory cells Mll...M.
in, M21...M2n control gates, and transistors 83 and 84 are connected to control gates [C
The high voltage of G2 is transferred to memory cells M31...M3n, M41.
...Transmit to the control gate of M4n. The drains of transistors 81 and 82 are connected to high voltage switch 51, and the drains of transistors 83 and 84 are connected to high voltage switch 61.

The control circuit 1 applies a control number 1J to the booster circuit 2 to cause the booster circuit 2 to generate a high voltage during the write mode and the erase mode. The booster circuit 2 includes an oscillator 21, as shown in FIG. The oscillator 21 starts oscillating operation in response to a control signal from the control circuit 1. The booster circuit 2 includes n-channel transistors 23 whose gates and drains are connected and which are connected in series, a source of each transistor 23, an output of an oscillator 21, and an output of an inverter 22 that inverts the output of the oscillator 21. It includes a capacitor 24 connected therebetween. This booster circuit 2 is called a charge pump, and uses a combination of an N-channel transistor 23 and a capacitor 24 to boost the output of the oscillator 21 and transfer the high voltage to the high voltage switches 51, 52, .
n, 61.62...6n, 71 and 72.

Control circuit 1 applies a control signal to one input terminal of each of AND gates 31 and 41 in write mode and erase mode. The other input terminal of AND gate 31 is supplied with address signal Y1, and the other input terminal of AND gate 41 is supplied with address signal Y2. AND gate 32...
・Data D1...D is input to one input terminal of each of 3n.
8 is applied, and an address signal Y1 is applied to the other input terminal.

Data D1...D8 are applied to one input terminal of each of the AND gates 42...4n, and an address signal Y2 is applied to the other input terminal. High voltage switch 71.7
2 are given address signals XI and X2.

Next, the configuration of the high voltage switch 50 will be explained with reference to FIG. The inverter 501 includes an AND gate 31.32''-3n shown in FIG.

41, 42...4n, and the output of either Xi or X2 is given. The output of inverter 501 is applied to the gate of N-channel transistor 502, the source of N-channel transistor 502 is grounded, and the drain is connected to the drain of N-channel transistor 503 and the gate of N-channel transistor 504. The gate and source of the N-channel transistor 503 are connected to the capacitor 50.
5 and the source of an N-channel transistor 504. A high voltage is applied to the drain of the N-channel transistor 504 from the booster circuit 2, and a high voltage is applied to the drain of the N-channel transistor 504.
The oscillation output of the oscillator 21 is applied to the other end of the oscillator 5. A high voltage is then output from the drain of N-channel transistor 502.

Next, the operation of the conventional EEFROM will be explained. The high voltage switch 50 is a switching element for switching a high voltage (approximately 20V) for writing to the EEPROM using a surrounding 5V signal, and connects the gate of the N-channel transistor 502 with a high level (5V). When a signal is input, this N-channel transistor 502 is turned on, and an "L# level signal is output from its drain.

When a signal of "L level (Ov)" is input to the gate of the N-channel transistor 502, this N-channel transistor 21 is turned off, and the capacitor 505 and N-channel transistors 503 and 504 function as the final stage of the booster circuit, and the high Output voltage.

- As an example, the operation of erasing and writing data in the memory cells M11 in the first row and first column of the 2 rows and 2 columns memory cell array MA shown in FIG. 6 will be described. EEFRO
M has two modes, an erase mode and a write mode, but the erase mode will be explained first. Data is erased by applying a high voltage of about 20V to the gate (generally called a control gate) of the storage transistor of the memory cell M11. First, a control signal to start oscillation is sent from the control circuit 1 to the oscillator 21 of the booster circuit 2. The oscillator 21 starts oscillating in response to the control signal, and the booster circuit 2 generates a high voltage.

At this time, the control signal E output from the control circuit 1 is “H”.
" level, and data D1 to D8 are set to "L" level. Now, the memory cell Dll in the first row and first column
Since the address signal X1 is about to be erased, the address signal
” level, X2 is “L” level, Yl is aH level,
Y2 is set to "Lm level. Therefore, AN
D gate 31 is opened, high voltage switch 51 sets control gate signal CGI to 20V, and high voltage switch 71 sets word signal W1 to 20V.

As a result, transistor 81 becomes conductive, and memory cell Ml
A high voltage is applied to the control gate of 1 to erase data.

Data writing is performed by applying a high voltage of 20V to the drain of the storage transistor of the memory cell. That is, in the write mode, the control signal E is “L”.
"level, and each data D1 to D8 is set to each position.

Address signals Xi, X2. Yl and Y2 are the same as in the erase mode. Control gate signal CGI is “L”
In contrast, when the data D1 to D8 are at the L level, writing to the memory cell is not performed because no high voltage is transmitted to the digit signal Dll. For example, when data D8 is set to “H” level,
Since a high voltage is transmitted to the digit signal Dll, writing to the memory cell Mll is performed.

[Problems to be Solved by the Invention] When the EEFROM shown in FIG. 6 above is used as a storage element, the data held by the EERPOM is destroyed when the power is turned on or off or when the applied voltage is momentarily interrupted. There is a possibility that That is, although power is supplied to the booster circuit 2 via an external terminal, when a high voltage is applied to the memory cell, 1sR is turned on.

If the signal output from the controller becomes unstable due to an off state or a momentary power failure, there is a possibility that the IC side will mistakenly enter the write mode. Furthermore, if the booster circuit 2 shown in Figure 7 is provided inside the IC, if the signal output from the controller becomes unstable due to power on/off or instantaneous power failure, the write mode may be accepted. There is sex.

By the way, data can be electrically rewritten in EEFROM, but in many cases, even if data is written in one area, the data once written in other areas is not rewritten, so-called. In most cases, it is used like a ROM. Therefore, from the user's point of view, various measures are taken to protect the written data from being disturbed due to the causes mentioned above, which could be fatal to the system.

For example, possible countermeasures include attaching a pull-up or pull-down resistor to the input terminal, attaching a power supply detection circuit inside or outside the IC, and turning off the main power supply after determining the signal line from the outside. However, these measures were not sufficient to completely protect against erroneous writing.

Therefore, the main object of the present invention is to provide a non-volatile semiconductor memory device having an area in an EEFROM memory element array where data cannot be rewritten.

[Means for Solving the Problem] The invention according to the first claim is a non-volatile semiconductor memory device that uses an electrically rewritable non-volatile semiconductor as a memory element, in which only a part of the storage area of the memory element is used. includes means for selectively rewriting the .

The invention according to claim 2 is a nonvolatile semiconductor memory device that uses an electrically rewritable nonvolatile semiconductor as a memory element, and includes a plurality of means for supplying a rewrite voltage to the memory element.

[Operation] In the nonvolatile semiconductor memory device according to the first claim, when the write mode is set, only a part of the storage area of the storage element can be rewritten, and data in other areas is prohibited from being rewritten. be done.

In the invention according to the second claim, since the area of the memory element is divided into several parts and means for supplying a rewriting voltage corresponding to each area is provided, it is not possible to rewrite only a specific area of the memory element. be done.

[Embodiment] FIG. 1 is a schematic block diagram showing the overall configuration of an embodiment of the present invention. Referring to FIG. 1, the memory matrix, Trix, is divided into an area M10 that can be rewritten only once and an area M20 that can be rewritten many times. Each area MIO, M
Corresponding to 20, write circuits 9 and 10 are provided for writing data into the respective memory cells. Furthermore, control circuit 110 allows data to be written to region MIO only when a control signal of, for example, "H" level is applied from external terminal 107.

FIG. 2 is a concrete block diagram of the periphery of the memory cell shown in FIG. 1. This FIG. 2 is constructed in the same manner as the above-mentioned FIG. 6 except for the following points.

That is, the one-time rewritable area MIO is the memory cell M
ll...Min and M21...M2n, and the rewritable area M20 includes memory cells M31...M3n and M4.
1...M4n. Word signal W1 of area MIO
0 is connected to the high voltage switch 71 and the word signal W20
is connected to high voltage switch 72. Word signal W11 of region M20 is connected to high voltage switch 73, and word signal W21 is connected to high voltage switch 74. The high voltage switches 73 and 74 are supplied with a high voltage from the booster circuit 2 and are also supplied with address signals Xi and X2.

The AND gate 31 receives a control signal E1 from the control circuit 110.
is applied, and the control signal E2 is applied from the control circuit 1 to the other input terminal of the AND gate 41.

The control circuit 110 sets the control signal E1 to the 11 L j level when data can be rewritten only once in the area MIO in response to a signal of, for example, "H° level" applied from the external terminal 107 shown in FIG. , otherwise ′
The control circuit 110 also sets the control signal E2 to the "H" level in the rewrite mode and the erase mode.

In response to the control signal E1 being set to the "L" level, the high voltage switch 51 outputs the control gate signal CG.
1 is set to "L" level. Address signals XI and Yl are set to the 'Hm level, and data D1 to D8 are set in their respective locations.

For example, when data D8 is set to “H rubel”,
High voltage switch 52 applies a high voltage to digit signal D11. At this time, the high voltage switch 71 also
Since high voltage is applied to the control gate of ll,
Writing is performed by applying a high voltage to the drain of the storage transistor of memory cell Mll. After writing, if the external terminal 107 is forced to the "L level", it is possible to eliminate the possibility that the data in the area M10 will be rewritten.

Writing of data to area M20 is performed by control circuit 110 setting control signal E2 to "L" level. At this time, the control signal E1 is set to the "H° level. In other words, the control circuit 110 sets the control signal E1 to the "L" level in order to rewrite the area MIO only once, and inputs data into the area M20. When rewriting the area M10 times, if the control signal E1 is forced to the H" level, the area M10
It is possible to eliminate the risk of data being rewritten.

Note that the operation of erasing regions MID and M2O is the same as that described in FIG. 6 above.

FIG. 3 is a block diagram showing the overall configuration of another embodiment of the invention. The embodiment shown in FIG.
A booster circuit 2 and a write circuit 9 are provided corresponding to the region M2.
A booster circuit 3 and a write circuit 10 are provided corresponding to M10, and the booster circuit 2 and the rewrite circuit 9 are operated when the area M10 is rewritten only once.

FIG. 4 is a concrete block diagram of the periphery of the memory cell shown in FIG. 3. Referring to FIG. 4, this embodiment is the same as FIG. 2 except as follows.

That is, booster circuit 3 is provided corresponding to region MIO, and booster circuit 2 is provided corresponding to region M20. When rewriting data in area MIO only once, a control signal is applied from control circuit 110 to booster circuit 3.

In response to the control signal, the booster circuit 3 boosts the power supply voltage +V applied to the terminal 3a to generate a high voltage, which is applied to the high voltage switches 51, 52, . . . , 5n, 71, and 72.

At this time, control circuit 1 sets control signal E to "L" level. As a result, the control gate signal CGI is “
Then, the address signals Xi and Yl become H
” level and data D8 is set to “H level,” the high voltage switch 52 applies a high voltage to the drain of the control gate transistor of the memory cell Mll, and the high voltage switch 71 applies a high voltage to the gate of the control gate transistor. give heavy pressure.

As a result, a high voltage is applied to the drain of the storage transistor and data is rewritten. After rewriting the data in the area MIO, if the terminal 3a is grounded instead of the power supply voltage +V applied to the booster circuit 3, the controller (not shown) will be affected by power on/off or instantaneous power outage. Even if the output signal from the area MIO becomes unstable and the write mode is mistakenly entered, writing to the area MIO will not be performed, and the risk of data stored in the area MIO being destroyed can be eliminated.

Note that the operations for writing and erasing data in the area M20 are the same as in the embodiment shown in FIG. 2 described above.

Note that in the above embodiment, the memory cell array is EE.
Although FROM is used, the same effect can be obtained by using a mask ROM in the area of the ROM where previously written data is not rewritten. At that time, data must be written in the mask ROM before mounting.

〔Effect of the invention〕

As described above, according to the first aspect of the invention, by providing a circuit that can selectively rewrite only a part of an electrically rewritable memory element,
Even if the storage element is mistakenly set to write mode, the rewritable area is limited, so data destruction in non-rewritable areas can be prevented.

According to the invention according to the second claim, by providing a plurality of means for supplying a rewriting voltage to the memory element and disabling the power supply means corresponding to a part of the storage area where data has been rewritten after the data has been rewritten. , it is possible to prevent data from being destroyed due to unstable power supply.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a concrete block diagram of the periphery of the memory cell shown in FIG. 1. FIG. 3 is a schematic block diagram showing the overall configuration of another embodiment of the invention. FIG. 4 is a concrete block diagram of the periphery of the memory cell shown in FIG. 3. FIG. 5 is a schematic block diagram of a conventional EEFROM. FIG. 6 is a detailed block diagram of the periphery of the memory cell shown in FIG. 5. FIG. 7 is a specific electrical circuit diagram of the booster circuit shown in FIG. 6. FIG. 8 is also a specific electrical circuit diagram of the high voltage switch. In the figure, 1 is a control circuit, 2.3 is a booster circuit, 9.1
0 is the write circuit, 31.32...3n, 41°42-4
n is an AND gate, 51.52-5n. 61.62...6n, 71.72 are high voltage switches,
'81 to 84 are N-channel transistors, M
lo is a rewritable area only once, M2O is a rewritable area,
Ml 1-Mln, M21-...M2n, M31-...M
3n, M41...M4n indicate memory cells.

Claims (2)

[Claims] (1) A nonvolatile semiconductor memory device using an electrically rewritable nonvolatile semiconductor as a memory element, characterized by comprising means for selectively rewriting only a part of the memory area of the memory element. Non-volatile semiconductor memory device. (2) A nonvolatile semiconductor memory device using an electrically rewritable nonvolatile semiconductor as a memory element, characterized in that the nonvolatile semiconductor memory device includes a plurality of means for supplying a rewrite voltage to the memory element. .