JPH02270051A - Storing system for data parity bit of memory - Google Patents

Abstract

PURPOSE:To reduce a packing space by using a parity bit selection circuit to store (n) pieces of parity bits into a parity bit storing memory as a single word. CONSTITUTION:The data on a single word including the parity bit of the data corresponding to an address shown by a memory address bus signal 9 is read out of an (m-word X n-bit)-structure parity memory 11 and latched by a data latch circuit 17. Then a data parity bit 4 is connected to the data bit of the corresponding parity memory data bus 5 via a parity bit selection switch 16 and based on the parity bit selection signal produced by an address decoder 18. Then only the data bit of the bus 5 is replaced with the bit 4 out of the parity data latched previously and written again into the memory 11. As a result, the number of parity bit storing memory elements can be decreased together with reduction of the packing space.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for storing data parity bits in a memory, and in particular to a method for storing data parity bits in a memory when detecting data errors on a data bus of a CPU such as a microcomputer. Regarding the storage method.

[Conventional technology]

Conventionally, this type of data parity bit storage method is
As shown in the figure and FIG. 5, a data storage memory 2 consisting of n×k data memories 13 having an m word×n bit configuration and storing data in which n bits constitute one word;
m words x n for storing 1-bit parity bits n x m x k corresponding to 1 word of data
Parity memories 11 having a bit configuration are n×k, or n
It consisted of a parity bit storage memory 1 having two parity memories 20 each having an m word x 1 bit configuration.

[Problem to be solved by the invention]

In the conventional memory data parity bit storage method described above, when a data storage memory with an m word x n bit configuration is used as a parity bit storage memory, the number of memory elements is n x the same as the number of elements of the data storage memory. Since k pieces are required, there is a problem that the mounting space increases.

Also, among the data bits in the parity bit storage memory (
There is a problem that n-1)/n pieces are unused and are wasted.

Furthermore, if a data storage memory with nm word x 1 bit configuration is used as the parity bit storage memory,
There is a problem in that a memory element of a different type from the data storage memory must be prepared.

It is an object of the present invention to reduce the number of data words of a parity bit storage memory, to use the same element as the data storage memory as a memory element, and to use the memory element used for the parity bit storage memory. It is an object of the present invention to provide a method for storing data parity bits in a memory, which can reduce the number of bits and the mounting space.

[Means to solve the problem]

The data parity bit storage method of the memory of the present invention is as follows: (A) m(
(m is a positive integer) word x n (n is a positive integer) data storage memory having n x k (k is a positive integer) bit-configured data memory, (B) 1 bit corresponding to 1 word of data (C) an address bus control circuit that converts a memory address bus into a parity memory address bus; a control signal generation circuit that converts a memory control signal into a parity memory control signal and a control signal for a data latch circuit; a parity bit selection switch that selectively connects a data parity bit to a corresponding parity bit of a parity memory data bus;
an address decoder that generates a signal for selecting a parity bit corresponding to an address of the parity memory data bus from the memory address bus; and a parity bit selection circuit having a data latch circuit that latches the data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The data parity bit storage method of the memory shown in FIG. 1) Data storage memory 2.1
1-bit parity bit n corresponding to word data
The parity bit storage memory 1 has k (k=1) parity memories each having an m word x n bit structure and stores Xmxk (k=1) parity memories, and a parity bit selection circuit 3 that selects parity bits.

In FIG. 1, a data storage memory 2 stores or reads n bits/1 word of data at an address designated by a memory address bus signal 9 in accordance with a memory control signal 8 via a memory data bus 10.

Parity bit storage memory 1 stores or reads parity bits corresponding to the content of n bits/1 word of data in data memory 2 in accordance with memory control signal 8 .

FIG. 2 is a diagram showing the bit configurations of the parity bit storage memory 1 and the data storage memory 2 when the number of memory elements in the embodiment shown in FIG. 1 is equal to 1.

In FIG. 2, m represents the number of words in the memory, and n represents the number of bits in one word. Further, [Dm,n] indicates the n-th bit 14 data of the data (word) at memory address m. PDnrn is memory address r
m x n indicates the parity bit 12 of the data at address J, and the data at memory address rm x nJ is [D
nm.

1] to [Dnm,n].

The parity bits are stored corresponding to addresses in the parity bit storage memory 1, with n bits as one word.

FIG. 3 shows the parity bit selection circuit 3 of the embodiment shown in FIG.
FIG.

The parity bit selection circuit 3 shown in FIG. 3 includes an address bus control circuit 15 that converts the memory address bus signal 9 into a parity memory address bus signal 6,
a control signal generation circuit 19 that converts the data into a parity memory control signal 7 and a control signal for the data latch circuit, a parity bit selection switch 16 that selectively connects the data parity bit to the corresponding parity bit of the parity memory data bus 5, and a memory address. An address decoder 18 generates a signal for selecting a parity bit corresponding to the address of the parity memory data bus 5 from the bus signal 9; It consists of a data latch circuit 17 that latches data.

First, a case will be described in which data parity bit 4 is written into parity memory 11 having an m word x n bit configuration.

First, one word of data including the parity bit of the data corresponding to the address indicated by the memory address bus signal 9 is
Read data is read from the parity memory 11 having an m word×n bit configuration and latched into the data latch circuit 17. The data latch timing signal and parity memory control signal 7 at this time are generated from the memory control signal 8 by the control signal generation circuit 19.

Further, the parity memory address bus signal 6 is generated from the memory address bus signal 9 by the address bus control circuit 15.

Next, according to the parity bit selection signal generated by the address decoder 18, the parity bit selection switch 16 is used to connect the data parity bit 4 to the corresponding data bit of the parity memory data bus 5.

Furthermore, among the parity data latched earlier,
Only the data bits of the corresponding parity memory data bus 5 are replaced with data parity bits 4, and the data is written again into the parity memory 11 having an m word x n bit configuration.

Next, a case will be described in which the data parity bit 4 is read from the parity memory 11 having an m word×n bit configuration.

First, one word of data including the parity bit of the data corresponding to the address indicated by the memory address bus signal 9 is
Read data is read from the parity memory 11 having an m word×n bit configuration and latched into the data latch circuit 17.

Further, according to the parity bit selection signal generated by the address decoder 18, the parity bit selection switch 16 is used to connect the corresponding data bit of the parity memory data bus 5 to the data parity bit 4 and output it.

At this time, the parity memory address bus 6 and the parity memory control signal 7 are generated by the address bus control circuit 15 and the control signal generation circuit 19, as in the case of writing to the parity memory 11 having an m word x n bit configuration.

〔Effect of the invention〕

As explained above, the present invention reduces the number of data words in the parity bit storage memory to 1/n by storing n parity bits as one word in the parity bit storage memory using the parity bit selection circuit. This has the effect that the same element as the data storage memory can be used as the memory element, and the number of memory elements used for the parity bit storage memory can be reduced to 17n, saving mounting space. This has the effect of making it smaller.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of the parity bit selection circuit of the embodiment of FIG. 1, and FIG. 4 shows the data parity of the conventional memory. Block diagram of bit storage method,
FIG. 5 is a diagram showing the bit configurations of a conventional parity bit storage memory and a data storage memory. DESCRIPTION OF SYMBOLS 1... Parity bit storage memory, 2... Data storage memory, 3... Parity bit selection circuit, 4...
data parity bit, 5... parity memory data bus, 6... parity memory address bus signal, 7.
...Parity memory control signal, 8...Memory control signal, 9...Memory address bus signal, 10...Memory data bus, 11...M word x n bit configuration parity memory, 12... Bit of data at memory address ``rm x n'', 13... Data memory with m word x n bit configuration, 14... nth bit of data (word) at memory address ``m'', 15... Address bus control circuit, 16... Parity bit selection switch, 17... Data latch circuit, 1.8... Address decoder, one... Control signal generation circuit, 20... n
Parity memory consisting of m words x 1 bit. Agent Patent Attorney Susumu Uchihara＼

Claims (1)

[Claims] (A) m(
(B) 1 bit corresponding to 1 word of data; (C) an address bus for converting a memory address bus into a parity memory address bus; a control circuit, a control signal generation circuit that converts the memory control signal into a parity memory control signal and a control signal for the data latch circuit, and selectively connects the data parity bit to the corresponding parity bit of the parity memory data bus. a parity bit selection switch;
an address decoder that generates a signal for selecting a parity bit corresponding to an address of the parity memory data bus from the memory address bus; and when selecting a corresponding parity bit from the parity memory data bus; A data parity bit storage method for a memory, comprising: a parity bit selection circuit having a data latch circuit that temporarily latches data.