JPH02265329A - Code inverse converter - Google Patents

Abstract

PURPOSE:To decrease the capacity of a lookup table by splitting an inputted code word into r-set of blocks in the unit of n-bit, decoding tentatively the code cord corresponding to each block into a bit number less than the n-bit of a basic code word length and decoding the result finally into a data word. CONSTITUTION:A bit string 10 of an input code word is inputted sequentially to a shift register 11, fed to a latch circuit 12, in which the signal is converted from a serial signal into a parallel signal. Moreover, a head 6-bit signal in 30 bits is sent to a bank selection circuit 13 and the remaining 25-bit is sent to a tentative coding circuit 14. The tentative decoding circuit 14 consists of 5 identical circuits and each circuit tentatively decodes a basic code word for each block in 5-bit. In total 15-bit except a 3-bit corresponding to the head block from the tentative decoded word is sent as an address signal of ROMs 21-25 being final decoding means. Thus, the capacity of the ROM for decoding is considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a code inversion device that decodes a data string consisting of a digital bit string when transmitting or recording a digital signal.

[Prior Art] Recording codes used when recording digital signals on optical disks, magnetic disks, etc.
Various methods have been developed as peripheral technologies such as LL progress. Such encoding converts binary data to be recorded into a binary code word pattern suitable for the characteristics of the recording/reproducing system including the recording medium. In particular, the following three points can be mentioned as properties required for this code.

(1) Minimum magnetization reversal interval T m l nThis T m l
It is desirable that n be as large as possible in order to make it less susceptible to the effects of band limitations in the recording/reproducing system.

(2) Maximum magnetization reversal interval T, □ This T, 1. is preferably a small value so that clock information can be extracted from reproduced data in order to obtain a self-clock function.

(3) Detection window width T.

It represents the margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and a large value is desirable.

Usually, a run-length limited (hereinafter abbreviated as RLL) code is often used as a recording code.
For the code, the minimum value of the number of runs of "O" between "1" and "1" in the code bit string after conversion is d, the maximum value is k, the basic data word length is n, the basic code word length is m, Let the codeword length be r−·wings (d, k.

n, m, rsa engineering) code. Using these parameters, T□l HT 1n + T'II is expressed as follows.

T mln = (d ” 1) T VT,,, =
(k+l)T.

T, = (m/n)T Here, T indicates the 1-bit length of the data word.

Among these RLL codes, variable length codes are suitable for high density, as they can achieve the same level of performance with a smaller code word length and number of code words than fixed length codes.

In order to use a recording code, a decoding device is required to convert the code word back into a data word, but this can be achieved by constructing a combination of gate circuits, or by using an input code word bit string as an address signal. There is a method of accessing a ROM in which a data word bit string is written. (d, ni, m
, n.

r□8) In the case of a code, if a ROM is used, its capacity v1 is y, = 2 rssx'. 'rmax'm pitted. In addition, in variable length codes, information on how many bits of the code word have been inversely converted is required in order to achieve word synchronization, and this is also normally written in the ROM, but this memory amount will not be considered when considering it. do.

FIGS. 2(A) to 2(D) are diagrams showing the case of (4, 19, 2, 5° 6) code. Here, the basic data word length is 2.
bit, basic codeword length is 5 bits, “
The minimum value of the number of runs of 0" is 4, and the maximum value is 19.

A conventional decoding circuit is configured as shown in FIG. 12, for example. Here, the input bit string is m'raax
(5X6=30), it is input into a 30-bit shift register, latched into a latch circuit also consisting of 30 bits, and decoded into a maximum of n''rma* (2X6=12) bits by the ROM table 141 in 30-bit units. Therefore, the required capacity V of the ROM table 141 is 2=230.12 to 1.3×10'' (bits).

[Problem to be solved by the invention] Generally, when the codeword length n is increased, T1°.

Either T 1jllX + TV can be improved. As mentioned above, when seeking a code with better performance in order to increase the density of variable-length codes, both the code word length and the number of code words become large. Therefore, decoding using ROM is necessary. When the circuit is constructed, the problem arises that its capacity becomes extremely large, making it impractical.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a code inversion device that reduces the capacity of a lookup table used for (d, ni, m, n, rahax) decoding. shall be.

[Means for Solving the Problems] In order to achieve the above object, the code inversion device of the present invention has the following configuration. That is, when the basic data word length is m bits and the basic code word length is n bits, for a predetermined number r, a data word with twice the bits of the basic data word is converted to twice the basic code word length. A code inverse conversion device that inversely converts a code word, the input code word being r
dividing means for dividing the blocks into blocks; temporary decoding means for temporarily decoding a code word corresponding to each of the blocks into a number of bits smaller than the n bits; Toni,
and decoding means for inputting the temporarily decoded bit pattern and finally decoding it into a data word.

[Operation] In the above configuration, the input code word is divided into r blocks in units of n bits, and the code word corresponding to each of the divided blocks is divided into bits smaller than the basic code word length of n bits. Temporarily decode into numbers. Then, input the temporarily decoded bit pattern based on the bit pattern of at least the first block among those blocks,
It operates to finally decode it into data words.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Before explaining this embodiment, the present invention will first be explained in detail.

In general, the basic number of code words of a variable-length code is much smaller than the number of binary codes represented by n bits, which is the basic code word length.In other words, with binary n bits, two codes can be expressed with one bit. , RLL code, the number of runs of "0" between "1" and "1" in a code word is limited in both the minimum value (d) and the maximum value (k). As a result, for example, in the (4, 19, 2.5.6) code shown in FIG. 2, the six code words shown in FIG. 3 become basic code words. This code has a code word length n=5 and can express 32 numerical values, so it has redundancy accordingly.

Here, if the number of basic codeword patterns is p, then p is q
Any one of the basic code word patterns can be uniquely specified using a binary number of (= [lagzpl + 1) bits ([ ] is a Gaussian symbol). In other words, instead of using the input code word directly as an address signal, q
Temporarily decoded into a bit code, and the total of the temporary decoded results r1
If 1, q bits are used as an address signal, the ROM capacity v2 required for decoding is V 2 = 2 """ - rmaw "m (bits).Furthermore, the bits in the first eight blocks Depending on the pattern, select 22 ROMs into which the temporary decoding output ((r, □-8)・q) (bit) from the remaining (f”sax S) block is input as an address, and the required ROM capacity will be reduced. ■ko is■! = (r
mat S ) r ”-hot”-”
” ” r , ax m (bits), and compared to the case where the input code word is directly used as an address signal, R
The ratio of OM capacitance is Vs/V+= (r, □s) 2 (r * a x −
* l °q-1” 1 blade °n.

[Description of decoding circuit (Figs. 1 to 8)] The configuration for realizing this embodiment will be described below (4°19.2, 5.6).
A description will be given based on the drawings, taking a code as an example.

This code has a basic data word length m=2. Basic codeword length n=5
．． The codeword length number r maM = 6, and T m l n
=2.0. It is a variable length code with T, , , = 8°O, T, = 0.4.

FIG. 1 is a block diagram schematically showing a decoding circuit according to an embodiment.

The bit string 10 of the input code word is sequentially input to a 30-bit shift register 11, and sent to a latch circuit 12 also consisting of 30 bits, where the serial signal is converted into a parallel signal. Furthermore, the first 5 bits of the 30 bits are sent to the bank selection circuit 13, and the remaining 2 bits are sent to the bank selection circuit 13.
The 5 bits are sent to the temporary decoding circuit 14.

The temporary decoding circuit 14 is composed of five identical circuits,
Each circuit temporarily decodes the basic code word for each 5-bit block. Here, as mentioned above, since the number of patterns of the basic code word is 6, the number of bits of the temporary decode word is 3 bits from [1ogz61+1.3. FIG. 3 shows the relationship between this provisional decoded word and the basic coded word. here 6
A 3-bit code is assigned to each type of basic code word. Although it is arbitrary how to allocate the eight types of 3-bit codes, the method shown in FIG. 3 will be followed here.

The temporary decoding circuit 14 outputs a 3-bit code (temporary decoded word) for each block according to this correspondence. In other words, if each of the code words shown in FIGS. 2(A) to (D) is divided into 5 bits and replaced according to FIG.
Correspondence between temporary decoded words and data words can be obtained. A part of it is shown in Figure 4.

A total of 15 bits (3 bits x 5), excluding 3 bits corresponding to the first block from this provisional decoded word, are sent as address signals to ROMs 21 to 25, which are the final decoding means. In this way, the temporary decoded word (address) is decoded into a data word (data stored in the ROM) as shown in FIG.

Since there are six types of 5-bit basic codewords as shown in Figure 3, each ROM requires six banks correspondingly, but which bank to select from among these is determined by bank selection. Determined by circuit 13. In addition, (4,
In the case of the 19,2,5,6) code, as can be seen from FIG. 2, there is no code word in which all five bits of the first block are "0", so there are five ROM banks.

As a result, the bank selection circuit 13 selects the first 5 bits. When 10000, bank 1 When 01000, bank 2 When 00100 (7), bank 3 When 00010, bank 4 When 00001, bank 5 shall be selected.

Next, the contents of the ROM used for final decoding will be explained based on FIG. 2.

As is clear from Fig. 2, when r > r+,
The codeword of 5r, bits may be equal to the 5r, bits from the beginning of the codeword of 5rz bits. (all codewords are included in bank 1)
. In this way, when the first 5 bits in the input shift register 11 are "10000" (the corresponding provisional decoded word is "001" from FIG. 3), it cannot be immediately decoded as the data word "00". However, it is necessary to give priority to codewords with longer word lengths. In order to realize this by arranging the data in the ROM, the data may be arranged in bank 1 as shown in FIG. In the figure, X in the data bits is an arbitrary bit.

Similarly, in FIG. 7, the first 5 bits are "ooo".

8 is a diagram showing the correspondence between code words starting with 1" and the corresponding temporary decoded words and data words. FIG. 8 is a diagram showing the data arrangement in the ROM 25 in bank 5 corresponding to FIG. 7. be.

Each of the ROMs 21 to 25 corresponds to the bank described above, with the ROM 21 corresponding to the bank 1, the ROM 22 corresponding to the bank 2, and so on. The 12-bit signals converted into data words by these ROMs (not all bits are necessarily fixed data words) are sent to a 12-bit output shift register 17. At the same time, ROM21~
25, information indicating how many bits of the code word have been decoded is sent to the latch signal generation circuit 15. As a result, for example, when a 10-bit code word (two data words) is converted, a new one is added to the input shift register 11.
When a 0-bit code word is input, the latch circuit 12
The next latch signal is output. Further, the code word sent to the output shift register 17 is serially converted and output bit by bit. However, although not shown in FIG. 1, the output shift register 17 is configured so that while the input shift register 11 shifts IO bits, the output shift register 17 shifts 4 bits.

[Explanation of decoding example (Figures 1 to 9)] Figure 9 shows the data word "1001001100011110101100"
This shows an example of decoding a code word encoded with " into the original data word.

In the figure, 90 indicates the original data word, and 91 indicates its code word string. Further, 92 indicates a temporary decoded word decoded by the temporary decoding circuit 14.

This code word string is input to a 30-bit shift register 11 as an input bit string 10. In this way, when 30 bits from the left of the code word string 91 are input to the shift register 11, a latch signal is output from the latch signal generation circuit 15 to the latch circuit 12, and the 30 bits of the shift register 11 are latched into the latch circuit 12. be done. Here, the first five bits (97) of the code word are input to the bank selection circuit 13, and bank 1 is selected. In addition, the temporary decoding circuit 14
temporarily decodes the subsequent 25 bits. The decryption result is 9
As shown in 3, "000000101101000" is yelling.

This “0000001011 old 000” is stored in ROM21 (
As shown in FIG. 6(b), the data word “100100x
xxx". Here, since X is an arbitrary code, the data word for the first 6 bits is determined.

Here, since the determined 6-bit data word corresponds to three words (15 bits) of the basic code word of the code word, a new 15-bit code word is shifted into the shift register 11. As a result, the next 5 bits input to the bank selection circuit 13 become the code word (00001) indicated by 98, and bank 5 is selected. In addition, the temporary decoding circuit 14
“0000100000100000000000
25 bits of “000” are input. Temporary decoding circuit 14
Now, temporarily decode this input data and get “10100θ00
1000000” 15 bits are stored in ROM25 (bank 5
) is output as the address. Since this address corresponds to the address shown at (8) in FIG. 8, the data word decoded is "l100OIXXXXXX" (94 in FIG. 9).

In this way, when another 6-bit data word is determined, a new 15-bit code word is shifted into the shift register 11, and code word 99 is set in the bank selection circuit 13 in the same manner as described above. In this way, bank 1 is selected again, and the temporary decoding circuit 14 has “0OOOOOOOOOOOO
OOOO100OOXXXXX” (X is undefined) is input, and the temporary decryption word “0OOOOOOOOOOIXXX” is input.
is converted to Since this provisional decoded word corresponds to (a) in FIG. 6, the data word “
1110101100” (95 in Figure 9)
, If we connect the definite parts of the decoded data words (the underlined parts of the data words mentioned above) as explained above, we get
It was decoded as "1001001100011110101100", and it was confirmed that this data word completely matched the original data word.

[Description of other embodiments (Fig. 5, Fig. 10, Fig. 11)] As is clear from Fig. 5, only four code words are sent from bank 1. to 32
A word ROM 21 is required. Therefore, if bank 1 is configured with the gate circuit 26 instead of the ROM 21, the number of ROMs corresponding to 32 words can be reduced by simply adding a circuit. This is shown in FIG. 10, which is a block diagram thereof, and FIG. 11 is a schematic circuit diagram of the gate circuit 26 constituting bank 1.

In the figure, each 3-bit block of the temporary decoding circuit 14 is shown as 14a to 14e. However, the temporary decoding word portion corresponding to block 14a is input to the bank selection circuit 13 and used for bank selection. . Now, considering the case where the temporary decoded word "001000" shown in FIG.
The output of 04 becomes high level. Since the beginning of the next temporary decoded word (a code in which any of the three bits is "1") is input to the block 14c, the output of the NOR circuit 103 becomes low level. As a result, the output of the AND circuit 105 becomes high level, and the output of the AND circuit 106 becomes low level. As a result, the output of the buffer 109 is “01”.
Here, since the input data is the temporary decoded word "001000", 4-bit data (0100) is adopted from the beginning of the output of the buffer 109.

Similarly, when the temporary decoded word is "001000000", the output of the buffer 109 is "1001001100".
6 bits from the beginning of this data (100100
) is adopted as a data word. Furthermore, the temporary decoded word “o”
When “aloooo ooo ooo oat” is input, the outputs of NOR circuits 102 to 104 all go to high level, the outputs of AND circuits 106 and 107 go to high level, and the outputs of AND circuits 105 and lO8 both go to low level. As a result, the output of the buffer 109 becomes “11”.
10101100'', and since the temporary decoded word consists of 15 bits, all the output bits of the buffer 109 (1
0 bit) is adopted as the data word.

In this way, the ROM21 part of bank 1 is connected to the gate circuit 2.
By substituting 6, the circuit cost can be kept low.

As explained above, according to this embodiment, the variable length RLL
In a code decoding device, by taking advantage of the fact that the basic number of n-bit code words is smaller than the number of code words represented by n bits, decoding is divided into preliminary decoding and final decoding, and furthermore, the bits in the first block are By selecting banks based on patterns, it was possible to significantly reduce the ROM capacity required for decoding in the circuit. As a result, even if recording density increases and the scale of recorded codes increases, a decoding circuit can be configured with a small ROM capacity, and its practical value is extremely high.

[Effect of the invention] As explained above, according to the present invention, (d.

k, m, n, r□8) This has the effect of reducing the capacity of the lookup table used for decoding.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a decoding circuit according to an embodiment, and FIGS. 2(A) to (D) are (4,19°2.5.
6) A diagram showing the correspondence between the data word and code word of the code, FIG. 3 is a diagram showing the correspondence between the basic code word and the temporary decoded word of the (4,19,2°5.6) code in this embodiment Fig. 4 is a diagram showing the correspondence between the data word and the temporary decoded word of the (4,19,2°5.6) code in this embodiment, and Fig. 5 is a code word whose first 5 bits are "10000". Figure 6 is a diagram showing the relationship between addresses and data in the ROM of bank 1 used for final decoding of the (4, 19, 2, 5, 6) code. Figure 7 shows a code word whose first 5 bits are "00001" and its corresponding temporary decoded word and data word. Figure 8 shows the relationship between the address and data of the ROM in bank 5 used for final decoding. 9 is a diagram showing the decoding process in the decoding circuit of the embodiment, FIG. 10 is a block diagram when R0M of bank 1 of the decoding circuit of the embodiment is configured with a gate circuit, and FIG. 11 is a diagram showing the decoding process in the decoding circuit of the embodiment. FIG. 12 is a block diagram showing the configuration of a substitute gate circuit for the ROM in bank 1, and FIG. 12 is a diagram showing the configuration of a conventional decoding circuit that uses an input code word bit string directly as a ROM address. In the figure, 10...input code word bit string, 11.17...
・Shift register, 12...Latch circuit, 13...
Bank selection circuit, 14...Temporary decoding circuit, 15...
Latch signal generation circuit, 21-25...R for final decoding
OM, 26... is a gate circuit. Patent applicant Canon Co., Ltd. Figure 4 Figure 12

Claims (3)

[Claims] (1) When the basic data word length is m bits and the basic code word length is n bits, for a given number r, the basic data word r
A code inversion device for inversely converting a code word obtained by converting a double-bit data word to twice the basic code word length, and a dividing means for dividing the input code word into r blocks in units of n bits. and provisional decoding means for provisionally decoding a code word corresponding to each of the blocks into a number of bits smaller than the n bits, and provisionally decoded bits based on the bit pattern of at least the first block among the blocks. A code inverse conversion device comprising: decoding means for inputting a pattern and finally decoding it into a data word. (2) The number of basic codewords of n bits, which is the basic codeword length, is p
Then, the temporary decoding means p
q bits corresponding to the seed pattern (q=[log_2p
2. The code inverse conversion device according to claim 1, wherein a temporary decoding code of ]+1 ([ ] is a Gaussian symbol) is output. (3) The decoding means outputs the maximum (r_m_a_x-1)×([log_2p]+
1) The code inverse conversion device according to claim 1, wherein a temporary encoded code of bits is converted into a data word of r_m_a_x·m bits.