JPH02263391A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate the layout of a semiconductor memory device by allowing a pre-word line connected to an output terminal of a line decoder and disposed extending over plural memory cell groups to intersect with a memory cell group selection line. CONSTITUTION:This memory device is provided with memory cell group selection lines 14a - 14c for selecting memory cell groups 1a - 1c, a pre-word line 15 placed in parallel in the same direction as word lines 3a - 3c being divided word lines, and AND gates 16a - 16c in which an input terminal is connected to the pre-word line 15 and the memory cell group selection lines 14a - 14c, and an output terminal is connected to the word lines 3a - 3c. A line decoder 4 is disposed in the end in the array direction of a chip formed by arraying plural memory cell groups 1a - 1c. Also, the pre-word line 15 connected to an output terminal of the line decoder 4, and disposed extending over plural memory cell groups 1a - 1c is allowed to intersect with the memory cell group selection lines 14a - 14c. In such a way, the layout of the semiconductor memory device is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional semiconductor memory device. In the figure, 1 is a memory cell arranged in a matrix, the detailed circuit of which is shown in FIG. 3, 2a and 2b are a pair of complementary bit lines, and 3 is a memory cell on the same row when selected 4 is a row decoder for decoding row address information; 5 is a row address signal line; 6a and 6b are bit line loads connected to the bit lines 2a and 2b, respectively; 7 is a power supply terminal; be.

In the memory cell 1 shown in FIG. 3, 8a and 8b are load elements constituted by MO3I transistors, resistors, etc., 9a and 9b are inverter transistors, and 10
a and 10b are access transistors; lla and llb are store nodes of memory cell 1;

Next, the operation of the semiconductor memory device having the above configuration will be described, for example, when store nodes lla and llb are written at "H" level and "L" level, respectively.

First, in the case of reading, when the address information of the cell to be read is input to the address signal line 5, the desired word vA3 is activated through the row decoder 4. and,
When this word line 3 is activated, the access transistor 10b storing the 1L'' level becomes conductive. Therefore, the bit line load 6b is connected from the power supply terminal 7 to the bit line 2.
A current flows through the path of access transistor 10b, access transistor 10b, and inverter transistor 9b, and reading can be performed.

In a semiconductor memory device with this configuration, all memory cells on the same device are activated, so current flows from the power supply to the memory cells in all columns, and when configuring a large-capacity static RAM with many columns, current consumption is reduced. growing. Therefore, in order to reduce current consumption, a semiconductor memory device shown in FIG. 4 has been proposed. In this case, the row decoder 4 is arranged in the center of the memory cell plane, the word line is divided into the left word line 3a and the right word line 3b, and only the word line of the selected memory cell group of the left and right memory cell groups is used. By activating it, a current path is generated in only half of all the columns. Note that 12a and 12b are AND gates that select the left word line 3a and the right word line 3b, respectively, and 13a and 13b.
are gate signal lines that open the AND gates 12a and 12b, respectively.

Next, FIG. 5 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 4.

In this case, row decoders 4a and 4b are arranged in multiple columns,
The word lines 3a to 3d are divided into multiples thereof to reduce the number of DC current paths.

[Problem to be solved by the invention]

However, conventional semiconductor memory devices require the provision of a large number of row decoders. This increases the chip area, resulting in disadvantages such as deterioration of speed performance and yield.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-speed, low-power, large-capacity semiconductor memory device.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a plurality of memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided into a plurality of blocks in the column direction, and each of the plurality of memory cell groups is arranged in a plurality of blocks. a memory cell group selection line for selecting a specific one of each memory cell group, a row decoder for decoding the row address information of the memory cell group to be accessed, and an output terminal of this row decoder. A front word line that is connected and arranged across a plurality of memory cell groups and intersects with a memory cell group selection line; In this embodiment, a divided word line is provided which is activated based on the output signal of the divided word line.

[Effect]

The semiconductor memory device according to the present invention has high speed and low power consumption.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention. As an example, it shows a case where memory cell groups 1a, lb and an IC divided into three in the column direction are arranged. In the figure, 14a, 1.4. b and 14c are memory cell group selection lines for selecting the memory cell groups 1a to 1c, and 15 is a divided word line for each word.
The input terminals of preword lines 16a, 16b and 16c arranged in parallel in the same direction as 3a to 3C are connected to the prefix word line 15 and memory cell group selection lines 14a to 14C, respectively, and the output terminals are connected to word line 3a, respectively. This is an AND gate connected to ~3C. The row decoder 4 is arranged at an end in the arrangement direction of a chip formed by arranging a plurality of memory cell groups.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, when selecting a memory cell in memory cell group a, for example, the row address information of memory cell group 1a to be accessed is decoded by row decoder 4, and one of the front word lines 15 is activated. Then, when a selection signal is applied to the memory cell group selection line 14a, the AND gate 16a opens and the word line 3a is activated. Therefore, the memory cell group 1a is connected from a power supply (not shown) to a bit line (not shown).
The column current flowing into the memory cell group la flows only through the columns within the selected memory cell group la.

Note that although the selection of memory cells in the memory cell group la has been described above, it goes without saying that the selection can be made in the same manner for other memory cell groups 1b and ICs. moreover,
Although the case where the memory cell group is divided into three cells has been described, it goes without saying that the same effect can be achieved even if the memory cell group is divided into N cells (N≧2). Further, if only the front word line 15 is made of a low-resistance material, the word line has a short length even if the resistance is somewhat high, so the capacitance is small and the memory cells can be accessed at high speed. In addition, and gates 16a to 16
Since c has two input terminals and one output terminal, the circuit configuration is simple and the increase in chip area can be ignored. Furthermore, AND gate 16 as a gate means
By providing a-16c at one end of each memory cell group, the layout of the semiconductor memory cell device becomes easy.

Furthermore, if the preword line 15 connected to the output terminal of the row decoder 4 and arranged across the plurality of memory cell groups 1a to IC is made to intersect with the memory cell group selection lines 14a to 14c, the semiconductor memory Equipment layout becomes easier.

〔Effect of the invention〕

As explained above, in the present invention, the number of columns with DC current paths can be reduced by performing memory cell selection in two stages: pre-word lines and divided word lines. This has the effect of making it possible to obtain a high-speed, low-power consumption, large-capacity semiconductor memory device.

Furthermore, the layout of the semiconductor memory device is facilitated by making the preword line connected to the output terminal of the row decoder and arranged across multiple memory cell groups intersect with the memory cell group selection line. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing a conventional semiconductor memory device, and FIG. 3 is a detailed circuit diagram of the memory cell shown in FIG. FIG. 4 is a block diagram showing another conventional semiconductor memory device, and FIG. 5 is a layout diagram showing another conventional semiconductor memory device. la-IC...Memory cell group, 3a-3C...Word line, 4... Row decoder, 14a-14c...Memory cell selection line, 15... Front word line, 16a-16
C...and gate.

Claims (1)

[Claims] A memory cell array in which memory cells are arranged in a matrix is divided into a plurality of blocks in the column direction. A memory cell group selection line for selecting a specific memory cell group, a row decoder for decoding row address information of the memory cell group to be accessed, and a memory cell group selection line connected to the output terminal of the row decoder and arranged across the plurality of memory cell groups , a prefix word line that intersects the memory cell group selection line, and a selection signal of the memory cell group select line provided corresponding to each of the plurality of memory cell groups and an output signal of the prefix word line. What is claimed is: 1. A semiconductor memory device comprising a divided word line that is activated based on the selected word line.