JPH02257551A - Image forming device - Google Patents

Image forming device

Info

Publication number
JPH02257551A
JPH02257551A JP7661189A JP7661189A JPH02257551A JP H02257551 A JPH02257551 A JP H02257551A JP 7661189 A JP7661189 A JP 7661189A JP 7661189 A JP7661189 A JP 7661189A JP H02257551 A JPH02257551 A JP H02257551A
Authority
JP
Japan
Prior art keywords
electron
grid electrode
electron beam
image forming
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7661189A
Other languages
Japanese (ja)
Inventor
Hidetoshi Suzuki
英俊 鱸
Haruto Ono
治人 小野
Tetsuya Kaneko
哲也 金子
Ichiro Nomura
一郎 野村
Yoshimi Uda
宇田 芳巳
Kiyoshi Takimoto
瀧本 清
Takeo Tsukamoto
健夫 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP7661189A priority Critical patent/JPH02257551A/en
Publication of JPH02257551A publication Critical patent/JPH02257551A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00Electrodes common to discharge tubes
    • H01J2201/30Cold cathodes
    • H01J2201/316Cold cathodes having an electric field parallel to the surface thereof, e.g. thin film cathodes
    • H01J2201/3165Surface conduction emission type cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2329/00Electron emission display panels, e.g. field emission display panels

Abstract

PURPOSE:To reduce unevenness of the brightness on an image by furnishing modulating grid electrodes for controlling passage and shutoff of an electron beam emitted from an electron emitting element, changing the area of an opening in each modulating grid electrode, and thereby making uniform the beam current. CONSTITUTION:Striped grid electrodes GR is furnished in the middle of a base plate S and a face plate FP. Each of these electrodes is provided with an open hole Gh to allow penetration by an electron beam. Therein open holes Gh in the grid electrodes have different opening areas in relationship as Gha<Ghb<Ghc. Usage of these grid electrodes GR shall be such that grid electrodes G1 and G200 at the two ends have the smallest opening, i.e., (a) the grid electrode G100 in the center has the greatest, (c), and ones between the ends and the center have middle opening area, (b).

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、多数の電子放出素子と前記多数の電子放出素
子から放出される電子ビーム群を変調する為のグリッド
電極と電子ビームの照射により画像を形成する為のター
ゲットとを備えた画像形成装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention utilizes a large number of electron-emitting devices, a grid electrode for modulating a group of electron beams emitted from the large number of electron-emitting devices, and irradiation of the electron beam. The present invention relates to an image forming apparatus including a target for forming an image.

〔従来の技術] 従来、簡単な構造で電子の放出が得られる素子として、
例えば、エム アイ エリンソン(M、I。
[Prior art] Conventionally, as an element that can emit electrons with a simple structure,
For example, M.I. Ellingson (M,I.

Elineon)等によって発表された冷陰極素子が知
られている。[ラジオ エンジニアリング エレクトロ
ン フィジッス(Radio Eng、 Electr
on。
A cold cathode device announced by Elineon et al. is known. [Radio Engineering Electron Physics (Radio Eng, Electr
on.

Phys、 )第10巻、1290〜1296頁、19
65年1この種の電子放出素子としては、前記エリンソ
ン等により開発されたSnug (Sb)薄膜を用いた
もの、Au薄膜によるもの[ジー・ディトマー“スイン
ソリド フィルムス″(G、 Dittmer:thi
nSolid Films”) 、 9巻、317頁、
  (1972年)1、ITO薄膜によるもの[エム 
ハートウェル アンド シー ジー フォンスタッド 
“アイ イーイー イー トランス”イー デイ−コ 
ン )(M、 Hartwell and C,G、F
onstad: ”IEEE Trans。
Phys, ) Volume 10, pp. 1290-1296, 19
1 In 1965, this type of electron-emitting device includes one using the Snug (Sb) thin film developed by Ellingson et al., and one using an Au thin film [G. Dittmer: thi
nSolid Films”), volume 9, page 317,
(1972) 1. ITO thin film [M
Hartwell and C.G. Fonstad
“I EEE E Trance” E Deco
) (M, Hartwell and C,G,F
onstad: “IEEE Trans.

εD Conf、”)519頁、  (1975年)]
、カーボン薄膜によるもの「荒木久他」”真空”、第2
6巻、第1号、22頁、(1983年)]などが報告さ
れている。
εD Conf,”) page 519, (1975)]
, by carbon thin film "Hisashi Araki et al.""Vacuum", No. 2
Vol. 6, No. 1, p. 22, (1983)].

また、上記以外にも、薄膜熱カソードやMIM型放出素
子等の有望な電子放出素子が数多く報告されている。
In addition to the above, many promising electron-emitting devices such as thin-film thermal cathodes and MIM-type emitting devices have been reported.

これらは、成膜技術やホトリソグラフィー技術の急速な
進歩とあいまって、基板上に多数の素子を形成すること
が可能となりつつあり、マルチ電子ビーム源として、蛍
光表示管、平板型CRT 、電子ビーム描画装置等の各
種画像形成装置への応用が期待されるところである。
Together with rapid advances in film-forming technology and photolithography technology, it is becoming possible to form a large number of elements on a substrate. Application to various image forming devices such as drawing devices is expected.

[発明が解決しようとする課題] しかしながら、これらの素子を画像形成装置に応用する
場合、一般には、基板上に多数の素子を配列形成し、各
素子間を薄膜もしくは厚膜の電極で電気的に配線しマル
チ電子ビーム源として用いていたが、配線抵抗で生じる
電圧降下の為に、各素子毎に印加される電圧がばらつい
てしまうという現象が生じる。その結果、各放出素子か
ら放出される電子ビームの電流量にばらつきが生じ、形
成される画像形成装置に輝度(濃度)むらが起きるとい
う問題が発生していた。
[Problems to be Solved by the Invention] However, when applying these elements to image forming devices, generally a large number of elements are arrayed on a substrate, and electrical connections are made between each element using thin or thick film electrodes. However, due to the voltage drop caused by the wiring resistance, a phenomenon occurs in which the voltage applied to each element varies. As a result, the amount of current of the electron beam emitted from each emitting element varies, causing a problem of uneven brightness (density) in the formed image forming device.

第9図及び第1O図はこの問題をより詳しく説明する為
の図で、両図とも (a)は電子放出素子と配線抵抗及
び電源を含む等価回路図であり、(b)は各電子放出素
子の正極と負極の電位を示す図、又(C)は各素子の正
負極間に印加される電圧を示す図である。
Figure 9 and Figure 1O are diagrams to explain this problem in more detail. In both figures, (a) is an equivalent circuit diagram including an electron-emitting element, wiring resistance, and power supply, and (b) is an equivalent circuit diagram of each electron-emitting element. A diagram showing the potentials of the positive and negative electrodes of the elements, and (C) a diagram showing the voltages applied between the positive and negative electrodes of each element.

第9図(a)は、並列接続されたN個の電子放出素子D
τ〜DH’と電源VEとを接続した回路を示すもので、
電源の正極と素子り、の正極を、また電源の負極と素子
DNの負極を接続したものである。また、各素子を並列
に結ぶ共通配線は、図に示すように隣接する素子間でr
の抵抗成分を有するものとする。(画像形成装置では、
電子ビームのターゲットとなる画素は、通常、等ピッチ
で配列されている。従って、電子放出素子も空間的に等
間隔をもって配列されており、これらを結ぶ配線は幅や
膜厚が製造上ばらつかない限り、素子間で等しい抵抗値
を有する。) また、全ての電子放出素子り、〜DNは、はぼ等しい抵
抗値Rdを各々有するものとする。
FIG. 9(a) shows N electron-emitting devices D connected in parallel.
This shows a circuit that connects τ~DH' and the power supply VE.
The positive electrode of the power source and the positive electrode of the element DN are connected, and the negative electrode of the power source and the negative electrode of the element DN are connected. In addition, the common wiring that connects each element in parallel is r
It shall have a resistance component of (In the image forming device,
Pixels that are targets of electron beams are usually arranged at equal pitches. Therefore, the electron-emitting devices are also spatially arranged at regular intervals, and the wiring connecting these devices has the same resistance value between the devices as long as there is no manufacturing variation in width or film thickness. ) Furthermore, it is assumed that all the electron-emitting elements R, ~DN have approximately the same resistance value Rd.

前記第9図 (a)の回路図に於て、各素子の正極及び
負極の電位を示したのが同図(b)である。図の横軸は
、D1〜DNの素子番号を示し、縦軸は電位を示す。・
印は各素子の正極電位を、厘印は負極電位を表わしてお
り、電位分布の傾向を見易くする為、便宜的に・印(■
印)を実線で結んでいる。
In the circuit diagram of FIG. 9(a), FIG. 9(b) shows the potentials of the positive and negative electrodes of each element. The horizontal axis of the figure shows the element numbers D1 to DN, and the vertical axis shows the potential.・
The mark represents the positive electrode potential of each element, and the square mark represents the negative electrode potential.For convenience, the mark (■
) are connected with solid lines.

本図から明らかなように、配線抵抗rによる電圧降下は
一様に起こるわけではな(、正極側の場合は素子り、に
近い程急峻であり、逆に負極側では素子DNに近い程急
峻になっている。これは、正極側では、D、に近い程配
線抵抗rを流れる電流が大きく、また、負極側では、逆
にDNに近い程大きな電流が流れる為である。
As is clear from this figure, the voltage drop due to the wiring resistance r does not occur uniformly (on the positive side, it is steeper the closer it is to the element DN, and conversely, on the negative side, the closer it is to the element DN, the steeper it is. This is because on the positive electrode side, the closer to D, the larger the current flows through the wiring resistance r, and on the negative electrode side, the closer to DN, the larger the current flows.

これから、各素子の正負極間に印加される電圧をプロッ
トしたのが同図 (c)である。図の横軸はり、〜DN
の素子番号を、横軸は印加電圧を各々示し、同図 (b
)と同様、傾向な見易(する為に便宜的に0を実線で結
んでいる。
From this, the voltage applied between the positive and negative electrodes of each element is plotted in FIG. The horizontal axis of the figure is ~DN
The horizontal axis shows the applied voltage.
), 0 is connected with a solid line for convenience (to make it easier to see the trend).

本図から明らかなように、同図(a)のような回路の場
合には、両端の素子(D、及びり、)に近い程大きな電
圧が印加され、中央部付近の素子では印加電圧が小さく
なる。
As is clear from the figure, in the case of the circuit shown in figure (a), the closer the elements at both ends (D, and ) are, the greater the voltage is applied, and the applied voltage is lower to the elements near the center. becomes smaller.

従って、各電子放出素子から放出される電子ビームは、
両端の素子程ビーム電流が大きくなり、画像形成装置に
応用した場合極めて不都合であった。(例えば、両端に
近い部分の画像は濃度が濃く、中央部付近の濃度は淡く
なってしまう。) 一方、第1O図に示すのは、並列接続された素子列の片
側(本図では素子D1側)に、電源の正負極を接続した
場合である。この様な回路の場合には、同図 (b)に
示すように、正極側、負極側ともり、に近い程配線抵抗
rによる電圧降下が太き(なる。
Therefore, the electron beam emitted from each electron-emitting device is
The beam current increases toward the elements at both ends, which is extremely inconvenient when applied to an image forming apparatus. (For example, the image near both ends will have a high density, and the image near the center will have a low density.) On the other hand, what is shown in Figure 1O is one side of an element array connected in parallel (in this figure, element D1 This is the case when the positive and negative poles of the power supply are connected to the In the case of such a circuit, as shown in FIG. 3(b), the voltage drop due to the wiring resistance r becomes thicker as the positive electrode side and the negative electrode side are closer to each other.

従って、各素子に印加される電圧は、同図 (c)に示
すように、D、に近い程大きなものとなり、画像形成装
置として応用するには極めて不都合であった。
Therefore, the voltage applied to each element becomes larger as it approaches D, as shown in FIG.

以上、二つの例で示したような素子毎の印加電圧のばら
つきの程度は、並列接続される素子の総数N、素子抵抗
Rdと配線抵抗rの比(= Rd/r) 、あるいは電
源の接続位置により異なるが、一般には、Nが大きい程
、Rd/rが小さい程ばらつきは顕著となり、また前記
第9図よりも第1θ図の接続方法のほうが、素子に印加
される電圧のばらつきが大きい。
As shown in the two examples above, the degree of variation in the applied voltage for each element depends on the total number of elements connected in parallel N, the ratio of element resistance Rd to wiring resistance r (= Rd/r), or power supply connection. Although it differs depending on the position, in general, the larger N is and the smaller Rd/r is, the more pronounced the variation is.Furthermore, the connection method shown in Fig. 1θ has a larger variation in the voltage applied to the element than the connection method shown in Fig. 9. .

例えば、第9図の接続法で素子抵抗Rd=1にΩ、r=
lOmΩの場合、N = 100であれば、印加電圧の
最も大きな素子と最も小さな素子を比較すると、V +
maX:v++t1゜= 102:100程度であるが
、N = 1000であれば、V、、、、:V、、n=
472:100と、ばらつきの割合は大きくなる。
For example, with the connection method shown in Figure 9, the element resistance Rd = 1, Ω, r =
In the case of lOmΩ, if N = 100, comparing the element with the largest applied voltage and the element with the smallest applied voltage, V +
maX:v++t1゜=about 102:100, but if N=1000, then V, , :V,, n=
The dispersion ratio becomes large at 472:100.

また、 N = 1000.Rd = 1 kΩ、r=
1mΩの場合には、V 、、、:V 111= 127
:100程度であるが、r = 10mΩの場合には、
V +++ax:Vat、= 472:100程度とい
うようにばらつきの程度は大きくなる。
Also, N = 1000. Rd = 1 kΩ, r=
In the case of 1 mΩ, V , , :V 111 = 127
: About 100, but when r = 10mΩ,
The degree of variation becomes large, such as V +++ax:Vat, = about 472:100.

以上説明したように、特性の等しい電子放出素子を複数
個並列に接続した場合には、配線抵抗により生ずる電圧
降下の為、各素子に実効的に印加される電圧は素子毎に
ばらついてしまい、電子ビームの放出量が不均一となり
、画像形成装置として応用する場合に不都合であった。
As explained above, when multiple electron-emitting devices with the same characteristics are connected in parallel, the voltage effectively applied to each device varies due to the voltage drop caused by wiring resistance. The amount of emitted electron beam becomes non-uniform, which is inconvenient when applied as an image forming apparatus.

特に、画素数の多い(すなわちNの大きい)大容量表示
装置を実現しようとする場合には、上記ばらつきの割合
は顕著となり、画像の輝度(濃度)むらが大きな問題と
なっていた。
In particular, when attempting to realize a large-capacity display device with a large number of pixels (that is, a large number of N), the rate of variation becomes significant, and uneven brightness (density) of images becomes a major problem.

[課題を解決するための手段(及び作用)]本発明によ
れば、各電子放出素子から放出される電子ビームの通過
と遮断を制御するための変調グリッド電極を設け、各変
調グリッド電極の開口部(空孔)の面積を変えることに
より、どの素子からも等しいビーム電流が゛ターゲット
に照射されるようにしたものである。
[Means for Solving the Problems (and Effects)] According to the present invention, a modulation grid electrode is provided for controlling passage and blocking of electron beams emitted from each electron-emitting device, and an aperture of each modulation grid electrode is provided. By changing the area of the holes (holes), the target is irradiated with the same beam current from all elements.

より詳しくは、電子放出素子が前記第9図のような配線
の場合には、両端よりも中央のグリッド電極の開口面積
を大きくする。また、前記第1O図のような配線の場合
には、素子の給電側から遠いグリッド電極程開口面積を
太き(するものである。
More specifically, when the electron-emitting device has wiring as shown in FIG. 9, the opening area of the grid electrode at the center is made larger than at both ends. In addition, in the case of wiring as shown in FIG. 1O, the grid electrode farther from the power supply side of the element has a larger opening area.

以上の手段により、電圧降下によって生じた電子放出部
からの単位面積当たりの電子ビーム放出量の減少を、変
調グリッド電極の開口面積を拡大することにより実効的
な電子ビームを増加させ、結果として画像形成面におい
ては均一な画像濃度を生じ得るという作用を成すもので
ある。
By the above means, the decrease in the amount of electron beam emitted per unit area from the electron emitting part caused by the voltage drop is compensated for by increasing the effective electron beam by expanding the aperture area of the modulation grid electrode, and as a result, the effective electron beam is increased. This has the effect of producing uniform image density on the forming surface.

[実施例J 以下に、実施例を用いて本発明を具体的に詳述する。[Example J The present invention will be specifically explained in detail below using examples.

第1図〜第7図は、本発明の一実施例である平板型画像
形成装置を説明するものである。
1 to 7 illustrate a flat plate image forming apparatus which is an embodiment of the present invention.

第1図は表示パネルの構造を示しており図中、VCはガ
ラス製の真空容器で、その一部であるFPは表示面側の
フェースプレートを示している。
FIG. 1 shows the structure of a display panel. In the figure, VC is a glass vacuum container, and FP, which is a part of the vacuum container, is a face plate on the display side.

フェースプレートFPの内面には、例えばITOを材料
とする透明電極が形成され、さらにその内側には、赤、
緑、青の蛍光体がモザイク状に塗り分けられ、CRTの
分野では公知のメタルバック処理が施されている。(透
明電極、蛍光体、メタルバックは図示せず、)また、前
記透明電極は、加速電圧を印加する為に端子EVを通じ
て、真空容器外と電気的に接続されている。
A transparent electrode made of, for example, ITO is formed on the inner surface of the face plate FP, and a red,
Green and blue phosphors are painted separately in a mosaic pattern, and a metal back treatment known in the CRT field is applied. (The transparent electrode, phosphor, and metal back are not shown.) Furthermore, the transparent electrode is electrically connected to the outside of the vacuum vessel through a terminal EV in order to apply an accelerating voltage.

また、Sは前記真空容器VCの底面に固定されたガラス
基板で、その上面には、従来技術の項で例示した電子放
出素子が200個×200列にわたり配列形成されてい
る。該電子放出素子群は、列毎に電気的に並列接続され
ており、各列の正極側配線(負極側配線)は、端子op
l〜Dp3゜。(端子Dm+〜Dllio。)によって
真空容器外と電気的に接続されている。すなわち、本装
置では、前述第9図の給電方法による素子列が200列
にわたり基板S上に形成されている。(1列あたりの素
子数は200個である。) また、基板SとフェースプレートFPの中間には、スト
ライブ状のグリッド電極GRが設けられている、グリッ
ド電極GRは、前記素子列と直交して200本設けられ
ており、各電極には、電子ビームを透過する為の空孔G
R(開口)が設けられている。空孔Ghは、第1図の例
では各電子放出素子に対応して1個づつ設けられている
が、後述する様に、電極により空孔の開口面積を適宜変
えであることが特徴である。
Further, S is a glass substrate fixed to the bottom surface of the vacuum container VC, and on the top surface thereof, the electron-emitting devices exemplified in the prior art section are arranged in 200 pieces x 200 rows. The electron-emitting device groups are electrically connected in parallel in each column, and the positive electrode side wiring (negative electrode side wiring) of each column is connected to the terminal op.
l~Dp3゜. (Terminals Dm+ to Dllio.) are electrically connected to the outside of the vacuum container. That is, in this device, 200 element rows are formed on the substrate S using the power feeding method shown in FIG. 9 described above. (The number of elements per row is 200.) Furthermore, a striped grid electrode GR is provided between the substrate S and the face plate FP, and the grid electrode GR is perpendicular to the element row. 200 electrodes are provided, and each electrode has a hole G for transmitting the electron beam.
R (opening) is provided. In the example shown in FIG. 1, one hole Gh is provided corresponding to each electron-emitting device, but as will be described later, the feature is that the opening area of the hole can be changed as appropriate depending on the electrode. .

各グリッド電極GRは端子G、〜G2゜。によって、真
空容器外と電気的に接続されている。
Each grid electrode GR has a terminal G, ~G2°. It is electrically connected to the outside of the vacuum vessel.

本表示パネルでは、200個の電子放出素子列と、20
0個のグリッド電極列により、X Y、マトリクスが構
成されている。電子放出列を一列づつ順次駆動(走査)
するのと同期してグリッド電極列に画像1ライン分の変
調信号を同時に印加することにより、各電子ビームの蛍
光体への照射を制御し、画像を1ラインづつ表示してい
くものである。
This display panel has 200 electron-emitting device rows and 20
An XY matrix is composed of zero grid electrode rows. Sequentially driving (scanning) electron emission columns one by one
By simultaneously applying a modulation signal for one line of the image to the grid electrode array in synchronization with this, the irradiation of each electron beam onto the phosphor is controlled, and the image is displayed line by line.

次に第2図に示すのは、前記第1図の表示パネルに用い
られるグリッド電極GRの一部を示す平面図で、(a)
、 、(b) 、 (c)の3種類を示しである。本図
から明らかなように、各グリッド電極の空孔Ghは、異
なる開口面積をもち、Gha <Ghb <Ghcなる
大小関係にある。
Next, FIG. 2 is a plan view showing a part of the grid electrode GR used in the display panel of FIG. 1, and (a)
Three types are shown: , , (b), and (c). As is clear from this figure, the holes Gh of each grid electrode have different opening areas and have a size relationship of Gha < Ghb < Ghc.

これらの開口面積の異なるグリッド電極GRは、前記第
1図の表示パネルに於て、次の様に用いられている。す
なわち、両端のグリッド電極(G、及びGaoo)に於
ては最も開口の小さな (a)を用い、中央のグリッド
電極GR(G+o。)に於ては最も開口の大きな (c
)を用い、両端と中央の間に於ては中間的な開口面積の
(b)を用いる。
These grid electrodes GR having different opening areas are used in the display panel shown in FIG. 1 in the following manner. That is, for the grid electrodes at both ends (G and Gaoo), use the one with the smallest opening (a), and for the central grid electrode GR (G+o.), use the one with the largest opening (c
), and (b) with an intermediate opening area is used between both ends and the center.

具体的には、例えばG、〜G8゜及びGI’FI−Gl
。aに(a)を、Gs+−Gyo及びGtst−Gty
。に(b)を、G? 1−GI30に (C)を用いて
表示パネルを構成することにより、従来問題となってい
た画像の輝度(濃度)むらを大幅に低減することが可能
となった。
Specifically, for example, G, ~G8° and GI'FI-Gl
. (a) in a, Gs+-Gyo and Gtst-Gty
. (b) to G? By constructing a display panel using (C) in 1-GI30, it has become possible to significantly reduce the uneven brightness (density) of images, which has been a problem in the past.

この開口面積の異なるグリッド電極の効果を説明する為
に、電子放出素子の出力特性を第3図に、グリッド電極
の動作特性を第4図に示す。
In order to explain the effects of grid electrodes having different opening areas, the output characteristics of the electron-emitting device are shown in FIG. 3, and the operating characteristics of the grid electrode are shown in FIG. 4.

第3図に示すのは、本表示パネルに用いた電子放出素子
の出力特性の一例である。(電子放出素子には、従来技
術の冒頭で例示した冷陰極素子、薄膜熱カソード、MI
M型放出素子、あるいはこれらに類似するもの等多数個
を配列形成できるものであれば良い、従って、第3図の
出力特性は、これらの中のほんの一例にすぎないが、本
発明は電子放出素子の特性が異なるものであっても、適
宜、グリッド電極の開口面積を調整することにより、同
様の効果を発揮するものである。)本図に於て、横軸は
電子放出素子に印加される電圧で、縦軸は電子放出素子
から放射される出力ビーム電流である。第9図 (C)
で説明したように、並列接続した電子放出素子に於ては
、印加電圧にばらつきが生じ(便宜上、印加電圧の最大
値をVmax、最小値をVminと表わす。)、第3図
のグラフから明らかなように、Vmaxが印加される素
子(列の両端、すなわちり、とD2゜。)からはEBm
axの電子ビームが放射され、またVIIIinが印加
される素子(列の中央、すなわちDl。。)からはEB
minの電子ビームが放射される。
FIG. 3 shows an example of the output characteristics of the electron-emitting device used in this display panel. (Electron-emitting devices include cold cathode devices, thin film hot cathodes, and MI
Any device capable of arraying a large number of M-type emitting devices or devices similar to these devices may be used. Therefore, the output characteristics shown in FIG. 3 are only one example of these, but the present invention Even if the characteristics of the elements are different, similar effects can be achieved by appropriately adjusting the opening area of the grid electrode. ) In this figure, the horizontal axis is the voltage applied to the electron-emitting device, and the vertical axis is the output beam current emitted from the electron-emitting device. Figure 9 (C)
As explained above, in electron-emitting devices connected in parallel, variations occur in the applied voltage (for convenience, the maximum value of the applied voltage is expressed as Vmax, and the minimum value as Vmin), which is clear from the graph in Figure 3. As shown, from the element to which Vmax is applied (both ends of the column, i.e., and D2°), EBm
EB is emitted from the element (center of the column, ie Dl...) to which the electron beam of ax is emitted and VIIIin is applied.
An electron beam of min is emitted.

説明を簡単にする為、前記EBmax及びEBminを
出力する素子だけについて述べるが、本発明によれば、
EBmaxを出力する素子に対しては開口面積の最も小
さなグリッド電極を用い、逆にEBminを出力する素
子に対しては開口面積が最も大きなグリッド電極を用い
ている。
To simplify the explanation, only the elements that output EBmax and EBmin will be described, but according to the present invention,
The grid electrode with the smallest opening area is used for the element that outputs EBmax, and the grid electrode with the largest opening area is used for the element that outputs EBmin.

従って、第4図に示すように、表示パネルの蛍光面電位
(加速電圧)を一定(例えばl0KV)にし、同時にグ
リッド電極の引き出し電圧を一定(例えば15KV)に
した場合は、グリッド電極空孔Ghを通じて蛍光面に到
達する電流は、EBmaxの素子もEBminの素子も
等しくなる。
Therefore, as shown in FIG. 4, when the phosphor screen potential (acceleration voltage) of the display panel is kept constant (for example, 10 KV) and the grid electrode extraction voltage is kept constant (for example, 15 KV), the grid electrode void Gh The current reaching the phosphor screen through the EBmax element and the EBmin element are equal.

以上の説明から明らかなように、グリッド電極の開口面
積を電子放出素子の出力ビーム電流にあわせて適宜変え
ておくことにより、表示パネルの輝度(濃度)むらを大
幅に低減することができる。前述したように本実施例で
は、第2図 (a)。
As is clear from the above description, by appropriately changing the opening area of the grid electrode in accordance with the output beam current of the electron-emitting device, it is possible to significantly reduce the brightness (density) unevenness of the display panel. As mentioned above, in this embodiment, FIG. 2(a).

(b) 、 (e)の3種の開口面積のものを用いたが
、より精密に輝度(濃度)むらを低減させる為には、各
グリッド電極毎に開口面積を変えてやれば良い。
Although three types of opening areas (b) and (e) were used, in order to more precisely reduce unevenness in brightness (density), the opening area may be changed for each grid electrode.

第5図に、各グリッド電極の開口面積を略図で示すが、
各グリッド電極毎に異なる開口を形成することは、ホト
リソグラフィー・エツチング技術により容易に可能であ
る。
FIG. 5 schematically shows the opening area of each grid electrode.
It is easily possible to form different openings for each grid electrode using photolithography and etching techniques.

発明者等は、第5図のようなグリッド電極を用いて、平
板形画像形成装置を試作した結果、本発明を適用しない
場合(すなわち、全ての素子に対して同一開口面積のグ
リッド電極を用いた場合)と比較して、発光の輝度(濃
度)むらをl/、。以下に低減させることに成功した。
The inventors prototyped a planar image forming apparatus using grid electrodes as shown in FIG. The luminance (density) unevenness of the emitted light is 1/. We succeeded in reducing it to below.

次に、本実施例の表示パネルの駆動方法の概略を説明す
る。
Next, the outline of the method for driving the display panel of this embodiment will be explained.

第6図に示すのは、前記第1図の表示パネルを駆動する
為の電気回路をブロック図として示したもので、図中、
lは第1図で示した表示パネル。
FIG. 6 shows a block diagram of an electric circuit for driving the display panel shown in FIG.
1 is the display panel shown in FIG.

2は素子列駆動回路、3は変調グリッド駆動回路、4は
高電圧電源である。表示パネル1の電極端子EVには、
高電圧電源4からl0KV程度の加速電圧が供給される
。また、電子放出素子列の負極側配線端子(Da、〜D
m*。。)は、グランドレベル(OV)に接地され、正
極側の配線端子(Dp−apl。。)は素子列駆動回路
2と接続されている。また、グリッド電極は、端子G、
〜G8゜。を通じて変調グリッド駆動回路3と接続され
ている。
2 is an element array drive circuit, 3 is a modulation grid drive circuit, and 4 is a high voltage power supply. In the electrode terminal EV of the display panel 1,
An accelerating voltage of about 10 KV is supplied from the high voltage power supply 4. In addition, the negative electrode side wiring terminals (Da, ~D
m*. . ) is grounded to the ground level (OV), and the positive electrode side wiring terminal (Dp-apl...) is connected to the element column drive circuit 2. In addition, the grid electrode has terminal G,
~G8°. It is connected to the modulation grid drive circuit 3 through.

さらに、素子列駆動回路2及び変調グリッド駆動回路3
からは、第7図の駆動タイムチャートに示すタイミング
で信号電圧が出力される。第7図中(a)〜(d)は、
素子列駆動回路2から表示パネルlのDp+、Dps、
Dps、及びDI。。端子に印加される信号を示すが、
図から分かる通り、Dp+、Da雪。
Furthermore, an element array drive circuit 2 and a modulation grid drive circuit 3
From there, a signal voltage is output at the timing shown in the drive time chart of FIG. (a) to (d) in Figure 7 are
Dp+, Dps, of the display panel l from the element column drive circuit 2;
Dps, and D.I. . Indicates the signal applied to the terminal,
As you can see from the figure, Dp+, Da snow.

Dps、 ass (DI)4− Dp+ssは図中路
) 、09*ooの順に、順次、振幅vi [V]の駆
動パルスが印加される。これと同期して変調グリッド駆
動回路3からは、端子GI−G鵞◎0に対し、第3図(
e)に示すタイミングで変°調信号(v6(ON)また
はV、(OFF) )が印加される。各端子に対してV
、(ON)レベル、 Va(OFF)レベルのどちらが
印加されるかは、表示画像のパターンにより決まるもの
である。
Driving pulses with an amplitude vi [V] are sequentially applied in the order of Dps, ass (DI)4-Dp+ss (in the figure), and 09*oo. In synchronization with this, the modulation grid drive circuit 3 sends a signal to the terminal GI-G ◎0 as shown in Fig. 3 (
A modulation signal (v6 (ON) or V, (OFF)) is applied at the timing shown in e). V for each terminal
, (ON) level, or Va (OFF) level is determined by the pattern of the displayed image.

以上、本発明の一実施例について説明したが、本発明の
実施形態はこれに限るものではなく、例えば、電子放出
素子が前記第1θ図の給電方法で配線されている場合に
は、給電側に近い素子に対するグリッド電極(即ちG、
側)よりも、給電側から遠い素子に対するグリッド電極
(即ちa黛OO側)程空孔の開口面積を大きくすること
が輝度(濃度)むらを低減するのに有効である。
Although one embodiment of the present invention has been described above, the embodiment of the present invention is not limited to this. For example, when the electron-emitting device is wired using the power feeding method shown in the above-mentioned Fig. 1θ, the power feeding side Grid electrodes for elements close to (i.e. G,
It is effective to reduce brightness (concentration) unevenness by increasing the opening area of the holes as the grid electrode for the element is farther away from the power supply side (ie, on the a-OO side) than on the side).

また、グリッド電極に設ける空孔は、各電子放出素子に
対して、必ずしも1個である必要はなく、例えば、第8
図に示すように多数の孔からなるメツシュ状のものでも
よい、その場合には、同図(a) 、 (b) 、 (
c)に示すように、形成する孔の個数を変えることによ
り、開口面積を変化させることが可能である。
Further, the number of holes provided in the grid electrode does not necessarily have to be one for each electron-emitting device;
As shown in the figure, a mesh-like structure consisting of a large number of holes may also be used.
As shown in c), it is possible to change the opening area by changing the number of holes to be formed.

【発明の効果] 以上説明したように、本発明では、グリッド電極に設け
た空孔の開口面積を、電子放出素子から放出される電子
ビーム電流のばらつきに応じて、異なった大きさとする
ことにより、蛍光面に到達するビーム電流を素子によら
ず均一にすることが可能である。これにより、従来問題
となっていた画像の輝度(濃度)むらを解消でき薄形で
大面積の大容量画像形成装置の実用性能を大幅に向上す
ることができた。
[Effects of the Invention] As explained above, in the present invention, the opening area of the holes provided in the grid electrode is made to have different sizes depending on the variation in the electron beam current emitted from the electron-emitting device. , it is possible to make the beam current reaching the phosphor screen uniform regardless of the element. As a result, the conventional problem of uneven image brightness (density) can be solved, and the practical performance of a thin, large-area, large-capacity image forming apparatus can be greatly improved.

本発明の適用は、実施例で示したような平板形画像形成
装置以外に、電子放出素子を多数個並列接続した電子源
部を有する画像形成装置の殆どに適用が可能で、例えば
電子ビーム描画装置や画像記録装置の分野にも極めて有
効なものである。
The present invention can be applied to most image forming apparatuses having an electron source section in which a large number of electron-emitting devices are connected in parallel, in addition to the flat image forming apparatus shown in the embodiments, such as electron beam lithography. It is also extremely effective in the field of devices and image recording devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、表示パネルの一部を示す斜視図、第2図は、
表示パネルに用いられる変調グリッド電極の一部平面図
、 第3図は、本画像形成装置に用いられる電子放出素子の
出力特性を示す図、 第4図は、変調グリッド電極の動作特性を示す図、 第5図は、各変調グリッド電極に形成された開口部の面
積を簡略に示すためのグラフ、第6図は、表示パネルを
駆動するブロック回路を示す図、 第7図は、表示パネルの駆動タイミングを示すタイムチ
ャート、 第8図は、他の実施態様を示すグリッド電極の一部平面
図、 第9図、第1θ図は、従来問題点を説明する為の図であ
る。 1−表示パネル     GR−グリッド電極2−素子
列駆動回路   Gh−空孔 3−変調グリッド駆動回路 4−高電圧電源
FIG. 1 is a perspective view showing a part of the display panel, and FIG. 2 is a perspective view showing a part of the display panel.
FIG. 3 is a partial plan view of a modulation grid electrode used in a display panel; FIG. 3 is a diagram showing the output characteristics of an electron-emitting device used in this image forming apparatus; FIG. 4 is a diagram showing operating characteristics of the modulation grid electrode. , FIG. 5 is a graph to simply show the area of the opening formed in each modulation grid electrode, FIG. 6 is a diagram showing a block circuit for driving the display panel, and FIG. 7 is a graph showing the area of the opening formed in each modulation grid electrode. FIG. 8 is a partial plan view of a grid electrode showing another embodiment; FIG. 9 and FIG. 1θ are diagrams for explaining conventional problems. 1 - Display panel GR - Grid electrode 2 - Element row drive circuit Gh - Hole 3 - Modulation grid drive circuit 4 - High voltage power supply

Claims (3)

【特許請求の範囲】[Claims] (1)複数の電子放出素子を電気的に並列に配線したマ
ルチ電子ビーム源と、前記電子放出素子から放出される
電子ビームの通過と遮断を行う為の複数の変調グリッド
電極と、電子ビームの照射により画像を形成する為のタ
ーゲットとを具備し、前記複数の変調グリッド電極には
、前記電子放出素子に印加される電圧に応じて、異なる
開口面積を有した電子ビームの通過用の空孔が設けられ
ていることを特徴とする画像形成装置。
(1) A multi-electron beam source in which a plurality of electron-emitting devices are electrically wired in parallel, a plurality of modulation grid electrodes for passing and blocking the electron beams emitted from the electron-emitting devices, and a plurality of modulation grid electrodes for passing and blocking the electron beams emitted from the electron-emitting devices; a target for forming an image by irradiation, and each of the plurality of modulation grid electrodes has a hole through which an electron beam passes, the opening area of which varies depending on the voltage applied to the electron-emitting device. An image forming apparatus characterized by being provided with.
(2)前記マルチ電子ビーム源において、並列接続され
た電子放出素子列の一端から正電圧を、他端から負電圧
を印加し得るよう給電手段が設けられ、かつ、前記変調
グリッド電極に設けられている空孔の開口面積が該素子
列の両端の素子に対するものよりも、該素子列の中央の
素子に対するものの方が大きくなっていることを特徴と
する請求項1記載の画像形成装置。
(2) In the multi-electron beam source, a power feeding means is provided so that a positive voltage can be applied from one end of the parallel-connected electron-emitting device array and a negative voltage can be applied from the other end, and the power feeding means is provided on the modulation grid electrode. 2. The image forming apparatus according to claim 1, wherein the opening area of the hole is larger for an element at the center of the element array than for elements at both ends of the element array.
(3)前記マルチ電子ビーム源において、並列接続され
た電子放出素子列の一端に該素子を駆動する為の正電圧
と負電圧を給電する手段が設けられ、かつ、変調グリッ
ド電極に設けられている空孔の開口面積が該素子列の前
記給電手段が設けられた一端に近い素子に対するものよ
りも、遠い素子に対するものの方が大きくなっているこ
とを特徴とする請求項1記載の画像形成装置。
(3) In the multi-electron beam source, means is provided at one end of the row of electron-emitting devices connected in parallel to supply a positive voltage and a negative voltage for driving the devices, and means is provided at the modulation grid electrode. The image forming apparatus according to claim 1, wherein the opening area of the hole is larger for an element far away than for an element near one end of the element array where the power feeding means is provided. .
JP7661189A 1989-03-30 1989-03-30 Image forming device Pending JPH02257551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7661189A JPH02257551A (en) 1989-03-30 1989-03-30 Image forming device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7661189A JPH02257551A (en) 1989-03-30 1989-03-30 Image forming device

Publications (1)

Publication Number Publication Date
JPH02257551A true JPH02257551A (en) 1990-10-18

Family

ID=13610139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7661189A Pending JPH02257551A (en) 1989-03-30 1989-03-30 Image forming device

Country Status (1)

Country Link
JP (1) JPH02257551A (en)

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