JPH02250331A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device whose reliability is high and which has been made fine by a method wherein a drain region is constituted of a low-concentration region and of a high-concentration region and the low- concentration region is formed in such a way that it is overlapped stably with a gate electrode and that its surface concentration is nearly definite in a transverse direction. CONSTITUTION:The following are formed on the surface of a semiconductor substrate 1: a low-concentration N<-> type semiconductor region 5 which has been doped with phosphorus of a prescribed amount; a high-concentration N<+> type semiconductor region 6 which has been doped with arsenic of a prescribed amount. The N<-> type semiconductor region 5 is formed in such a way that it is over-lapped stably with a gate electrode 3 over a prescribed length. That is to say, since the N<-> type semiconductor region is formed so as to be overlapped stably with the gate electrode and so as to be a nearly definite concentration at their overlapped part, it is possible to reduce hot carriers and to make a parasitic resistance small. Thereby, since reliability of a MOS transistor can be enhanced and its driving capacity can be enhanced, a high-performance integrated circuit which has been made fine can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices and their manufacturing technology, particularly MIS
The present invention relates to FETs, and more specifically, to high-performance, highly reliable miniaturized MISFETs and their manufacturing technology.

[Conventional technology]

With the miniaturization of semiconductor integrated circuits, deterioration in reliability due to hot carriers generated during operation has become a problem, and for this reason, the so-called LDD structure in which the drain region is composed of a low concentration region and a high concentration region has recently been developed. It is starting to be used.

This kind of semiconductor device having an LDD type structure is described, for example, in "Electronic Materials", June 1985 issue, published by Kogyo Kenkyukai, pages 64 to 73.

[Problem to be solved by the invention]

By the way, in the conventional LDD structure, the hot carrier resistance is improved by the low concentration region, but on the other hand, there is a trade-off in that the current driving ability, that is, the performance decreases because this low concentration region acts as a parasitic resistance.
This trade-off is getting bigger.

The present invention seeks to resolve the above trade-off.

That is, an object of the present invention is to provide a highly reliable miniaturized M
An object of the present invention is to provide a semiconductor device such as an ISFET.

Another object of the present invention is to provide a high driving capacity M that is suitable for high-speed operation.
An object of the present invention is to provide a semiconductor device such as an ISFET.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device that achieves stable characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the semiconductor device of the present invention, the drain region is composed of a low concentration region and a high concentration region, the low concentration region has stable overlap with the gate electrode, and the surface concentration thereof is approximately constant in the lateral direction. do it like this. Further, the gate electrode has a substantially vertical shape, and the low-concentration and high-concentration drain regions are defined by the gate electrode.

Further, in the method of manufacturing a semiconductor device of the present invention, impurities are doped into the surface of the semiconductor substrate by angular ion implantation in the low concentration region by penetrating the edge of the gate electrode, and in the high concentration region, impurities are doped from the substantially vertical direction. This is achieved by performing ion implantation.

[Effect]

Since the low concentration drain region has a stable overlap with the gate electrode and the surface concentration at the overlap part is constant,
During operation, the largest field on the surface of the semiconductor substrate is located within the low concentration region and inside the surface. Therefore, the generation of hot carriers at the surface is suppressed, so deterioration due to hot carrier injection is suppressed. Furthermore, since the generated hot carriers are mainly injected into the gate insulating film on the low concentration region under the gate electrode, the low concentration region is not easily modulated during operation.

Furthermore, since the low concentration region itself has a large electric field effect due to the gate electrode, there is no adverse effect as a parasitic resistance, and the region has high driving ability.

Furthermore, the low concentration region can be arbitrarily determined by the angle of ion implantation, the implantation energy dose, and these are controlled very well, so that problems such as variations in characteristics can be prevented from occurring.

〔Example〕

'JR1 is a sectional view showing the first embodiment of the present invention, FIG. 2 is a sectional view showing the second embodiment of the present invention, FIG. 3 is a sectional view showing the third embodiment of the present invention, and FIG. 5 to 7 are cross-sectional views showing the method of manufacturing a semiconductor device according to the invention.

In FIG. 1, a 12 nm gate insulating film 2 is formed on a P-type semiconductor substrate 1, and the gate insulating film 2 is made of a polycrystalline silicon film doped with an N-type impurity, such as phosphorus, and a metal silicide, such as WS12. A gate electrode 3 is formed. I'm getting angry.

Further, on the surface of the semiconductor substrate 1, 1012 to 103/
A low concentration N-type semiconductor region 5 doped with ctl phosphorus and having a depth of about 0.1 μm, and a high concentration N-type semiconductor region 6 doped with 5×10”/cd arsenic and having a depth of about 0.2 μm. The N- type semiconductor region 5 and the N+ type semiconductor region 6 constitute an LDD structure.N-
The type semiconductor region 5 is 0.1 to 0.2 μm thick with the gate electrode 3.
They are formed with a certain degree of stable overlap.

In the second embodiment shown in FIG. 2, the N-type semiconductor region 6 is
A side wall spacer 7 is provided so as to be spaced apart from the gate electrode 3. The other configurations are the same as in FIG.

In the third embodiment shown in FIG.
An intermediate concentration N-type semiconductor region 8 is provided between the ゛-type semiconductor region 6 and
is formed. N-type semiconductor region 8 is 1013 to 10
It is doped with arsenic of 14/CrI and formed to a depth of about 0.15 μm.

The N- type semiconductor region 5 shown in FIGS. 1 to 3 has a lateral concentration distribution as shown in FIG.

That is, the surface concentration of the N- type semiconductor region 5 is approximately constant in the lateral direction.

Next, the manufacturing process of semiconductor devices according to Examples 1 to 3 of the present invention will be explained based on FIGS. 5 to 7.

First, as shown in FIG. 5, a field oxide film for element isolation is formed on a P-type semiconductor substrate 1, and then a 12-layer gate oxide film is formed by thermal oxidation to form a gate insulating film 2. Channel doping to adjust the threshold voltage is done before or after gate oxidation.

Next, IQQn is deposited on the surface of the semiconductor substrate l by the CVD method.
A polycrystalline silicon film 3a having a thickness of m is formed and doped with phosphorus by diffusion or ion implantation.

Next, a layer of 150
After forming the WSi film 3b with a thickness of 1 nm, the WSi2 film 3b and the polycrystalline silicon film 3a are sequentially etched using a resist as a mask to form the gate electrode 3.

Next, as shown in FIG. 6, the semiconductor substrate 1 is oxidized,
A silicon oxide film 4 is formed. Then, for example, 5810 phosphorus at 150-200 kev at an angle of 45 degrees
At this time, ions are not implanted in the region shaded by the gate electrode 3 as shown in FIG. A semiconductor region 5 is formed.The angle and energy of ion implantation depend on the height of the gate electrode 3, that is, the polycrystalline silicon film 3a and the WSi2 film 3b.
It is determined by taking into consideration the film thickness of the film, the coarse density of the pattern, and the amount of overlap between the gate electrode 3 and the N- type semiconductor region 50.

Next, as shown in FIG. 7, arsenic is ion-implanted from the vertical direction, for example, at 60 keV to 5810 inches. As a result, an N+ type semiconductor region 6 is formed using the gate as a mask.

Furthermore, in order to manufacture the semiconductor devices shown in Example 2 of FIG. 2 and Example 3 of FIG. 3, the steps shown in FIG. 7 are additionally performed.

That is, as shown in FIG. 7(a), 2
X10"cnf ions are implanted to form an N-type semiconductor region 8. Note that in Example 2, the N-type semiconductor region 8 is not formed. Next, as shown in FIG. 7(b), CV
After forming a 3001m silicon oxide film by method D,
Sidewall spacers 7 are formed by reactive ion etching. Next, after forming a silicon oxide film on the exposed surface of the semiconductor substrate 1 by thermal oxidation, arsenic is applied 5× at 50 keV from a direction perpendicular to the semiconductor substrate 1.
10"/c- ions are implanted and heat treated to form an N"" type semiconductor region 6. Further, heat treatment is performed at 900 DEG C. for about 10 minutes to activate the implanted impurities.

After this, formation of a normal PSG or BPSG film, formation of contact regions, formation of electrodes and wiring, formation of passivation, etc. are performed.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above description, the invention made by the present inventor is mainly applied to MISFET, which is its field of application, but the invention is not limited to this, and can be applied to other semiconductor devices, for example.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, according to the present invention, the N-type semiconductor region is formed to have a stable overlap with the gate electrode, and the C concentration is approximately constant in the overlapped portion.
) The generation of hot carriers can be reduced. (2) Parasitic resistance can be reduced. There are other effects.

This makes it possible to improve the reliability of the MOS transistor and increase its driving capability, thereby realizing a miniaturized, high-performance integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of Embodiment 1 of the present invention, Fig. 2 is a sectional view of Embodiment 2 of the present invention, Fig. 3 is a sectional view of Embodiment 3 of the present invention, and Fig. 4 is a cross-sectional view of Embodiment 3 of the present invention. 5 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. 1... Semiconductor substrate, 2... Gate insulating film, 3...
Gate electrode, 3a... polycrystalline silicon film, 3b...
W3i2 film, 4... silicon oxide film, 5... N- type semiconductor region, 6... N. type semiconductor region, 7... side wall spacer, 8.
...N-type semiconductor region. Figure 1 Figure 4 Figure 5 Figure 8 FN type semiconductor device Figure Figure

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type, a gate electrode provided on the surface of the semiconductor substrate via a gate insulating film, and a source and drain region defined by the gate electrode. , the gate electrode has a substantially vertical shape, and at least one of the source and drain has a low concentration region and a high concentration region, and the low concentration region extends from an end of the gate electrode in the channel direction. A semiconductor device characterized by having a region in which the surface concentration is approximately constant in the lateral direction. 2. The semiconductor device according to claim 1, wherein at least one of the source and drain has an intermediate concentration region between the low concentration region and the high concentration region. 3. The semiconductor device according to claim 1 or 2, wherein the high concentration region is separated from the gate electrode by a sidewall spacer. 4. Claims 1 and 2 characterized in that it is a MISFET.
or the semiconductor device according to 3. 5. In the low concentration region, impurities are doped into the surface of the semiconductor substrate by penetrating the edge of the gate electrode by angular ion implantation, and in the high concentration region and the intermediate concentration region, ions are implanted from a substantially vertical direction. Claim 1 characterized by
A method of manufacturing the semiconductor device described above. 6. Manufacturing the semiconductor device according to claim 2 or 3, wherein the sidewall spacer is formed by forming a silicon oxide film over the entire upper surface of the semiconductor substrate and then performing reactive ion etching. Method.