JPH02244479A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a sensor amplifying circuit, to eliminate the need of a selection use signal line of an output of the sense amplifier, and to contrive a high integration by constituting the sense amplifying circuit which is set to a non-selection state by a selecting circuit so as to output fixed data of a logical level. CONSTITUTION:This device is provided with a selecting circuit 7 for selecting only one of sense amplifying (S/A) circuits 21-2n and setting it to an active state, based on address information AS, and the S/A circuits 21-2n which are set to a non-selection state by the selecting circuit 7 output fixed data of a logical level. In such a way, since only one of the S/A circuits 21-2n becomes an active state, when the number of S/A circuits 21-2n is (n) pieces, the lower consumption as the whole S/A circuit becomes 1/n. Also, since the S/A circuits 21-2n at the time of non-selection are constituted so as to output fixed data, an area of the wiring occupied on a chip can be decreased relatively due to a fact that a signal line for selecting an S/A output becomes unnecessary. Thus the power consumption of the sense amplifying circuit is reduced, a selection use signal line of an output of the sense amplifier becomes unnecessary, and a high integration can be contrived.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor memory device, particularly a semiconductor memory device including a sense amplifier (S/A) circuit for each cell block of a memory cell array divided into a plurality of cell blocks. The purpose is to reduce the power consumption of the S/A circuit, eliminate the need for a signal line for selecting the S/A output, and contribute to high integration. The sense amplifier circuit is provided with a selection circuit that selects only one of the sense amplifiers and makes it active, and the sense amplifier circuit that is made non-selected by the selection circuit is configured to output data at a fixed logic level.

[Industrial Application Field] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a sense amplifier (S/A) circuit for each cell block of a memory cell array divided into a plurality of cell blocks. Regarding.

[Prior Art] FIG. 4 shows the overall configuration of a semiconductor memory device as an example of a conventional type.

In the figure, 41 indicates a plurality of cell blocks 4L to 41. , a memory cell array divided into 42. 42 are S/A circuits provided corresponding to the cell blocks 41□ to 41fi, respectively; 43. ~43. are the S/A circuits 42, respectively.
+ to 427, a Nantes gate 44 responds to the output of the Nantes gate, 45 latches a part of the output of the Nantes gate 44 and outputs it to the outside, 46 is a data output buffer. An address buffer that launches a part of the address signal ADD from the outside and outputs part of the address signal as address information SAS; 47 is a decoder that selects a memory cell based on the latched address signal ADD; 4g is an output In response to the enable signal ■, the S/A circuits 421-42. An S/A activation circuit 49 supplies a precharge signal P and an S/A enable signal SE to the Nant gates 43, . 2 shows an S/A output selection circuit supplying signals SL, -5L;

When reading data in this configuration, for example, when reading data directly from the cell block 41,
2n to the reset state, ■S/A enable signal SR
By supplying all the S/A circuits 421 to 427 to the active state (selected state), the S/A circuits 42. Set only the selection signal SL corresponding to the "H" level to open the Nantes gate 43□, and select the selection signal SL+~5Li-,,SL,,,~ corresponding to the other S/A circuits.
All SLn are set to "L" level and Nantes Gate 43. The output of ~43i-,,43i,,~43fi is “
The S/A circuit 42
The outputs of 1 to 4h-142t-t to 427 are not reflected in the output of the Nant gate 44, but are reflected in the output of the S/A circuit 42. Only the output of is reflected in the output of the Nant gate 44 and read out to the outside via the data output buffer 45.

FIG. 5 shows an example of the configuration of the S/A circuit in FIG. 4. Furthermore, unless otherwise specified in the following description,
The term "transistor" refers to an "n-channel transistor."

This S/A circuit is connected between a high potential power supply line VCC and an output terminal 011T (OUT), and is connected to a node Nl (N
P-channel transistor 51 (5
2) and output terminal 0UT (ffi and low potential power supply line V
S/A input data IN connected in series between SS
Transistor 53 (54) responsive to the signal at node Nl (N2), transistor 55 responsive to the signal at node Nl (N2)
(56) and a transistor 57 (58) responsive to the S/A enable signal SE, and responsive to a signal at a node Nl (N2) connected in series between the power supply line VCC and the drain end of the transistor 55 (56). P-channel transistor 59 (60) responsive to S/A input data IN (IN) and transistor 61 (62) responsive to S/A input data IN (IN).
) and node Nl (connection point of transistors 59 and 61)
and node N2 (connection point of transistors 60 and 62)
The transistor 63 is connected between the output terminals OUT and OUT and responds to the precharge signal P, and the transistor 64 is connected between the pair of output terminals OUT and OUT and responds to the precharge signal P.

In this S/A circuit configuration, for example, when ("H", "L") is input as the S/A input card data N, IN, when the S/A enable signal SE is at the "H" level, the transistor 57 and 58 are turned on, thereby lowering the source potentials of transistors 55 and 56.

On the other hand, since the gates of the transistors 55 and 56 are applied with the levels of the nodes Nl and N2, which have been determined to have a potential determined by the reset based on the application of the precharge signal P, the transistors 55 and 56 are both turned on. As a result, the source potentials of the transistors 53, 54, 61.62 are lowered, but only the transistors 54.61 are turned on because ("H", "L") is input as data (IN, IN). When the transistor 61 is turned on, the potential of the node N1 is lowered to the "L" level, which turns on the transistor 51, and the output terminal OUT
The potential of is raised to the "H" level.

On the other hand, when the transistor 54 is turned on, the potential of the output terminal OUT is lowered to "Level". That is, the output (OUT, field) of the S/A circuit exhibits ("H" Ill).

Conversely, as input data (IN, π) (“L”, “H”
) is input, the output (OUT, ?iTim is (”
L", "11#).

That is, the S/A circuit enters the active state upon receiving the S/A enable signal SE at the "H" level, and its output (
OUT, ] exhibits a logic level according to input data (IN, IN). In this state, depending on the logic level of input data, the power supply line VCC is connected to the transistor 51 (
60), 53 (62), 55 (56) and 57 (5B) to the power supply line VSS, or from the power supply line ■Cc to the transistor 59 (52),
61 (54), 55 (56) and 57 (5
8), a current flows to the power supply line VSS.

Therefore, power is consumed according to the current value.

On the other hand, when the S/A enable signal SE is at "L" level,
Since the transistors 57 and 58 maintain the cutoff state, the level of the pair of output terminals OUT and 0tlT becomes a floating state.

[Problem to be solved by the invention]

According to the conventional configuration described above, the S/A enable signal SE is supplied to all S/A circuits when reading data. Therefore, when reading data from a cell block consisting of a cell block, S/A circuits corresponding to other cell blocks that are not involved in reading data are also in an active state (selected state), so power is reduced in the S/A circuit. The disadvantage is that it is wasted.

In addition, since the selection signals SL and -SL are used to select the output of the S/A circuit, the selection signals 43 and 437 for controlling the passage of the output of the S/A circuit and the selection signal SL and -SL are used. A circuit 49 for generating a signal is required, and as a matter of course, wiring for the selection signal is also required.

Such circuit elements and wiring are integrated and formed on a chip, but in general, the area that the wiring area occupies on the chip is relatively small compared to the area that other circuit elements etc. occupy on the chip. It is known that it is large. Therefore, in order to achieve higher memory integration, it is of course necessary to simplify the circuit configuration, but it is particularly effective to reduce the area occupied by the wiring on the chip as much as possible. .

The present invention was created in view of the problems in the prior art, and reduces the power consumption of the S/A circuit, eliminates the need for a signal line for selecting the S/A output, and contributes to high integration. The purpose of the present invention is to provide a semiconductor memory device that can perform the following steps.

[Means to solve the problem]

The problem with the above-mentioned conventional technology is to transform the signal (SE) used for activating all S/A circuits into a signal for selectively activating the S/A circuits. It is solved by

Therefore, the semiconductor memory device according to the present invention is a semiconductor memory device that includes an S/A circuit for each cell block of a memory cell array divided into a plurality of cell blocks, and is configured to select one of the S/A circuits based on address information. a selection circuit that selects only one S/A circuit and makes it active;
The S/A circuit rendered unselected by the selection circuit is characterized in that it outputs data at a fixed logic level.

[Effect]

According to the above-mentioned configuration, only one of the S/A circuits is in the active state (selected state), so for example, the S/A circuit
When the number of A circuits is n, the power consumption of the entire S/A circuit is reduced to 1/n compared to the conventional type.

In addition, since the S/A circuit is configured to output fixed data when not selected, the S/A circuit as seen in the conventional type
A signal line for selecting the A output is not required, thereby making it possible to relatively reduce the wiring area occupied on the chip. This contributes to high integration.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the overall configuration of a semiconductor memory device as an embodiment of the present invention. However, the illustrated example only shows the configuration of the data read system according to the present invention.

In the figure, l is a memory cell array in which SRAM cells (not shown) are arranged in a matrix, and this matrix of cells consists of n cell blocks l, ~1
It is divided into n. 2°~2. ．． are S/A circuits provided corresponding to cell blocks 11 to 1.1, respectively, and each has a corresponding S/A enable signal S.
-SE and precharge signal P, it has a function of detecting and amplifying signals read out from memory cells selected based on address decoding to corresponding data line pairs DL and DL, respectively.

The output of each S/A circuit 21 to 27 is input to a Nant gate 3, and the output of the Nant gate is sent to a data output buffer 4.
After being temporarily latched, it is taken out to the outside. 5 is an address buffer that temporarily latches the address signal ADD from the outside and outputs part of the address signal (k bits, however, 2≧n) as address information AS, and 6 is the address latched by the address buffer. 3 shows a decoder that selects a memory cell based on a signal ADD.

7 is an S/A selection circuit, which selects the S/A selection circuit when the low active output enable signal from the outside is at "L" level.
The "H" level precharge signal P is output to the circuits 21 to 211, and the S/A circuits 21 to 2. , and has a function of outputting an S/A enable signal S-SR for activating one of the S/A enable signals S-SR. In this embodiment, when this S/A enable signal is at the "H" level, the S/A circuit is in the active state (selected state), and the S/A circuit is in the "L" level.
``At level, it becomes inactive (non-selected).

FIG. 2 shows the S/A circuit 2 in FIG. - An example configuration is shown.

In the same figure, a high potential power supply line VCC and an output terminal o
There is an S/A enable signal Sl between U T (m
l! = 2-responsive p-channel transistor IH12)
is connected, and a node Nl (
p-channel transistor 13 (
14) is connected. Between the output terminal 0υr (m) and the low potential power supply line v3., there is a transistor 15 (16) that responds to the complementary data signal (data IN) from the corresponding cell block li, and a node Nl (N2). A transistor 17 (1B) responsive to the signal and a transistor 19 (20) responsive to the S/A enable signal S1 are connected in series.

Also, the power line ■. and the drain end of transistor 17 (1B), there is a p-channel transistor 21 (22) that responds to the signal at node Nl (N2), and a transistor 23 that responds to data IN (complementary data IN).
(24) are connected in series. Furthermore, a transistor 25 that responds to the precharge signal P is connected between the connection point of the transistors 21.23 (node Nl) and the connection point of the transistors 22.24 (node N2), and the transistor 25 that responds to the precharge signal P is connected between the pair of output terminals OUT and 0tlTO. A transistor 26 responsive to the precharge signal P is connected to the transistor 26 .

Next, the operation of this S/A circuit will be explained.

First, the precharge signal P is set to 1H'' level to turn on the transistors 25 and 26. As a result, the potentials of the nodes Nl and N2 are fixed at the same level (equal potential),
In addition, the potential of the pair of output terminals OUT and surface is also at the level (
Equipotential). In other words, the S/A circuit 2 is brought into the beam set state. Next, when precharge signal P is set to "L" level, nodes N1 and N2 and output terminal OMI
T and weak are in a state where they are electrically separated from each other.

In this state, for example, data "1" is input from the corresponding cell block 1□. In other words, “H” is used as data IN.
``Level data is input with complementary data ``L'' data.

At this time, if the S/A enable signal SR is at "H" level, transistors 11.12 are turned off and transistors 19.20 are turned on. This causes transistor 17
．． The source potential of transistor 18 is lowered, and the levels of nodes Nl and N2 are applied to the gates of transistors 17 and 18, so both transistors 17 and 18 are turned on. As a result, transistors 15, 16.23
．． Although the source potential of 24 is lowered, the data (IN
Since ("H", "P") are input as , IN), only the transistors 16 and 23 are turned on. When the transistor 23 is turned on, the potential of the node N1 is lowered to the "L" level, and in response to this, The transistor 13 is turned on, and the level of the output terminal 0υT is pulled up to the "H" level. On the other hand, when the transistor 16 is turned on, the level of the inverted output end " is pulled down to the "L" level.

In other words, the output (OUT, 0UT) is “H”
).

Conversely, as input data (IN, IN”) (“L”,
When “I(”) is input, the output (OUT, 0II
T) exhibits L"lln").

In this way, when the S/A circuit is selected (when the S/A enable signal SE= is at the "H" level), the output (OUT
The logical level corresponding to the S/A person's Kadeka data (N, IN) is shown.

On the other hand, if the S/A enable signal signal S is at "L" level, transistors 11 and 12 are on, and transistor 1
9.20 is off. As a result, a pair of output terminals OUT
, OUT are both raised to the "H# level."

That is, when the S/A circuit is not selected (S/A enable (H SEt is at "L" level), its output (OU
T, 0UT) is fixed at "H" level.

2, according to the configuration of this embodiment, only one of the S/A enable signal signals S-SE becomes "H" level, and only the corresponding S/A circuit is in the active state (
(selected state), and other S/A circuits become inactive (non-selected state). As a result, the power consumption in the S/A circuit is reduced to 1/n compared to the conventional type (see FIG. 4).

Further, the S/A enable signal signals S-SE, , are sent to the S/A circuit 2. ~27 itself is used as a selection signal to selectively activate the active state, so the signal for selecting the S/A output (SL
, ~SL, ), the Nantes gates (431 to 437) for controlling the passage of the S/A output, the selection signal generation circuit (49), etc. are unnecessary. Therefore, the area occupied on the chip can be reduced by that amount, and higher integration can be promoted.

Note that in the embodiment described above, the outputs of each of the S/A circuits 2I to 2n are configured to be input to the Nant gate 3, but the present invention is not limited to this. Instead of this Nant gate 3, for example, as shown in FIG. 3, inverters 81 to 81 that respond to the outputs of the S/A circuits 21 to 2n, respectively, and a NOR gate 9 that responds to the outputs of the inverters are used. It may also be a configuration.

Furthermore, in the embodiment described above, the output of the S/A circuit when not selected is fixed at the "H" level, but this can be done by appropriately modifying the S/A circuit shown in FIG. ``It is also possible to fix the level. However, in this case, in order to match the logic of the data output from the data output buffer 4 with the S/A input card data logic, a NOR gate is used instead of the Nant gate 3, and depending on the circuit configuration, the output of the S/A circuit is It is necessary to use the data at the inverted output terminal].

〔Effect of the invention〕

As explained above, according to the present invention, for example, if the number of S/A circuits is n, the number of S/A circuits that become active when reading data is 1/n, and the overall S/A circuit The power consumption can be reduced to 1/n compared to the conventional type. In addition, the S
Since a signal line for /A output selection is not required, the wiring area occupied on the chip can be relatively reduced.

This contributes to high integration and is extremely useful.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a semiconductor memory device as an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the S/A circuit in FIG. 1, and FIG. FIG. 1 is a diagram showing the configuration of the main parts of a modification of the embodiment. FIG. 4 is a diagram showing the overall configuration of a semiconductor memory device as an example of the conventional type. FIG. 5 is a diagram showing the S/A circuit in FIG. 4. This is a circuit diagram showing the configuration of . (Explanation of symbols) 1...Memory cell array, 1+ to 17...Cell block, 2, to 2n...-Sense amplifier (S/A) 7...S/
A selection circuit, AS...address status (signal), SE, -3E,...S/A enable signal. circuit,

Claims (1)

[Scope of Claims] A semiconductor memory device comprising a sense amplifier circuit (2_1 to 2_n) for each cell block of a memory cell array (1) divided into a plurality of cell blocks (1_1 to 1_n), It is equipped with a selection circuit (7) that selects only one of the sense amplifier circuits based on the address information (AS) and makes it active, and the sense amplifier circuits that are made non-selected by the selection circuit have a fixed logic level. A semiconductor memory device characterized in that it outputs data.