JPH02238750A - Error signal selection system for eight-phase psk demodulator - Google Patents

Abstract

PURPOSE:To improve the quality of the entire demodulation by operating various control circuits of an octal phase PSK demodulator only when a normal error signal is identified and a normal error signal is obtained. CONSTITUTION:When two internal points of a channel are identified, it signifies that accurate error information exists, and when the two internal points are discriminated, a selection signal SEL representing the enable state is outputted from a selection circuit 4. When the selection signal SEL is in enable state, various circuits of the octal phase PSK demodulator uses error information to be valid. The various control circuits in the demodulator are not operated when normal error information is not obtained and operated when the error information is normal. Thus, the operation of the various control circuits in the demodulator is accurately implemented with simple circuit constitution and the performance of the entire demodulator is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding an 8-phase PSK demodulator, directional dependence of signal identification based on the fact that 8-phase PSK signal points are arranged non-squarely on the Q channel plane for one channel. Therefore, various circuits in the demodulator that utilize the error signal are used to eliminate control errors caused by the inability of the identification circuit to accurately detect the error signal, and to use the error signal only when the error signal is valid. The basic form of the circuit is to calculate two orthogonal I and Q channel signals, two other channel signals orthogonal to these two channels, and a circuit that calculates the signals of these four channels. an identification circuit that identifies the
a 4/3 conversion circuit that converts each of the four identified signals into a binary 3-bit parallel signal representing 8-phase PSK;
8-phase PS from 3-bit parallel signal from 4/3 conversion circuit
and a selection circuit that outputs a selection signal in an enabled state indicating that signals at two points inside the K signal point arrangement are present, and the selection signal is configured to be used for controlling the use of the error signal.

[Industrial application field]

The present invention is an 8-phase PSK system in a digital multiplex radio system.
It relates to a demodulator, and in particular, it solves the problem that accurate detection of identification error signals is not possible due to the fact that 8-phase PSK signal points are arranged non-square on the I channel and Q channel planes. , only when a valid error signal is detected and a valid error signal exists, the error signal is used to control various circuits in the demodulator, carrier regeneration circuit, automatic drift control circuit of the identification circuit, and automatic control of the variable amplifier circuit. The present invention relates to an error signal selection method for an 8-phase PSK demodulator that improves the performance of a gain control circuit, an equalizer control signal generation circuit, etc.

FIG. 21 shows a configuration diagram of an 8-phase PSK demodulator to which the present invention is applicable. In the figure, the received signal is hybrid 1
00, it is separated into orthogonal I channel data and Q channel data. ■Channel data and Q channel data are converted to intermediate frequency (I) by frequency converters 111 and 121, respectively.
F).

A local oscillation signal for conversion into IF is provided from a VCO 127 as a local oscillator. IF's! Channel data and Q channel data are filtered through filters 112 and 1, respectively.
22 and variable amplification circuit 113. 123 and is amplified (or attenuated) at a predetermined amplification factor (attenuation factor). Thereafter, equalizer 114. 124. These (1) channel data are applied to discriminators 117 and 120 each comprising an AD converter, and signal information and error information are discriminated. In addition, ■ Channel data and Q
Channel data is an addition circuit 115 and a subtraction circuit 116.
As a result, (1+Q) channel axis data and (1-Q) channel axis data that are orthogonal to the channel axis and Q channel axis, respectively, are created, and the discriminators 118 and 119 extract signal information and error information from these data as well. is identified. The identification results of these discriminators 117 to 120 are applied to the logic processing circuit 125, and the binary number 3 representing 8-phase PSK is applied to the logic processing circuit 125.
Bit signals A, B. Converted to C. Further, a carrier wave regeneration circuit 126 regenerates the carrier wave based on the result from the logic processing circuit 125. The reproduced carrier wave is applied as a control voltage signal to the VCO 127. In the demodulator shown in FIG. 21, based on the discrimination error signals from the discrimination circuits 117 to 120, carrier wave recovery in the carrier wave recovery circuit, gain control of the variable amplifier circuit, control signal generation of the equalizer, and discriminator 117 are performed.
-120 drift control etc. are performed.

[Prior Art] FIG. 22 shows a circuit diagram of a conventional carrier wave regeneration circuit. ■ Signal information D0 error information D from AD converters 117 and 120 as discriminators provided in the channel and Q channel
2 is EXOR circuit (exclusive logic circuit) 125a, 126
b, and the results are applied to the operational amplifier 12 for difference calculation.
6a and further applied to the loop filter 126b. BXOR circuit 125a, 126b
constitutes the logic processing circuit 125. Further, the difference calculation amplifier 126a and the loop filter 126b constitute a carrier wave regeneration circuit 126.

EXOR circuits 125a and 126b receive signal information D
0, a 1-bit correlation with the error information D2 is taken, and based on the correlation, the carrier wave regeneration circuit 126 regenerates the carrier wave, and the VC
Apply to O127.

FIG. 23 shows a circuit diagram of a conventional automatic drift control circuit. The automatic drift control circuit consists of an integrating circuit 301 and an inverter 302. Error information D of AD converter 117
2 is integrated by the integrating circuit 301, and an inverter 302 inverts the polarity of the signal from the integrating circuit 301 in order to invert the signal and apply it to the AD converter 117. A DC cut filter 303 is provided before the AD converter 117 so that only the DC signal from the automatic drift control circuit 300 is applied to the AD converter 117.

FIG. 24 shows a conventional equalizer circuit. The equalizers are tap delay circuits 401 to 402, only two of which are shown for simplicity.
, a transversal filter consisting of coefficient multiplication circuits 411 to 413, and an addition circuit 421, and an AD as an identification circuit.
Converter 431, error calculation circuit 441, identification signal Dk
Binarization circuits 451 and 45 that binarize the % error signal Em
2. Consists of a control circuit consisting of delay circuits 461, 462, multiplication circuits for calculating correlation (specifically, EXOR circuits for calculating 1-bit correlation) 471 to 473, and integration circuits 481 to 483. .

The control circuit updates the coefficients C-1I C+1IC+1 of the coefficient multiplier by calculating the correlation between the identification signal and the error signal, more specifically, by performing a 1-bit exclusive OR (EXOR) on each signal.

[Problem to be solved by the invention]

Multilevel QAM, for example, 1 as shown in FIG. 25(a)
6 In the case of 0AH, the signal point arrangement is equally spaced on the I channel and Q channel planes, so even when viewed from either direction of the I or Q channel or identified by the identification circuit, the signal points are as shown in Figure 25 (b). signal information I) o. D+ and the error information D2 are accurately expressed as 1/2 to the power, and the error information can be accurately identified.

However, as shown in Figure 26(a), the signal point arrangement of 8-phase PSK is spaced at 45° intervals, so when viewed from the 1st and Q channels, the spacing is 1.1/(T, and the signal The information D0 and the error bit D1 do not have a relationship of 1/2 to the power of 2. Therefore, even if they are identified by a discriminator, as shown in FIG. 26(b)
As shown in , the direction of the error information D1 following the signal information D0 cannot be detected accurately depending on the position of the signal point, whether the error is positive or negative, whether viewed from the I channel or the Q channel. or accurately detected. The problem is that it can't be done.

Therefore, using such an error signal, FIGS.
If we were to operate the carrier wave regeneration circuit, automatic drift control circuit, equalizer, and automatic gain control circuit (not shown) shown in Figure 24, we would encounter the problem of not being able to obtain accurate operational results. There is.

The present invention solves the above problems, accurately operates circuits in the demodulator such as the carrier regeneration circuit, automatic drift control circuit, equalizer, automatic gain control circuit, etc., and further improves the overall 8-phase PSK demodulator. The purpose is to operate with high performance and improve the quality of the reproduced signal. [Means for solving the problem] In the following explanation, the 8-phase P
The overall configuration of the SK demodulator is assumed.

FIG. 1 shows a basic block diagram of the error signal selection method of the 8-phase PSK demodulator of the present invention.

In the same figure, the orthogonal . Q2 channel signal I. A circuit 1 that calculates Q and signals (1+Q) and (1-Q) of other two channels orthogonal to these two channels, and an identification circuit 2 that identifies these four channel signals, respectively. A 4/3 conversion circuit 3 that converts the 4-channel signal AD-DD into a 3-pit parallel signal C}l 1-C}13 representing the 8-phase PSK in binary, and 3 bits from the 4-3 conversion circuit. and a selection circuit 4 that outputs a selection signal SEL in an enabled state indicating that two points inside the 8-phase PSK signal point arrangement exist from the parallel signals of 8-phase PSK, characterized in that it is used for control in
A demodulator error signal selection scheme is provided.

Further, the present invention provides a carrier wave recovery circuit for an eight-phase PSK demodulator, characterized in that the selection signal SEL is used as an input signal of the carrier wave recovery circuit 5 of the demodulator, as shown in FIG. Ru.

Furthermore, in the present invention, as shown in FIG. 3, a latch circuit 61 holds the identification error information E from the identification circuits 21 to 24 (representatively 20) and applies its output to the input of the identification circuit. and an AND which inputs a clock CLK and the selection signal SEL used as gate control of the clock, and outputs a signal for latch operation of the latch circuit 61.
circuit 62, and compensates for the drift of the identification circuit 20 by the output from the latch circuit.
An automatic drift control circuit for a K demodulator is provided.

According to the present invention, as shown in FIG. 4, there is also an interphase circuit 7l that correlates the identification signal information D from the identification circuit 20 with the identification error information E, and a latch that holds the output of the interphase circuit. The latch circuit 72 includes a circuit 72 and an AND circuit 73 that provides a latch operation signal for the latch circuit, into which a clock CLK and the selection signal SEL for gate control of the clock are input. The output is 8-phase P
Variable amplifier circuit 113 provided in the ■ channel and Q channel of the SK demodulator. There is provided an automatic gain control circuit for a variable amplifier circuit of an 8-phase PSK demodulator, which is characterized in that it is used as a gain control signal of 123 (FIG. 21). According to the present invention, as shown in FIG.
, Identification circuit 21.24 (
1) from the respective identification signal information and identification error information signal AD. and A.D. , and DD. and D
D. and based on the selection signal SEL, channel identification data and error data ID, It, Q
Channel identification data and error data Q. ,Q. The circuit 8 generates identification data and error data for controlling the I channel equalizer 114 (FIG. 21), and the Q channel equalizer 124 (FIG. 21). The identification data and error data for control of the 8-phase PS
An equalizer control signal generation circuit is provided which is characterized in that it is used as a correlation control signal for equalizers 114 and 124 provided in the I channel and Q channel of the K demodulator.

[For production]

Figures 6 and 7 show the signal point arrangement diagrams of the 8-phase PSK of the present invention.
As shown in the figure. Eight signals a, b, c. d, e, r, g. h are arranged at intervals of 45 degrees. And each 8-phase PSK
is expressed by the 3-bit binary number shown in the figure.

The identification circuit 2l in FIG. 1 has signal points a, d, centering on the I channel. Identify e and h. The identification circuit 24 identifies signal points b, c, and fg centered on the Q channel. Furthermore, the addition circuit 11 creates (I+Q) channel data, the subtraction circuit 12 creates (1-Q) channel data, and the discriminating circuit 22 creates signal points b, a, e, f, la, and the separate circuit 23 creates signal points c. d
, g, h. (1+Q) channels and (1 −
The Q) channel is orthogonal to the ■ channel and the Q channel, respectively. In Figure 6, each signal point is ``'1'' when viewed from the channel axis (for left (L) rotation), and ``0'' when located below (for right (R) rotation). be identified. The opposite is true when viewed from the Q channel axis.

In this way, identifying signal points from the 4-channel axial direction is important because, as described with reference to FIG. This is because the placement cannot be identified and an accurate error signal cannot be obtained.
) channel and (1-Q) channel, signal points are also identified. That is, as shown in Fig. 7, when viewed from each axis, each axis has 1 as identification signal information.
bit, and only one bit is taken as identification error information.

If we focus on only two points inside such a signal point,
Signal points are expressed as 1 to the power of 2. In other words, when a certain signal point is viewed from a corresponding channel, accurate error information can be returned.

Identification information AA-DD from identification circuits 21 to 24 is 4.3
The signal is applied to the conversion circuit 3 and converted into 3-bit binary parallel data CI11 to CH3 representing 8-phase PSK.

The truth table for this conversion is shown in FIG. For example, the signal point f is below all channel axes (clockwise rotation side), and the input AD-DD signal to the 4/3 conversion circuit 3 is
0000″, and the playback output cH1~CI1 3 =
Converted to 000.

The outputs CHI to CH3 from the 4/3 conversion circuit 3 are applied to the selection circuit 4, and it is determined whether or not they indicate two internal points of the 8-phase PSK signal points. As shown in FIG. 7, if two points inside a certain channel are identified, accurate error information is indicated. When two internal points are determined, a selection signal SEL indicating an enable state is output from the selection circuit 4.

When this selection signal SEL is enabled, the 8-phase PS
Various circuits of the K demodulator can effectively use error information. If the selection signal SEL is not enabled, the error signal is not used. By doing this, the various control circuits in the demodulator will not operate unless normal error information is obtained; in other words, they will operate normally only when the error information is normal. .

The carrier wave regeneration circuit shown in FIG. 2 inputs the selection signal SEL as it is and passes it through the loop filter 5 to regenerate the carrier wave. The reproduced carrier wave is the VCO 12 in Fig. 21.
7.

The automatic drift control circuit 6 in FIG. 3 uses the selection signal SE
L is used to inhibit the clock CLK for operating the latch circuit 61. That is, the selection signal SEL
Only in the enabled state, the clock CLK is output to the latch operation of the latch circuit 61, and the identification error information E from the identification circuit 20 is latched by the latch circuit 61. The output of this latch circuit 6l is input to the identification circuit 20 and used for drift compensation of the identification circuit 20. Also in the automatic gain control circuit 7 of FIG. 4, the selection signal SEL is used to inhibit the latch operation clock CLK of the latch circuit 72. In the automatic gain control circuit 7, the identification signal information D and the identification error information E of the identification circuit 20 are
If the correlation with the interphase circuit 71 is 1 bit each, and the identification signal information D and the identification error information E are 1 bit, EXOR is used as shown in the figure.
After being captured by the circuit, it is held in the latch circuit 72. The output of the latch circuit 72 is used to control the gains of the variable amplifier circuits 113 and 123 provided for the I channel and Q channel.

The control signal generation circuit 8 of the equalizer in FIG.
Identification signal information (identification data) from AD. and identification error information (error data) AD, ■ identification signal IO for calculating correlation in channel equalizer control circuit
and an error signal I. In this case as well, a selection signal SEL is used to identify valid data. If the selection signal SEL is not enabled, the control identification signal and error signal are not used.

FIGS. 9(a) to (d) show signal point arrangement diagrams in this case, and FIG. 10 shows the relationship between the outputs of the identification circuits 21 to 24 and the reproduced signal, and the identification circuit that outputs effective control information. 21
．． A truth table showing 24 relationships is shown below.

In this case, the binary representations of signal points a' to h' are shown differently from those shown in FIGS. 6 and 7. As is clear from FIG. 10, the CH of the reproduced signal CH l -CI1 3
When CH3 is "0", this indicates that the error information from the ■channel identification circuit 21 is valid, and when CH3 is "1", the error information from the Q channel identification circuit 24 is valid.As stated above,
By using the selection signal that indicates two points inside the signal point, that is, the selection signal SEL that indicates that the error signal is valid, the operation of various circuits in the 8-phase PSK demodulator can be accurately performed with a simple circuit configuration. can be made to do so.

〔Example〕

FIG. 11 shows a circuit diagram of an embodiment of the 4/3 conversion circuit 3 shown in FIG. The 4/3 conversion circuit 3 is shown in FIG. 8, and the contents of the truth table in FIG. 8 are expressed by the following algorithm.

CHI = BD...(1
．． 1) CH2 = BD ■ CD
...(1.2)CH3= ・ ・
・DD +AD・Ding ■・CD − DD +AD−BD−CD−DD +τ Ding・BD−τ Ding・DD = (AD■CD). (B D■DD)...(1
．． 3) However, AD indicates the discrimination output of the discrimination circuit 21, BD indicates the discrimination output of the discrimination circuit 22, CD indicates the discrimination output of the discrimination circuit 23, and DD indicates the discrimination output of the discrimination circuit 24.

In the above formula, ■ is exclusive logic (EχOR), and is AN
Shows D logic.

Therefore, 4 in Fig. 11, which realizes the above algorithm,
・The three conversion circuits 3 are EXOR circuit 3l, EXOR circuit 3
2. It is composed of an AND circuit 33. FIG. 12 shows a circuit diagram of an embodiment of the selection circuit 4 of the present invention. This selection circuit 4
are two points inside the signal point arrangement, and when they are two points inside, the enable (“1”) selection signal S
Outputs EL. Before describing the configuration of this circuit, select circuit 4
We will explain the principle of This will be explained with reference to Figure 7. The identification circuit 21 selects signal point a. d
, e. Look at the rotation of h. Also, the identification circuit 24 selects the signal point b.
,c. f. Look at the rotation of H. As mentioned above, the ■ channel identification circuit 21 represents left rotation as "0" and right rotation as "1", and the Q channel identification circuit 24 represents left rotation as "1" and right rotation as "1". Since it is expressed as 0'', the identification circuit 21 outputs ADo as signal information and AD as error information.
+, DD. from the identification circuit 24 as signal information. , DD as error information. is output, the rotation of the signal is expressed by the algorithm below.

Signal point a. d, e. Rotation of f: DD. ■ADl...(2.1) Signal point b. Rotation of c, f, g: AD. ■DD, ・ (2.2) Therefore, in order to match the direction of rotation, select the following signal.

DD for signal points a, d, e, f. ■AD+...(3.1)
Signal point b. c. For f and g,

Selection of these signals can be performed by output CH2.

That is, from the bit representation in FIG. 6, if CH2 is "0", the signal points a, d. e. f, and when CH2 is "1", the signal point b+C. It shows flg.

In the circuit of Fig. 12, the above equations (3.1) and (3.2) are
Only the selection circuit section obtained by the χOR circuit (not shown) is shown. The selection circuit section 4 includes AND circuits 41 .
42, an inharter 43, and an EXOR circuit 44. The EXOR circuit 44 outputs a high enable (“1”) selection signal SEL. This selection signal SEL is applied to various control circuits in the demodulator, which will be described later, and is used for various controls. That is, the various control circuits use the error information as valid only when the selection signal SEL is high enable.

Note that AD converters are generally used as the identification circuits 21 to 24. In this case, AD converter 21~
24 may each be a 2-bit AD converter.

FIG. 13 shows a circuit diagram of a carrier regeneration circuit according to an embodiment of the present invention.

The identification circuits 21 to 24 in FIG. 1 are provided with 2-bit AD converters 211 to 241, respectively, and convert channel data, (1+Q) channel data, (1-Q) channel data, and Q channel data into 2-bit data, respectively. Identification data ADO. ADI~DD. ．． D.D. Output. Upper identification data ADo, BDo, CDo. DD6 indicates identification signal data, and lower identification data AD+. BD
+, CD+. DD+ indicates identification error data.

The EXOR circuit 91 realizes the algorithm of the above equation (3.1), and the EXOR circuit 92 realizes the algorithm of the above equation (3.2).

The 4/3 conversion circuit 3 is the same as shown in Fig. 11. Selection circuit 4
is also the same as Fig. 12.

The selection output SEL of the selection circuit 4 is directly connected to the resistors 51 and 52.
and a loop filter 5 consisting of a capacitor 53. Loop filter 5 filters the enable selection signal SEL and outputs the output to VCOt2.
'7 (Figure 21).

In this way, by directly using the selection signal SEL,
An error-free carrier wave regeneration circuit can be realized with a simple configuration.

FIG. 14 shows a circuit diagram of a general automatic drift control circuit according to an embodiment of the present invention. In the same figure, for the path of the DC cut filter 212 and the AD converter 211,
Flip-flop 61, integration circuit 63, inverter 64
, and an automatic drift control circuit consisting of an A N D circuit 62.

The selection signal SEL is applied to the AND circuit 62, and only when the selection signal SEL is enabled, the clock CLK is applied to the clock terminal of the D flip-flop 61, and the error information D of the AD converter 211 is held in the D flip-flop 63. That's what I do. The integrating circuit 63 integrates the output of the D flip-flop 6l. The signal of this integrated output is inverted by the inverter 64, and the signal is inverted by the AD converter 211.
is applied to compensate for the drift of the AD converter 211. The reason why the D flip-flop 6l is used as a holding circuit is because the error information D1 is 1 bit, either O or 1.

FIG. 15 shows an overall configuration diagram of an automatic drift control circuit according to an embodiment of the present invention.

(2) Channels are the same as in FIG. 14.

Q channel is! Since the polarity is inverted from that of the channel, the clock CLK is gate-controlled by the selection signal r inverted by the inverter 35 provided in the 4/3 conversion circuit 3'. Regarding the (I+Q) channel and the (I-Q) channel, the EXOR circuit 34 provided in the 4/3 conversion circuit 3' generates selection signals SELA and SELA based on the outputs CH2 and CI13, taking into account the phase difference. is output. It has a reverse phase relationship with the selection signals SEL^ and SELA. Therefore, the EXOR circuit 34 has an inverted output terminal and outputs a selection signal. In this way, an automatic drift control circuit that operates normally can be realized with a simple circuit configuration. FIG. 16 shows an automatic gain control circuit according to an embodiment of the present invention.

Since the variable amplifier circuits 113 and 123 are provided only for the ■channel and the Q channel, as shown in FIG.
Automatic gain control circuits are also provided for the ■ channel and the Q channel. The 4/3 conversion circuit 3 is similar to that shown in FIG. However, the selection signal for Q channel −m
- is used by inverting the signal via the inverter 34. (2) Regarding the channel automatic gain control circuit, the signal information AD. of the AD converter 211. and the error information A D + are correlated by 1 bit in an EXOR circuit 71. Then, the correlation result of the EXOR circuit 71 applied to the D flip-flop 72 is held in the D flip-flop 72, but in this holding, the clock C
LK is gated by the selection signal SEL, and the D flip-flop 7 is activated only when the selection signal SEL is enabled.
It is held at 2. The holding result is integrated by an integrating circuit 74 and then passed through an inverter 75 to control the gain of the variable amplifier circuit 113.The EXOR circuit 7l correlates the magnitude of the gain fluctuation of the variable amplifier circuit 113 with its movement. This is to determine the direction. The same applies to the Q channel.

In this way, an automatic gain control circuit that operates normally can be realized with a simple circuit configuration.

FIG. 17 shows a circuit diagram of the equalizer control signal generation circuit 8 according to the embodiment of the present invention.

In the same figure, among the identification signals from AD converters 211 to 241, upper signal information ADo to DDo is applied to a 4/3 conversion circuit 3''', and 3-bit binary reproduction signals CHI to CH3 are output. . This conversion logic is based on FIG. Therefore, the 4/3 conversion circuit 3''' is the 11th
It consists of the circuit shown in the figure. In this case, as shown in FIG. 10, the output CH2 indicates whether one channel or the Q channel is valid.

AD converter 211. Identification signal from AD.241, that is, signal information and error information: AD. and A.D. , and DD. and D D + are output to the control signal generation circuit 8. From these identification signals, the control signal generation circuit 8
Only when the selection signal SEL is valid, the equalizer 114,
124 (Fig. 21) coefficients t, . ．． C. ,C. control signals for determination, i.e. identification signals I, each of 1 bit;
and Q, and error signals I, and Q, are output.

Therefore, the control signal generation circuit 8 has a first control signal generation circuit consisting of an AND circuit 81a, an OR circuit 8lb, and a J-K7 lip 7o7b 81c, which outputs identification signal information I for the equalizer 114. AND circuit 82a and OR circuit 82b, which output identification error information I for the circuit and equalizer 114.
, a second control signal generation circuit consisting of a J-K flip-flop 82c, and a third control signal generation circuit consisting of an AND circuit 83a, an OR circuit 83b, and a J-K flip 707183c, which outputs identification signal information Q for the equalizer 124. control signal generation circuit,
AND outputs identification error information QE for the equalizer 124
Circuit 84a, OR circuit 84b, JK7'J7
A fourth control signal generation circuit consisting of “7ro7” 84c,
Since the Q channel is orthogonal to the (2) channel, the inverter 85 inverts the polarity of the selection signal SEL.

A diagram showing the operation of JK flip-flops 81c to 84c is shown in the 18th summary. Further, FIG. 19 shows an operation timing diagram of the control signal generation circuit 8.

As shown in FIG. 19, for example, the AD converter 21
A case will be described in which the identification signal information I0 of the control signal of the equalizer 114 is calculated from the identification information A Do of No. 1. When the selection signal SEL is at low level, the identification information AD. is at a low level, the output X of the AND circuit 81a is at a low level. In this case, the output y of the OR circuit 8lb also becomes low level. Therefore, as is clear from FIG. 18, the Q output of the JK flip-flop 81c is "0".
It becomes ゛゜. In other words, ■. =0.

When the selection signal SEL is at low level, the identification information AD. is at a high level, the output X of the AND circuit 81a is at a high level. In this case, the output y of the OR circuit 8lb is at a high level. Therefore, as is clear from FIG. 18, the Q output of the JK flip-flop 81c is "1".
It becomes ゛. That is, Io=1.

When the selection signal SEL is at high level, the identification information AD. Regardless of the signal level of the AND circuit 81a, the output X of the AND circuit 81a is at a low level. In this case, the output y of the OR circuit 8lb becomes high level. Therefore, the Q output of the JK flip-flop 81c maintains its previous state, as is clear from FIG.

As described above, the selection signal SEL is used to generate an effective equalizer control identification signal (2). is obtained.

Other equalizer control identification signals It, QD, Qi
The same applies to

The identification information In, It calculated in this way is the second
The coefficients C-r to C.0 of the transversal filter section of the equalizer 114 shown in FIG. , Correlation calculation for calculation, more specifically, identification information■. ．． (2) is 1 bit each, so in the correlation calculation circuits 471 to 473, which are composed of EXOR circuits and which calculate 1-bit correlation, EXOR
Used for calculations.

In this case, identification information ■ that does not contain any errors. The coefficient C-1 to 0.1 of the transversal filter section is determined by +If.
is updated successfully.

As described above, since the various control circuits within the 8-phase PSK demodulator operate normally, the entire demodulator also operates normally. As a result, the quality of the reproduced signal from the demodulator is significantly improved.

〔Effect of the invention〕

As described above, according to the present invention, a normal error signal can be identified with a simple circuit configuration, and only when a normal error signal is obtained, various control circuits of the 8-phase PSK demodulator are activated. Since the demodulator is operated, the demodulator as a whole can output a reproduced signal with improved quality.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the error signal selection method of the 8-phase PSK demodulator of the present invention. Figure 2 is a block diagram of the principle of the carrier recovery circuit of the present invention. Figure 3 is the principle of the automatic drift control circuit of the present invention. Block diagram: Figure 4 is a principle block diagram of the automatic gain control circuit of the present invention; Figure 5 is a principle block diagram of the equalizer control signal generation circuit of the present invention; Figure 6 is the 8-phase PSK in Figure 1. Fig. 7 is a diagram showing the identification operation of the identification circuit in Fig. 1 for the signal point arrangement in Fig. 6, Fig. 8 is a diagram showing the truth of the conversion of the 4/3 conversion circuit in Fig. 1. Figures 9(a) to (d) are diagrams showing the signal point arrangement of the 8-phase PSK in Figure 5, Figure 10 is the relationship between the output of the identification circuit and the reproduced signal in Figure 5, 11 is a circuit diagram of a 4/3 conversion circuit according to an embodiment of the present invention; FIG. 12 is a circuit diagram of a selection circuit according to an embodiment of the present invention; FIG.
14 is a general circuit diagram of an automatic drift control circuit according to an embodiment of the present invention. FIG. 15 is a circuit diagram of an automatic drift control circuit according to an embodiment of the present invention. 16 is a circuit diagram of an automatic gain control circuit according to an example of the present invention. FIG. 17 is a circuit diagram of a control signal generation circuit of an equalizer according to an embodiment of the present invention. A diagram showing the operation of the J-K flip-flop, Figure 19 is an operation timing diagram of the equalizer control signal generation circuit of Figure 17, and Figure 20 is a diagram showing the operation timing of the equalizer control signal generation circuit of Figure 17. 21 is a block diagram of an 8-phase PSK demodulator to which the present invention is applied, FIG. 22 is a conventional carrier wave regeneration circuit diagram, and FIG. 23 is a conventional automatic Drift control circuit diagram, Fig. 24 is a circuit diagram of a conventional equalizer, Fig. 25 (a), (b) is a diagram showing the signal point arrangement of 16 1 AM and its identification, Fig. 26 (a), (b) is a diagram showing the signal point arrangement of 8-phase PSK and its conventional identification. (Explanation of symbols) ■...Sub-axis data calculation circuit 1, 2...Identification circuit, 3...4/3 conversion circuit,
4... Selection circuit, 5... Carrier regeneration circuit, 6... Automatic drift control circuit, 7... Automatic gain control circuit, 8... Equalizer control signal generation circuit, 11... Addition circuits 11, 12...subtraction circuit l2
, 21-24...Identification circuit.

Claims (1)

[Claims] In a 1- and 8-phase PSK demodulator, two orthogonal I and Q channel signals (I, Q) and two other channel signals (I, Q) orthogonal to these two channels are used.
+Q, I-Q), an identification circuit (2) that identifies these 4 channel signals, and converts the 8-phase PSK into binary numbers from the identified 4 channel signals (AD to DD). 3-bit parallel signal (CH1
~CH3), and 8-phase P from the 3-bit parallel signal from the 4-3 conversion circuit.
It has a selection circuit (4) that outputs a selection signal (SEL) in an enabled state indicating the presence of signals at two points inside the signal point arrangement of SK, and the selection signal is used to control the use of the error signal. An error signal selection method for an 8-phase PSK demodulator, characterized in that it is used. 2. The selection signal is transmitted to the carrier regeneration circuit (5) of the demodulator.
2. The carrier wave recovery circuit for an 8-phase PSK demodulator according to claim 1, which is used as an input signal for the 8-phase PSK demodulator. 3. Holding identification error information (E) from the identification circuit;
A latch circuit that applies its output to the input of the identification circuit (
61), and an AND circuit (62) that inputs a clock (CLK) and the selection signal (SEL) used as gate control of the clock and outputs a signal for latch operation of the latch circuit. The automatic drift control circuit for an 8-phase PSK demodulator as claimed in claim 1, wherein the drift of the discriminator circuit is compensated by the output of the circuit. 4. A correlation circuit (71) that correlates the identification signal information (D) from the identification circuit with the identification error information (E), a latch circuit (72) that holds the output of the interphase circuit, and the latch circuit. A provides a clock signal for latch operation of
An ND circuit (73), into which a clock (CLK) and the selection signal (SEL) for gate control of the clock are input, and the output of the latch circuit (73) is an 8-phase PSK circuit. Automatic gain control of a variable amplifier circuit of an 8-phase PSK demodulator according to claim 1, characterized in that it is used as a gain control signal of a variable amplifier circuit (113, 123) provided in an I channel and a Q channel of a demodulator. circuit. 5. Input the identification signal of the identification circuit (21, 24) that identifies the orthogonal I and Q2 channel signals, and generate identification data for controlling the I channel equalizer based on the selection signal (SEL). and a circuit that generates error data, identification data for controlling the Q channel equalizer, and error data (
8), and when the selection signal (SEL) is in an enabled state,
The identification data and error data of the I channel and the identification data and error data of the Q channel are transmitted to the 8-phase PSK.
2. The equalizer control signal generating circuit according to claim 1, wherein the equalizer control signal generating circuit is used as a correlation control signal for an equalizer provided in an I channel and a Q channel of a demodulator.