JPH0223454A - Bus using right control system - Google Patents

Abstract

PURPOSE:To evade the continuance of processing wait even for a requiring source at low priority, and to effectively process a bus occupying request by using a shift circuit and advancing the priority of the bus occupying request according to the number of times of bus occupying permission. CONSTITUTION:When bus occupying request signals DRQa to DRQc are simultaneously generated from processors 1 to 3, and the priority is given to the request of the processor 1, a request wait condition continues for the processor 3. There, a shift circuit 5 generates a signal DRQc' by four shift clocks and DRQc'' by eight shift clocks by means of a clock generating circuit 11. When the signal DRQc'' is outputted, the priority higher than the signal DRQb is decided by a secondary priority deciding circuit 6, and the request is received after the signal DRQa. Thus, even for the request source at the low priority, when the wait condition continues for a prescribed time, it is made into the condition to have the almost highest priority, the continuance of the processing wait time is avoided, and the bus occupying request can be effectively processed.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a bus right control system, and more particularly to a bus right control system that efficiently processes all requests when there are conflicts of bus occupancy requests.

Prior Art Conventionally, as an example of a bus usage right control method, priorities are assigned in advance to all requesting processors, and when multiple bus occupancy requests occur in conflict, they are assigned priority within a certain period of time. A common method is to judge existing requests according to their priorities, and to grant bus occupancy permission to the request with the highest priority.

In addition to this method in which the priority order is fixed, there is also a method in which the priority order is semi-fixed and processing is executed by rotating the priority order.

In the conventional bus right to use control system described above, since the priority order is fixed, a request source with a low priority takes a considerable amount of time to acquire the right to use the bus. Furthermore, since the right to use the bus is given to the request source with the highest priority within each time period, if at least one request from a request source with a higher priority than any other request source is issued within each time period, the former The drawback is that the processing of the request is delayed forever during this time. Therefore, if a method is adopted in which the priority order is rotated in order to avoid such a drawback, there is a problem that there is no actual priority order.

21J and l An object of the present invention is to gradually increase the priority of bus occupancy requests even for request sources with low priority, so that if the request source continues to wait for a request, the priority level of the request source becomes close to the top priority. To provide a bus use right control system which can efficiently process bus occupancy requests by avoiding continuous waiting for processing.

11. The bus right to use control system according to the present invention has a plurality of shift systems that input bus occupancy request signals from a plurality of request sources whose priorities are determined in advance and shift these signals, respectively, in response to a shift clock. A bus occupancy request signal from the request source and a shift output signal of each of the shift circuits are provided corresponding to a plurality of groups obtained by dividing the bus occupancy request signal from the request source and the shift output signal of each of the shift circuits according to a predetermined rule. A plurality of circuits that generate a group request signal in response to a group request signal, each determine the highest priority request signal according to a predetermined priority order within the corresponding group, and each output a highest priority bus occupancy permission signal. a secondary priority determination circuit; and a primary determination circuit that determines the group request signal for each group outputted from each secondary priority determination circuit according to a predetermined priority order and generates a permission signal for each group. a priority determination circuit; and a clock generation circuit that generates the shift clock in response to the generation of the permission signal in units of groups, and in response to the generation of the permission signal in units of groups, the two clocks correspond to the corresponding group. The present invention is characterized in that the bus occupancy permission signal is sent to the request source of the highest priority bus occupancy request signal to the next priority order determining circuit.

Embodiments Below, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention.

It is assumed that processors 1 to 3 are requesters requesting the right to use the bus, and the priorities are determined in advance in order of priority. Each of the processors 1 to 3 outputs bus occupancy request signals DRQa and DRQbDRQc, respectively, but the outputs DRQb and DRQb of processors other than the highest priority processor 1 are
DRQc is input to corresponding shift circuits 4.5.

Signal DRQa and first stage output DIIQ of shift circuit 4
b' and the output DRQC'' of the second stage of the shift circuit 50 are set to 1.
one group, called group a, and 0RQa
, DRQb", DRQc", and the secondary priority determination circuit 6 judges these three manual operations according to the priority order.

The bus occupancy request signal DRQb and the first stage output DRQc' of the shift circuit 5 are called group b, and DRQb,
Priorities are set in the order of ``DI'tQC'', and the secondary priority determination circuit 8 determines whether these two people will be able to power according to this priority order.The bus occupancy request signal DRQc is placed in group C by itself and is used for secondary priority determination. It is input to circuit 8.

Group request signals RQO, RQl, and RQ2, which are OR outputs of the signals of groups a, b, and c, are generated from the corresponding secondary priority determination circuits 6, 7.8, respectively, and these group request signals @RQO, RQl, I' (Q2 is the three-man power of the primary priority determination circuit 9. In this -order priority determination circuit 9, the group request signals RQO, RQl, RQ2 for each group a, b, c are divided into groups a, b, The determination is made according to the priority order set in ascending order of c.

Based on this determination result, the requested MRQO of group a is @
If it is a priority, 0 is generated in the corresponding group a permission signal expression, which is returned to the secondary priority determination circuit 6 of group a, and is also input to the clock generation circuit 10.11. Similarly, request signals RQ1 of groups b and c,
If RQ2 is determined to be the destination of RIa, corresponding group permission signals AKI and AK2 are generated, respectively, and group b
, c to the secondary priority determination circuit 7.8, and
It is input to clock generation circuit 10.11.

When the a-group permission signal AKO is returned, the secondary priority determination circuit 6 issues bus occupancy permission signals DAKa, DAKb', D8 to C'' according to the priority in group a.
to the corresponding requestor. When 1 is returned to the group b permission signal, the secondary priority determination circuit 7 outputs a bus occupancy permission signal DA according to the priority in group b.
Either Kb or DAKc' is returned to the corresponding request source. In addition, when the C group permission signal AK2 is returned, the secondary priority order determination circuit 8 operates according to the priority order in group C (in this example, since group C is only a single manual DRQC, this input DRQc always has the highest priority). ) The processor 3, which is the requesting source, receives the bus occupancy permission signal DAKc.
Return to. Note that 12.13 is an OR gate for returning these permission signals to the corresponding processor 2.3.

The clock generation circuit 10.11 outputs an output signal to the group enable signal.
Count the number of occurrences of 2 in ~8, and when this count value reaches a predetermined value (for example, it may be 1),
Generates a shift clock for shift circuit 4.5.

FIG. 2 is a timing chart showing an example of the operation of the blocks in FIG. 1. When requests DRQa, DRQb, and DRQc for the right to use the bus are generated simultaneously from processors 1 to 3, the request DRQa from processor a has the highest priority. ) is generated from the secondary priority determination circuit 6 and sent to the requesting processor 1.

When this permission signal DAKa becomes low level,
There are two requested signals, DRQb and DRQc, but since DRQb has the highest priority, b■ is generated in D^ in the secondary priority determination circuit 7 and sent to the requesting processor 2. be done. Therefore, the request DRQc from the processor 3 will have to wait.

During this period, when the request DRQa is issued again from the processor 3, the permission signal DA of the DRQa after processing the previous DAKb■
Then, the process moves to a①, and the request DRQc is still kept waiting.

Here, the shift circuit 5 performs DRQC with four shift clocks.
', and generates [1RQC' with 8 shift clocks, and the clock generation circuits 10 and 11 both count the number of occurrences of 2 in input signals AKO~8, and the count value becomes '1'. It is assumed that a shift clock is generated every time 0 to AK2 is generated in the input signal (that is, a shift clock is generated every time the input signal 0 to AK2 occurs).

If this is done, DRQc' will first be outputted from the shift circuit 5 at the rising timing of b2 at D8. However, this DRQc' is DRQa DRQ
Since the priority is lower than b, the process is not executed yet. Next, when DRQC'" is output from the shift circuit 5 at the rising edge of b■ on D^, since this has a higher priority than DRQb, it is determined by the secondary priority determination circuit 6, and DAKa■ After the processing, the processing of DAKe'' is executed, and the request DRQC from the processor 3 is accepted for the first time.

When this request DRQc is accepted, DRQc becomes a low level, thereby also resetting the shift circuit 5, and canceling the respective bus occupancy request signals DRQc'', DRQc' and DRQc to the secondary priority determination circuits 6 to 8. and returns to the initial state.

DRQc'' has the lowest priority within group a, but DRQa and DRQb' are issued less frequently than DRQ.
Since the frequency with which DRQa and DRQb are issued for DRQc is lower than the frequency with which DRQa and DRQb are issued, there is little possibility that the processing of DRQc will be delayed forever, and therefore efficient processing can be performed.

As explained above, according to the present invention, by using a shift circuit to advance the priority of bus occupancy requests according to the number of bus occupancy permissions for the entire system, requests with lower priority are Originally, if a process continues to be in a waiting state for an arbitrary period of time, it becomes a state close to the top priority, and it is possible to avoid endlessly waiting for a process.

The rate at which the priority is raised can also be set for each request source, so it can be changed without ignoring the basic priority, such as decreasing the rate for request sources with low priority. By grouping the outputs of the shift circuit into a plurality of groups, it becomes easy to irregularly change the priority order and add request sources.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of this embodiment, and FIG. 2 is a time chart showing an example of the operation of the blocks in FIG. Explanation of symbols of main parts 1 to 3...Request source processor 4.5...Shift circuits 6 to 8...Secondary priority determination circuit 9...
・-Next priority determination circuit

Claims (1)

[Claims] (1) A plurality of shift circuits each receiving bus occupancy request signals from a plurality of request sources whose priorities are determined in advance and shifting these signals in response to a shift clock, and bus occupancy requests from the request sources. A bus occupancy request signal is provided in response to generation of a bus occupancy request signal in the corresponding group, and is provided corresponding to a plurality of groups obtained by dividing the signal and the shift output signal of each of the shift circuits according to a predetermined rule. a plurality of secondary priority determination circuits that determine the highest priority request signal according to a predetermined priority within the corresponding group and output the highest priority bus occupancy permission signal; a primary priority determination circuit that determines the group request signal for each group outputted from each of the secondary priority determination circuits according to a predetermined priority order and generates a permission signal for each group; a clock generation circuit that generates the shift clock in response to the generation of the permission signal of the group, and a clock generation circuit that generates the shift clock in response to the generation of the permission signal for each group; A bus use right control system characterized in that the bus occupancy permission signal is sent to the request source of the bus occupancy request signal with the highest priority.