JPH02232974A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02232974A
JPH02232974A JP1054225A JP5422589A JPH02232974A JP H02232974 A JPH02232974 A JP H02232974A JP 1054225 A JP1054225 A JP 1054225A JP 5422589 A JP5422589 A JP 5422589A JP H02232974 A JPH02232974 A JP H02232974A
Authority
JP
Japan
Prior art keywords
ferroelectric
superlattice
semiconductor device
mgal2o4
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1054225A
Other languages
Japanese (ja)
Inventor
Yasuki Sase
泰規 佐瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1054225A priority Critical patent/JPH02232974A/en
Publication of JPH02232974A publication Critical patent/JPH02232974A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve a ferroelectric film in stability and residual polarized charge density by a method wherein the ferroelectric film is formed in a multilayered hetero-superlattice structure which comprises at least one or more ferroelectric layers of perovskite crystal structure. CONSTITUTION:A high impurity concentration region 102 is formed on an Si substrate 101, and a buffer layer 103 of MgAl2O4 is formed thereon. Then, a PZT-MgAl2O4 superlattice 104 is formed. It is desirable that the final growth layer of the superlattice 104 is an MgAl2O4 108 of cubic system. Lastly, a metal 107 of Al or the like is sputtered thereon, and an electrode is provided to the region 102 and the metal 107 respectively.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、強誘電体を用いた、電気的に書き換え可能な
不揮発性メモリに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically rewritable nonvolatile memory using a ferroelectric material.

[発明の概要] 本発明は、強誘電体を用いた不揮発性メモリ半導体装置
に於て、強誘電体薄膜として、ペロブスカイト結晶構造
である強誘電体層を少くとも一層以上持つ多層構造から
なるヘテロ超格子構造として、結晶性の秀れた強誘電体
薄膜を得るようにしたものである。
[Summary of the Invention] The present invention provides a nonvolatile memory semiconductor device using a ferroelectric material, in which a ferroelectric thin film is a heterogeneous material having a multilayer structure having at least one ferroelectric layer having a perovskite crystal structure. A ferroelectric thin film with excellent crystallinity is obtained as a superlattice structure.

[従来の技術] 従来の半導体不揮発性メモリとしては、絶縁ゲート中の
トラップまたは浮遊ゲートに、シリコン基板からの電荷
を注入することによりシリコン基板の表面ポテンシャル
が変調される現象を用いたMIS型トランジスタが一般
に使用されており、K’F R O M (紫外線消去
型不揮発性メモリ)や、KKFROM(電気的書き換え
可能型不揮発性メモリ)などとして実用化されている。
[Prior Art] As a conventional semiconductor non-volatile memory, an MIS type transistor uses a phenomenon in which the surface potential of a silicon substrate is modulated by injecting charge from the silicon substrate into a trap or floating gate in an insulated gate. is generally used and has been put into practical use as K'FROM (ultraviolet erasable nonvolatile memory), KKFROM (electrically rewritable nonvolatile memory), and the like.

[発明が解決しようとする課題] しかし、これらの不揮発性メモリは情報の書き換え電圧
が、通常約2CIV前後と高いことや、書き換え時間が
非常に長い(例えば、EEFROMの場合数士1′rL
sec)等の欠点を有する。また情報の書き換え回数が
約105回程度であり、非常に書き換え可能回数が少く
、繰り返し使用する場合Kは問題が多い。
[Problems to be Solved by the Invention] However, these nonvolatile memories have a high voltage for rewriting information, usually around 2 CIV, and a very long rewriting time (for example, in the case of EEFROM, it takes about 1'rL
sec). Further, the number of times information can be rewritten is about 105 times, which is a very small number of times, and K has many problems when used repeatedly.

電気的に自己分極が反転可能である強誘電体を用いた、
不揮発性メモリについては、書き込み時間と読み出し時
間が原理的にほぼ同じであり、また電源を切っても分極
は保持されるため、理想的な不揮発性メモリとなる可能
性を有する。この様な強誘電体を用いた不揮発性メモリ
については、例えば、米国特許41 49302の様に
、シリコン基板上に強誘電体から成るキャパシタを集積
した構造や、米国特許3832700の様に、MエS型
トランジスタのゲート部分に強誘電体膜を配置した不揮
発性メモリ等の提案がなされている。
Using a ferroelectric material whose self-polarization can be electrically reversed,
Non-volatile memory has the potential to become an ideal non-volatile memory because the write time and read time are basically the same, and the polarization is maintained even when the power is turned off. Regarding nonvolatile memories using such ferroelectric materials, for example, there is a structure in which a capacitor made of ferroelectric material is integrated on a silicon substrate as in U.S. Pat. Nonvolatile memories and the like have been proposed in which a ferroelectric film is placed in the gate portion of an S-type transistor.

しかし、実際には強誘電体膜の安定性がなかったり、集
積化に適さなかったりしたために実用化には今だ至って
いない。
However, it has not yet been put into practical use because ferroelectric films lack stability and are not suitable for integration.

そこで本発明は、この様な課題を解決するもので、その
目的とする所は、強誘電体膜の安定性の改善,残留分極
電荷密度の改善を行った不揮発性メモリを提供するとこ
ろにある。
Therefore, the present invention aims to solve these problems, and its purpose is to provide a nonvolatile memory in which the stability of the ferroelectric film and the residual polarization charge density are improved. .

[課題を解決するための手段] 本発明の半導体装置は、その強誘電体薄膜が、ペロブス
カイト結晶構造強誘電体層が少くとも一層以上の多層構
造であるヘテロ超格子構造であることを特徴とする。
[Means for Solving the Problems] The semiconductor device of the present invention is characterized in that the ferroelectric thin film thereof has a hetero superlattice structure, which is a multilayer structure including at least one ferroelectric layer with a perovskite crystal structure. do.

[実施例コ 第1図は、本発明に於ける強誘電体薄膜を用いた半導体
装置の一実施例に於ける断面図である。
[Example 1] FIG. 1 is a sectional view of an example of a semiconductor device using a ferroelectric thin film according to the present invention.

以下第1図に従い、本発明の半導体装置を説明する。こ
こでは、説明の都合上81基板を用い、ヘテロ超格子の
材料としてMgAt,O,をPZTを用いた例につき説
明する。
The semiconductor device of the present invention will be described below with reference to FIG. Here, for convenience of explanation, an example in which an 81 substrate is used and PZT is used as the material of the hetero superlattice will be described.

101はN− (または、P−)Si基榎であるこれに
102で示す濃い不純物濃度領域N+ (またはP+,
基板の不純物型に準ずる。)を例えば、イオン打ち込み
法等で形成する。
Reference numeral 101 is an N- (or P-) Si substrate, and a heavily impurity concentration region N+ (or P+,
Depends on the impurity type of the substrate. ) is formed by, for example, an ion implantation method.

次に、S1とPZTの両方と格子整合性の良いMgAt
,O,をバッ7ア層103としてovD法等を用いてエ
ビタキシャル形成する。例えば3μrrL程度成長する
Next, MgAt has good lattice matching with both S1 and PZT.
, O, are used as the buffer layer 103 and are formed epitaxially using the ovD method or the like. For example, it grows by about 3 μrrL.

次に、光OVD法等のエビタキシャル成長法を用い、P
ZT−MgAl2O4超格子104を作製する。このエ
ビタキシャル成長時にはSi基板に高周波をかけること
により0軸配向性を持たせる必要がある。
Next, using an epitaxial growth method such as the optical OVD method, P
A ZT-MgAl2O4 superlattice 104 is produced. During this epitaxial growth, it is necessary to impart zero-axis orientation by applying high frequency to the Si substrate.

この超格子においては、従来のMgAt,04上に成長
させたPZT膜でよく見られる様に、基板からの応力に
よるα軸配向性への配向性の反転が、歪超格子となるこ
とで応力を吸収してしまうために防ぐことができる。従
って、その超格子の周期はなるべく小さくするのがよい
。例えば30A−5OA 超格子の最終成長層となるのは立方晶である、MgAt
t04108とするのが良い。
In this superlattice, as is often seen in conventional PZT films grown on MgAt. can be prevented from being absorbed. Therefore, it is preferable to make the period of the superlattice as small as possible. For example, the final growth layer of the 30A-5OA superlattice is a cubic MgAt
It is better to set it to t04108.

最後に、At等の金属107をスパッタ法等で形成し、
81基板上のN  (P  )領域と、金属部に電極を
取シ付けることにより、本発明の半導体装置の一実施例
の構造を得る。
Finally, a metal 107 such as At is formed by sputtering or the like,
By attaching electrodes to the N (P) region on the 81 substrate and the metal portion, a structure of an embodiment of the semiconductor device of the present invention is obtained.

さて従来の強誘電体膜を用いた不揮発性メモリに於いて
は、強誘電体膜はスパッタ法等により、セラミックの形
で形成されていた。この様に不揮発性メモリに於いては
、その特性が、例えば情報の保持特性に着目してみると
約8ケ月(常温に換算)しかもたなかった。この原因を
詳細に調べてみると、強誘電体の結晶粒界に於いて劣化
が進んでいることが分った。そこで本発明の様に強銹電
体薄膜を用いると、ほぼ0軸配向の単結晶が得られるた
め、結晶粒界はほとんどな《、その保持特性が約2年(
常温に換算)と改善できた。
In conventional nonvolatile memories using ferroelectric films, the ferroelectric film is formed in the form of ceramic by sputtering or the like. As described above, when looking at the characteristics of non-volatile memory, for example, focusing on the information retention characteristics, it lasts only about eight months (converted to room temperature). When the cause of this was investigated in detail, it was found that the deterioration progressed at the grain boundaries of the ferroelectric material. Therefore, when a strong electric thin film is used as in the present invention, a single crystal with almost 0-axis orientation can be obtained, so there are almost no grain boundaries.
(converted to room temperature).

また、結晶の配向軸が揃っている為、残留分極電荷密度
が太き《なったことも原因の一つであるまた、本発明の
趣旨は強誘電体膜の特性の改善である為、下地の構造は
第1図で説明した様な構造ばかりでな<、OMOS構造
、バイボーラトランジスタを用いた構造、バイボーラ/
 O M O S (7)構造、また基板としてもS1
ばかりではなくパッファ一層に強誘電体,基板共に格子
整合性のある材料を用いればG a A℃等の化合物半
導体を用いても良いことは言うまでもない。
In addition, one of the reasons is that the remanent polarization charge density has become thicker because the orientation axes of the crystals are aligned. The structure is not only the structure explained in Fig. 1, but also the OMOS structure, the structure using bibolar transistors, and the structure using bibolar transistors.
OMOS (7) S1 structure and also as a substrate
It goes without saying that a compound semiconductor such as GaA° C. may also be used as long as both the ferroelectric material and the substrate in the puffer layer are made of materials with lattice matching.

また、この方法はベロプスカイト結晶系の材質すべてに
有効であって、高温超伝導膜を形成した半導体装置に有
効であることは言うまでもない。
It goes without saying that this method is effective for all materials of the velopskite crystal system, and is also effective for semiconductor devices in which a high-temperature superconducting film is formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の実施例のひとつである半導体装置(
コンデンサ)の主要断面図である。 101・・・・・・S1基板 102・・・・・・高不純物濃度領域 103・・.・・・・MgAt,O,バッファ層1 0
 4 = − M g A t t O , − P 
Z T超格子105・・・・・・PzT層 106・・・・・・MgAl2O4層 107・・・・・・At電極 108・・・・・・MgAl2O4 }ップ層以上 [発明の効果コ 以上述べてきた様に、本発明の半導体装置に於いて、強
誘電体膜の特性が向上した為、強誘電体膜を用いた不揮
発性メモリが製造出来るという効果を有する。
FIG. 1 shows a semiconductor device (
FIG. 2 is a main cross-sectional view of a capacitor. 101...S1 substrate 102...High impurity concentration region 103... ...MgAt,O, buffer layer 1 0
4 = − M g A t t O , − P
Z T superlattice 105...PzT layer 106...MgAl2O4 layer 107...At electrode 108...MgAl2O4 }Up layer or above [Effect of the invention or above] As described above, in the semiconductor device of the present invention, since the characteristics of the ferroelectric film are improved, a nonvolatile memory using the ferroelectric film can be manufactured.

Claims (2)

【特許請求の範囲】[Claims] (1)強誘電体薄膜を用いた半導体装置に於いて、前記
強誘電体薄膜が、ペロブスカイト結晶構造である強誘電
体層を少くとも一層以上持つ多層構造からなるヘテロ超
格子構造であることを特徴とする半導体装置。
(1) In a semiconductor device using a ferroelectric thin film, the ferroelectric thin film has a hetero superlattice structure consisting of a multilayer structure having at least one ferroelectric layer having a perovskite crystal structure. Characteristic semiconductor devices.
(2)前記強誘電体薄膜を構成するペロブスカイト結晶
構造強誘電体の主成分が、PbTiO_3、PZT(P
bTiO_3/PbZrO_3)、PLZT(La/P
bTiO_3/PbZrO_3)のうちいずれかであり
、それとヘテロ接合をなす材料がMgAl_2O_4で
あることを特徴とする請求項1記載の半導体装置。
(2) The main components of the perovskite crystal structure ferroelectric material constituting the ferroelectric thin film are PbTiO_3, PZT(P
bTiO_3/PbZrO_3), PLZT(La/P
2. The semiconductor device according to claim 1, wherein the material forming a heterojunction therewith is MgAl_2O_4.
JP1054225A 1989-03-07 1989-03-07 Semiconductor device Pending JPH02232974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1054225A JPH02232974A (en) 1989-03-07 1989-03-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1054225A JPH02232974A (en) 1989-03-07 1989-03-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02232974A true JPH02232974A (en) 1990-09-14

Family

ID=12964600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1054225A Pending JPH02232974A (en) 1989-03-07 1989-03-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02232974A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994010704A1 (en) * 1992-10-23 1994-05-11 Symetrix Corporation Integrated circuit with layered superlattice material and method of fabricating same
US5423285A (en) * 1991-02-25 1995-06-13 Olympus Optical Co., Ltd. Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications
US5434102A (en) * 1991-02-25 1995-07-18 Symetrix Corporation Process for fabricating layered superlattice materials and making electronic devices including same
US5468679A (en) * 1991-02-25 1995-11-21 Symetrix Corporation Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications
US5688565A (en) * 1988-12-27 1997-11-18 Symetrix Corporation Misted deposition method of fabricating layered superlattice materials
US5719416A (en) * 1991-12-13 1998-02-17 Symetrix Corporation Integrated circuit with layered superlattice material compound
US5803961A (en) * 1992-10-23 1998-09-08 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
US5871853A (en) * 1992-10-23 1999-02-16 Symetrix Corporation UV radiation process for making electronic devices having low-leakage-current and low-polarization fatigue
US6056994A (en) * 1988-12-27 2000-05-02 Symetrix Corporation Liquid deposition methods of fabricating layered superlattice materials
US6080592A (en) * 1991-02-25 2000-06-27 Symetrix Corporation Method of making layered superlattice materials for ferroelectric, high dielectric constant, integrated circuit applications
KR100273884B1 (en) * 1996-07-24 2000-12-15 가네꼬 히사시 Reduced fatigue ferroelectric element
US6207465B1 (en) * 1998-04-17 2001-03-27 Symetrix Corporation Method of fabricating ferroelectric integrated circuit using dry and wet etching
WO2002073680A3 (en) * 2001-03-09 2003-10-16 Symetrix Corp Method of making layered superlattice material with ultra-thin top layer
US6890768B2 (en) 2001-03-09 2005-05-10 Symetrix Corporation Method of making layered superlattice material with ultra-thin top layer
CN100355042C (en) * 2001-03-09 2007-12-12 塞姆特里克斯公司 Method of making layered superlattice material with ultra-thin top layer

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5688565A (en) * 1988-12-27 1997-11-18 Symetrix Corporation Misted deposition method of fabricating layered superlattice materials
US6056994A (en) * 1988-12-27 2000-05-02 Symetrix Corporation Liquid deposition methods of fabricating layered superlattice materials
US5825057A (en) * 1991-02-25 1998-10-20 Symetrix Corporation Process for fabricating layered superlattice materials and making electronic devices including same
US6080592A (en) * 1991-02-25 2000-06-27 Symetrix Corporation Method of making layered superlattice materials for ferroelectric, high dielectric constant, integrated circuit applications
US5423285A (en) * 1991-02-25 1995-06-13 Olympus Optical Co., Ltd. Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications
US5434102A (en) * 1991-02-25 1995-07-18 Symetrix Corporation Process for fabricating layered superlattice materials and making electronic devices including same
US5468679A (en) * 1991-02-25 1995-11-21 Symetrix Corporation Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications
US5719416A (en) * 1991-12-13 1998-02-17 Symetrix Corporation Integrated circuit with layered superlattice material compound
US5871853A (en) * 1992-10-23 1999-02-16 Symetrix Corporation UV radiation process for making electronic devices having low-leakage-current and low-polarization fatigue
US6133050A (en) * 1992-10-23 2000-10-17 Symetrix Corporation UV radiation process for making electronic devices having low-leakage-current and low-polarization fatigue
WO1994010704A1 (en) * 1992-10-23 1994-05-11 Symetrix Corporation Integrated circuit with layered superlattice material and method of fabricating same
US5909042A (en) * 1992-10-23 1999-06-01 Symetrix Corporation Electrical component having low-leakage current and low polarization fatigue made by UV radiation process
US5955754A (en) * 1992-10-23 1999-09-21 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
US5803961A (en) * 1992-10-23 1998-09-08 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
WO1994010702A1 (en) * 1992-10-23 1994-05-11 Symetrix Corporation Process for fabricating layered superlattice materials and making electronic devices including same
US5840110A (en) * 1992-10-23 1998-11-24 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
KR100407232B1 (en) * 1992-10-23 2004-06-26 시메트릭스 코포레이션 Integrated circuit and direct circuit manufacturing method
KR100273884B1 (en) * 1996-07-24 2000-12-15 가네꼬 히사시 Reduced fatigue ferroelectric element
US6207465B1 (en) * 1998-04-17 2001-03-27 Symetrix Corporation Method of fabricating ferroelectric integrated circuit using dry and wet etching
WO2002073680A3 (en) * 2001-03-09 2003-10-16 Symetrix Corp Method of making layered superlattice material with ultra-thin top layer
US6890768B2 (en) 2001-03-09 2005-05-10 Symetrix Corporation Method of making layered superlattice material with ultra-thin top layer
CN100355042C (en) * 2001-03-09 2007-12-12 塞姆特里克斯公司 Method of making layered superlattice material with ultra-thin top layer

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