JPH02224223A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid channeling of ions in a gate electrode and increase the resistance of the gate electrode by a method wherein the gate electrode is made from a laminated unit composed of a polycrystalline silicone layer and an amorphous silicon layer. CONSTITUTION:As an amorphous silicon layer 8 free from grains causing channeling is formed on a polycrystalline layer 7 of which a gate electrode 9 is composed, channeling in the gate electrode produced when ions are implanted for forming source and drain is blocked by the amorphous silicon layer 8. Further, if a thermal treatment is performed after the amorphous silicon is doped with impurity, the resistance of the amorphous silicon becomes lower than that of polycrystalline silicon by about 20% and hence the resistance of the gate electrode 9 is reduced. With this constitution, a MOS-FET which has no channeling in its gate electrode 9, has stable characteristics and, further, has the low gate electrode 9 resistance can be obtained.

Description

[Detailed Description of the Invention] [Summary] Improvement of MO3 type field effect transistor (MOS type FET), especially a structure that prevents ion channeling from occurring in the gate electrode during ion implantation to form the source and drain. With regard to the improvement, we aim to provide a MOS FET with stable characteristics and low resistance of the gate electrode without the need for an increase in the number of processes, without the occurrence of channeling in the gate electrode. The semiconductor device includes a gate insulating film formed on a gate electrode formation region on a semiconductor layer of a mold, and a gate electrode made of a stacked body of a polycrystalline semiconductor layer and an amorphous semiconductor layer on the gate insulating film.

[Industrial application field]

The present invention is an MO3 type field effect transistor (MOS type F).
The present invention relates to improvements in ET), particularly structural improvements to prevent ion channeling from occurring in the gate electrode during ion implantation to form sources and drains.

[Conventional technology]

Refer to FIG. 7 In FIG. 7, which is a block diagram of a MOS type FET according to the prior art, 3 is an n-type silicon layer, for example.
5 is a LOGOS field insulating film, 6 is a gate oxide film, 9 is a gate electrode made of polycrystalline silicon, 17 is a silicon dioxide insulating film, and 16 is formed by ion-implanting p-type impurities. 18 is a source/drain electrode.

The source/drain 16 is formed by forming the gate electrode 9 and then ion-implanting p-type impurities through a self-alignment line using the gate electrode 9 as a mask. At this time, if ion channeling occurs in the gate electrode 9, the characteristics of the MO3 type FET will deteriorate. In recent years, gate lengths have become shorter and shorter in order to increase speed, but the shorter the gate length, the greater the influence of channeling. The following methods have been used to prevent gate electrode channeling. That is, a gate electrode 9 made of polycrystalline silicon is formed on the gate oxide film 6, and then the surface of the polycrystalline silicon layer forming the gate electrode 9 is oxidized to form a silicon dioxide film 17, or a CVD method is used. After forming silicon dioxide 1K17 on the polycrystalline silicon layer constituting the gate electrode 9 using a method such as the above, ions are implanted to form the source and drain, thereby preventing the occurrence of a channeling phenomenon in which ions penetrate through the gate electrode. It is prevented.

[Problem to be solved by the invention]

By the way, the number of steps is increased in order to form a silicon dioxide film on the surface of the polycrystalline silicon layer forming the gate electrode.

In addition, impurity phosphorus is doped to reduce the resistance of the gate electrode 9, but as the concentration of impurity phosphorus increases, the grains of polycrystalline silicon grow larger, so the surface of polycrystalline silicon is blocked with a silicon dioxide film. However, the phosphorus concentration cannot be made too high because channeling is likely to occur, and therefore the resistance of the gate electrode 9 cannot be made sufficiently low. There is also a method of laminating layers, but this increases the number of steps and is not preferable.

The purpose of the present invention is to eliminate this drawback, and to provide an MO3 type FET that does not involve an increase in the number of steps, has no channeling in the gate electrode, has stable characteristics, and has a low resistance of the gate electrode. Our goal is to provide the following.

[Means to solve the problem]

The above purpose is to form a gate insulating film (6) formed on a gate electrode formation region on a - conductivity type semiconductor layer (3), and a polycrystalline semiconductor layer (, 7) formed on this gate insulating film (6). This is achieved by a semiconductor device having a gate electrode (9) made of a laminate of an amorphous semiconductor layer (8) and an amorphous semiconductor layer (8).

[Effect]

In the MO3 type FET according to the present invention, the gate electrode 9
On the polycrystalline silicon layer 7, an amorphous silicon layer 8 is formed, which does not contain grains that cause channeling. Channeling is blocked. Furthermore, if amorphous silicon is doped with impurities and then heat treated, the resistance value will be about 20% lower than that of polycrystalline silicon, so the resistance of the gate electrode will be lowered. Note that the gate electrode 9 is not formed only of amorphous silicon because
The growth rate of amorphous silicon is 1 that of polycrystalline silicon.
/4 or less, and this drawback is compensated for by forming a laminate of polycrystalline silicon and amorphous silicon.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a complementary MOSFET according to an embodiment of the present invention will be explained with reference to the drawings to further clarify the structure of the present invention.

Refer to FIG. 2. For example, an n-type impurity such as antimony is ion-implanted into the p-channel FET formation region of the p-type silicon substrate 1.
After forming an anti-inversion layer 2 and epitaxially growing an n-type 2937 layer 3 to a thickness of about 1.5 Jl on the entire surface, a p-type well 4 is formed by ion-implanting p-type impurities such as boron into the n-channel FET formation region. Next, a Lacos field insulator 1II5 is formed surrounding the element formation region, and the entire surface is oxidized to form a gate oxide film 6 with a thickness of about 200 nm. A polycrystalline silicon layer 7 is formed to a thickness of about 1,500 layers,
Subsequently, the growth temperature is lowered to about 570° C. to form the amorphous silicon layer 8 as thick as human skin.

See Figure 3. Implanting n-type impurities such as phosphorus with an energy of approximately 70 KeV
After performing gate doping by ion implantation with a dose of 7×10 “CI-”, the polycrystalline silicon layer 7 and the amorphous silicon layer 8 are patterned to form a gate electrode 9.

Refer to FIG. 4. To form low impurity concentration regions for the source and drain of the n-channel FET, a resist layer 10 is formed in the p-channel FET formation region, and n-type impurities such as phosphorus are implanted at an energy of about 50 KeV.

The n- layer 11 is formed by ion implantation with a dose of I x 10 l3CI-''.

Refer to FIG. 5.Resist layer 10 is removed, and a silicon dioxide layer is formed on the entire surface to a thickness of about 2,500 nm using CVD method, etc., and reactive ion etching is performed to form a silicon dioxide layer only on the side walls of the gate electrode. 12 remains, a resist layer 13 is again formed in the p-channel FET formation region, and n-type impurities such as arsenic are ion-implanted with an energy of about 120 KeV and a dose of 4 x 10 "CM-".
The source and drain 14 of the channel FET are formed.

Refer to FIG. 6. After removing the resist layer 13 and forming a resist layer 15 in the n-channel FET formation region,
Type impurities are ion-implanted with an energy of about 60 KeV and a dose of 2 x 10 "ell-" to form the source/drain 16 of the p-channel FET.

Refer to FIG. 1, the resist layer 15 is removed, and an insulating film 17 made of silicon dioxide or the like is formed on the entire surface to a thickness of about 1,000 wafers using a CVD method or the like, and openings are formed in the source/drain electrode forming regions. Next, after forming an aluminum film, this is patterned to form source/drain electrodes 18.

〔Effect of the invention〕

As explained above, in the MO3 type FET according to the present invention, since the gate electrode is constituted by a laminate of a polycrystalline silicon layer and an amorphous silicon layer, the source/drain forming region is formed using a self-alignment line using the gate electrode as a mask. When ions are implanted into the gate electrode, ion channeling is prevented from occurring in the gate electrode due to the amorphous silicon layer having no grains that cause channeling. If channeling of the gate electrode is eliminated, the thickness of the gate oxide film, which was conventionally about 300 to 400, can be reduced to about half, making it possible to lower the threshold voltage of the MO3 type FET. Furthermore, since the resistance of amorphous silicon is lower than that of polycrystalline silicon, the resistance of the gate electrode can be lowered.

If the resistance of the gate electrode is the same as the conventional one, the thickness of the gate electrode can be made thinner, making it possible to flatten the gate electrode and improve the reliability of the wiring. Note that polycrystalline silicon and amorphous silicon that form the gate electrode can be formed in the same step using the CVD method by simply changing the growth temperature, so manufacturing is easy and there is no particular increase in the manufacturing process. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a C-MOSFET according to an embodiment of the present invention. FIG. 2 to FIG. 6 show a C-MOS according to an embodiment of the present invention.
It is a manufacturing process diagram of FET. FIG. 7 is a configuration diagram of a MOSFET according to the prior art. DESCRIPTION OF SYMBOLS 1... Opposite conductivity type semiconductor substrate, 2...-conductivity type reversal prevention layer, 3 ・ ・ 4 ・ ・ 5 ・ ・ 6 ・ ・ 7 ・ ・ 8 ・ ・ 9 ・ ・ lO ・ ・ 11 ・ ・ 12・ 13・ ・ 14・ ・ 15・ ・ 16・ ・ 17・ ・ 18・ ・ ・-conductivity type semiconductor layer, ・Opposite conductivity type well, ・LOCOS insulating film, ・Gate insulating film, ・Polycrystalline silicon layer, ・Amorphous Silicon layer, ・Gate electrode, ・Resist layer, ・Low impurity concentration region, ・Silicon dioxide layer, ・Resist layer, ・N-type source/drain, ・Resist layer, ・P-type source/drain, ・Insulating film, ・Source・Drain electrode.

Claims (1)

[Claims] A gate insulating film (6) formed on a gate electrode formation region on a semiconductor layer (3) of one conductivity type;
) on which a polycrystalline semiconductor layer (7) and an amorphous semiconductor layer (
A semiconductor device characterized by having a gate electrode (9) made of a laminate of a semiconductor device and a gate electrode (9).