JPH02223285A - Superimposing circuit - Google Patents

Abstract

PURPOSE:To attain superimposing with a desired color by providing an oscillation circuit oscillating a chrominance subcarrier phase-locked with a burst signal of a video signal and modulating a color difference signal of an additional signal such as a character with the oscillation output. CONSTITUTION:An oscillation circuit 14 is provided, which oscillates a chrominance subcarrier phase-locked with a burst signal of a video signal and a color difference signal of the additional signal such as character is modulated by a modulation circuit 12 with an output of the oscillation circuit 14. Thus, the color difference signal of the additional signal is modulated by the chrominance subcarrier phase-locked to the burst signal of the video signal. Thus, the character paving a desired stable color is superimposed.

Description

[Detailed description of the invention] [Industrial application field] The present invention is applicable to video equipment that supports NTSC.

The present invention relates to a superimpose circuit that superimposes characters, etc. on a composite signal such as PAL, and particularly relates to colorization of the characters, etc.

[Prior Art] For example, during playback of a videotape, the remaining amount of tape, etc. may be displayed on the screen. This display is performed by superimposing a character signal on a composite signal such as NTSC signal reproduced by a video deck. In this way, when a reproduced video signal and a character signal to be added are to be synthesized inside a video deck, a circuit as shown in FIG. 13 has been used. That is, by switching the analog switch 2.degree. 4, a desired character signal is inserted into the reproduced video signal. For example, Figure 14A
When a character signal as shown in FIG. 14B is added to a reproduced video signal as shown in FIG. 14, a composite signal as shown in FIG. 14C is obtained. When this composite signal is displayed, white characters are displayed in the video. In addition, in FIG. 14A, 6 is a horizontal synchronization signal, and 8 is a burst signal.

[Problems to be Solved by the Invention] However, in the superimpose circuit as described above, the added signal includes only a luminance component. Therefore, only white, black, and gray characters could be inserted.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a circuit that can superimpose color characters, etc. in a video deck or the like.

[Means for Solving the Problems] A superimpose circuit according to the present invention includes an oscillation circuit that oscillates a color subcarrier that is phase-locked with a burst signal of a video signal, and the output of this oscillation circuit generates characters, etc. The color difference signal of the additional signal is modulated.

[Operation] In the TV signal, each color is represented by a phase difference with respect to the burst signal. In this invention, the color difference signal of the additional signal is modulated by a color subcarrier phase-locked to the burst signal of the video signal. Therefore, characters with a desired stable color can be superimposed.

[Embodiment] -NTSC system- Fig. 1A shows a superimpose circuit for the NTSC system according to an embodiment of the present invention. The reproduced video signal is input to the video input terminal P, and the character signal to be superimposed is input to the input terminals S6, SG, and S. The character signal, which is this additional signal, is composed of the R signal, G signal, and B signal, which are the three primary colors. This R signal, G
In the matrix 16, which is an additional color difference signal generation circuit, the B signal is used as the luminance signal EY and the color difference signal E R-E.
'v is converted into a color difference signal Es-EY. These luminance signals and color difference signals are sent to the pedestal clamp circuit 17.
, 18.19, the pedestal level is adjusted.

On the other hand, the video signal reproduced by the magnetic head is level-adjusted by a pedestal clamp 29 and then applied to a switching circuit 38 which is switching means. At the same time, from this video signal, only the synchronization signal is separated in the synchronization separation circuit 27 and then provided to the timing generator 28 .

The timing generator 28 generates pulses necessary for displaying images, such as burst signal timing. The details are shown in Figure 2. The horizontal synchronization signal Ha ya c from the synchronization separation circuit 27 is sent to the flip-flop 29
It is input to reset terminals 6, 298, 300, 302, and 304. The vertical synchronization signal Lyac is input to the reset terminals of flip-flops 310 and 312.

On the other hand, a clock PI having a frequency four times that of the color subcarrier is input to the input terminal 28a. This clock P1
is obtained by multiplying the output of a PLL circuit, which will be described later, by four. The input clock P1 is input to the 455-decimal counter 28.
Counted by 0. The output of each stage of the counter 280 is the logic circuit 286, 288, 290292.29
4 through flip-flops 296, 298, 300
302.304 is applied to the set terminal. That is, each flip-flop 296, 298, 300, 302
, 304 are reset by the fall of the horizontal synchronization signal Hayna, and the logic circuits 286, 288
, 290, 292, 294. Therefore, the logic circuits 286, 288, 290,
292 and 294, each flip-flop 29
Inverted output (Q) of 6,298,300,302,304
B3. Bl, B2. The pulse lengths of BY and FP can be arbitrarily determined.

In this timing generator 28, as shown in FIG.
02304 inverted outputs HS, Bl, B2. Obtained BY and FP. In FIG. 3, each pulse Is, Bl, B2. B
In order to clarify the significance of Y and FP, the correspondence with video signals is shown. For example, pulse H5 is horizontal synchronization signal H*y
This corresponds to ag. That is, the flip-flop 296 receives horizontal synchronizing signals H, A,. The logic circuit 286 is configured to be set 4.7 μhec after being reset by the falling edge of PT (obtained by counting the clock pt). Other pulse B
l.

B2. The same applies to BY and FP.

AND3 the inverted version of pulse H8 and pulse B2
Through 14, pulse G1 is obtained. This pulse G1
is used for pedestal clamps. Also, pulse B
Pulse G2 is obtained by ANDing 316 the inverted version of l and pulse B2. This pulse G2 is used for burst gate.

Returning to FIG. 1A, the burst gate 30 receives the burst timing pulse G2 from the timing generator 28.
Based on this, only the burst signal is extracted from the video signal.

FIG. 4 shows details of this burst gate. A video signal as shown in FIG. 5A is input to the signal input terminal 30a.
is input. On the other hand, the gate input terminal 30b has a fifth
A burst timing pulse G2 shown in Figure B is provided. Therefore, the analog switch 30d takes out the signal only during the H period of the pulse G2, and only the burst signal 8 (FIG. 5C) is obtained at the output 30c.

This burst signal 8 is transmitted to a PLL circuit 14 which is an oscillation circuit.
is applied to the phase comparator 32. The phase-locked loop (PLL) circuit 14 includes a phase comparison circuit 32, a low-pass filter 33, and a voltage-controlled oscillation circuit 34, and outputs an oscillation output locked to the phase of the signal input to the phase comparator 32. That is, this PLL circuit 14 outputs an oscillation output 80 that is phase-locked to the burst signal 8.

This oscillation output 80 is provided to modulators 24.26.

Details of the modulator 24 are shown in FIG. Carrier wave input terminal 2
4a includes a PLL 14 phase-locked to the burst signal 8.
An output 80 is given. A color difference signal ER-EY of a character signal is applied to the modulated signal input terminal 24b. The modulator 26 has a similar configuration, but the color difference signal E is connected to the terminal 24b.
, -EY are given with a phase difference of 90°.

These modulators 24, 26 switch transistors Q1 and Q2 and transistors Q1 and Q4 according to a signal from carrier input terminal 24a to perform balanced modulation.

Therefore, from the output 24c, the color difference signal ER-EY is modulated using the output 80 of the PLL 14 as a color subcarrier.
(El-EY) is taken out. That is, the color difference signal Ell-EY and the color difference signals E and -EY are modulated by color subcarriers synchronized (phase locked) with the burst signal of the video signal. In addition, the color difference signal E, 1-Ev and the color difference signal E
, -EY are modulated with a phase difference of 90°.

The modulated output 241 of the color difference signal E*-Ev and the color difference signal E,
The modulated outputs 261 of -E1 are added in the adder 25. This addition output 251 is further added with the luminance signal EY in an adder 27, and then the modulated character signal 2
71 to the switch 38.

Switching between the video signal 100 and the modulated character signal 271 is performed by a switching circuit 38. Normally, the video signal 100 is output from the output OUT, but the character signal is output only when the switching signal 150 from the switching signal generating circuit 10 becomes H level. The switching signal generating circuit 10 sets the switching signal to H level only during the character insertion period in accordance with the character insertion timing. Video signal 10
0 in FIG. 7A, the modulated character signal 271 in FIG. 7B,
The switching signal 150 is shown in FIG. 7C.

When the switching signal 150 is at L level, the reproduced video signal 100 including the burst signal 8 is output as is from the output OUT. When the switching signal 150 becomes H level,
The modulated character signal 271 is obtained from the output OUT only during the H period. Therefore, a composite output as shown in Figure 7 is obtained from the output OUT.

In this composite output, the modulated character signal 271 is modulated by the color subcarrier 80 phase-locked to the burst 8 of the reproduced video signal 100. Therefore, characters having a desired color can be superimposed.

This allows the time and mode to be displayed in color text, as well as ``Search'' and ``Still'' information, etc., to be displayed during video playback.

In the above, a case has been described in which superimposition is performed on a color video signal. However, if the video signal is a black and white signal, there is no burst signal 8, so color characters cannot be displayed. Further, color characters cannot be displayed even when no video signal is input.

Therefore, in this embodiment, in order to superimpose color characters even in the above case, the following steps are taken. If no video signal is input, burst signal 8
is not entered either. Therefore, PLL circuit 1 of FIG. 1A
4 outputs an oscillation output at a free-running frequency. This free running frequency is set to be the frequency f16 of the burst signal. As described above, the output 80 of the PLL circuit 14 is multiplied by four (4f, . . . ) and fed to the counter 280 of the timing generator in FIG. Since no video signal is being given now, the horizontal synchronizing signals H and A are sent. . Also, the vertical synchronization signal Vsyat is not input. Therefore, the frequency f of the horizontal synchronization signal Hsyeg and the vertical synchronization signal v,
,. .

By utilizing the following relationship between the frequency fv of the burst signal and the frequency fat of the burst signal, the horizontal synchronizing signal H', . .

and vertical synchronization signal V'sya. is being generated.

f@g = (455/2)-fH f,, = (1/4)・455・525・fV In other words, since the signal input from the terminal 28a has a frequency of 4f, 6, the counter 280 calculates 455 minutes. The frequency is then divided by two by the counter 282 to obtain the frequency f,
A horizontal synchronization signal H'*ya having a horizontal synchronization signal H'*ya. I am getting .

The vertical synchronizing signals V'sy, , e are obtained by dividing the output of the counter 280 by 525 by a counter 284.

When a video signal is input, a synchronization signal L 7 n t + V # 711 e separated from the video signal
The flip-flops 296, 298, 300, 302,
304, but here H' @ 7116 + V' @ 7 n C generated above is given. Therefore, even if the video signal is not manually input, the timing generator 28 operates.

Timing generator 28 obtained as described above
and the output of the PLL circuit 14 are provided to a burst signal/synchronization signal generation circuit 36.

Details of the burst signal/synchronization signal generation circuit 36 are as shown in FIG. 1B. 4 analog switches 160
, 162, 164, and 166 are provided. A burst voltage of H level (see FIG. 1C) is input to the analog switch 160. analog switch 162
A burst voltage of L level (see FIG. 1C) is manually applied to . Further, the analog switch 164 receives a pedestal level voltage, and the analog switch 166 receives a voltage of 5.
ync Tip (bottom level of the mill level signal) is input (see FIG. 1C). Each analog switch 160, 162, 164, 166 closes only when the control input becomes H level.

An AND output of the burst timing pulse G2 from the timing generator 28 and the output of the PLL circuit 14 is applied to the control input of the analog switch 160. On the other hand, the control input of the analog switch 162 receives the burst timing pulse G from the timing generator 28.
2 and an inverted version of the output of the PLL circuit 14. Therefore, from output 168, the first
A burst signal 80a as shown in FIG. C is obtained.

In addition, the analog switch 166 is controlled manually by a pulse H3 from the timing generator 28 (see FIG. 3).
is given. Therefore, as shown in FIG. 1C, a horizontal synchronization signal H'@7!1e is generated.

Note that the vertical synchronization signals v゛ and a. . is formed in the same manner. Furthermore, the control input of the analog switch 164 is given a pulse that becomes H only during a period in which the burst timing pulse G2 is not H, the pulse HS is not H, and the video signal is not supposed to be output. That is, API, AP2. H only during the period shown in AP3
A control signal is given. Thus, a pedestal level is formed.

Burst and synchronization signal 3 generated as above
61 is applied to the adder 27.

By the way, when displaying characters when no video signal is provided, they are often displayed against a background such as blue. In this case, character signal input (SR, SG to Figure 1)
, 5ll) are given a green signal, and a text color signal is given only to the text portion.

These signals are converted into a luminance signal EY and color difference signals Elf-EY and El-EY by the matrix 16.

The color difference signals E, -EY, E, -EY are modulated by modulators 24 and 26 and then added by adder 25. The added signal is given to the adder 27 and added to the luminance signal.

Since the adder 27 is also supplied with the burst and synchronization signals 361 as described above, the output of the adder 27 provides the signals necessary for display.

This signal is taken out via switch 38 and used as an output. Note that in this case, the switch 38 outputs the output 271.
It remains switched to the side.

Even if the video signal is not input as described above,
It is possible to display characters, etc.

FIG. 8 shows a superimpose circuit according to another embodiment. In this example, from matrix 16,
R signal, Yellow signal, G signal, Cyan signal, B
A Magenta signal is output, and each is modulated in a phase shift level circuit 40a, 40b . . . 40f. That is, in this embodiment, the phase level circuit 4
A modulator 12 is constituted by 0a, 40b, . . . , 40f.

-PAL system- Next, FIG. 9A shows an embodiment in which the present invention is applied to a PAL system video signal. The basic circuit configuration is the same as the circuit shown in FIG. timing generator 2
85 is a circuit configuration as shown in FIG. 12, for example. It has the same configuration as the timing generator 28 in FIG. 2, except that a signal obtained by multiplying the output of the PLL circuit 14 by eight is applied to the input terminal 28a, and a 909-base counter 281.625-base counter 283 is used. This timing generator 285 outputs each timing pulse to correspond to a PAL video signal. In the PAL system, as shown in FIGS. 10A and 10B, it is specified that the phase of the color difference signal EY is inverted for each line. In addition, the burst signals are color difference signals E, -E
With respect to Y, a phase difference of +135° and -135° is specified for each line.

The timing generator 285 provides the horizontal synchronization signal Hsy□ and the vertical synchronization signal Vmyat separated by the synchronization separation circuit 27 to the line discrimination circuit 294. The line discrimination circuit 700 includes a T flip-flop 705 as shown in FIG. This T flip-flop 2
705 is reset by the vertical synchronization signal Vay+'+c, and the discrimination cuff 0 is reset by the horizontal synchronization signal H*yne.
1 is changed to H, LSH, etc.

The changeover switch 330 is switched line by line based on this discrimination output. As a result, the output of the voltage controlled oscillator 34 is shifted in phase by 90 degrees by the phase shifter 335 every other line, and is applied to the phase comparator 32. Therefore, even though the phase of the burst signal inputted from the burst gate 30 is shifted by 90 degrees for each line, the PLL circuit 14 is phase-locked to the burst signal and outputs an oscillation output.

Further, the discrimination cuff 01 of the line discrimination circuit 700 is also applied to the control input of the phase inverter 23. That is,
The phase inverter 23 applies the output 80 of the PLL circuit 14 as it is to the modulator 24 when the control input is given an L level, and when the control input is given an H level, the output 80 of the PLL circuit 80 is sent directly to the modulator 24.
0 is phase inverted and applied to the modulator 24.

Therefore, the color difference signals E and -E are modulated with phase inversion for each line.

The modulated outputs 241 and 261 are added by an adder 25, and further added with a luminance signal EY by an adder 27, and then provided to a switch 38. Therefore, if the switching signal 150 is set to H level only during the period when characters are added,
You can superimpose colors. As described above, color superimposition can also be performed in the PAL system.

As explained in the NTSC system, there are cases where a burst signal cannot be obtained due to reasons such as no video signal being input. In this case, as in the case of the NTSC system,
Output 80 of PLL circuit 14 and timing generator 2
A burst signal and a synchronization signal may be generated based on the output of 85.

The circuit is similar to that of FIG. 1B. However, P.A.
In the L method, the phase of the burst signal must be changed by 90° for each line. Therefore, based on the output of the line discrimination circuit 700, the analog switch 160
, 162 is phase-shifted by 90° every other line. That is, a control signal is generated using a circuit as shown in FIG. 9B.

The switch 450 is switched line by line by the discrimination amount cuff 01 of the line discrimination circuit 700. As a result, P
The output of the LL circuit 14 passes through a phase shifter 21 every other line and is phase-shifted by 90°. Therefore, analog switch 1
The control signals to 60 and 162 are shifted by 90 degrees every other line.

Some Embodiments - In each of the above embodiments, a character signal is used as an additional signal for superimposing, but other signals such as a picture signal may also be used. Further, as the color difference signal, a so-called E signal or E0 signal may be used.

In the above embodiment, explanation has been given for the time of playback, but the remaining amount of tape and battery capacity can also be superimposed in color on the monitor (or finder of a video camera) during recording. For example, when the remaining amount of tape is low, a warning color of red can be used to draw attention.

Furthermore, information that needs to be recorded, such as a title or date, can be recorded as a color superimposed image by recording the superimposed signal.

[Effects of the Invention] The superimpose circuit according to the present invention includes an oscillation circuit that oscillates a color subcarrier that is phase-locked with a burst signal of a video signal, and uses this oscillation output to generate a color difference signal of an additional signal such as a character. I'm trying to modulate it. Therefore, superimposition with a desired color can be performed.

[Brief explanation of the drawing]

FIG. 1A is a diagram showing an NTSC system superimpose circuit according to an embodiment of the present invention, FIG. 1B is a diagram showing details of the burst signal/synchronization signal generation circuit 36, and FIG. FIG. 2 is a diagram showing the output waveform of the synchronization signal generation circuit 36, FIG. 2 is a diagram showing details of the timing generator 28, FIG. 3 is a timing chart for explaining the operation of the timing generator 28, and FIG. 4 is a burst gate. The circuit diagrams, Fig. 5 (A to C) are waveform diagrams showing the operation of the burst gate, Fig. 6 is a circuit diagram showing the modulator, and Fig. 7 (A to D) are the circuit diagrams of Fig. 1 A. A waveform diagram showing the operation; FIG. 8 is a diagram showing an NTSC system superimpose circuit according to another embodiment; FIG. 9A is a diagram showing a PAL system superimpose circuit according to one embodiment;
FIG. 9B is a diagram showing some details of the /first signal/synchronization signal generation circuit 365, FIG. 10 (A and B) is a diagram showing the characteristics of the PAL system signal, and FIG. 12 is a diagram showing details of the timing generator 281 for PAL system, and FIG. 13 is a diagram showing the details of the timing generator 281 for the PAL system, and FIG. 13 is a diagram showing the details of the timing generator 281 for the PAL system. Phase inverter 24.26...Modulator 38...Switching circuit Condolence diagram? l'SY! 10 Fig. 4 Fig. 8 syn. Figure 7 Hsym. A Figure 10 E, -E. ■ Line n E, -E. ↑ Funeral map number 1

Claims (3)

[Claims] (1) A superimpose circuit used in the NTSC system, which receives an additional signal and generates at least first and second additional color difference signals, and is phase-locked to the burst signal of the video signal. An oscillation circuit that oscillates a color subcarrier, a modulation circuit that modulates the first and second additional color difference signals using the output of the oscillation circuit, and a switch that switches between the modulated first and second additional color difference signals and the reproduced video signal. circuit, a superimposed circuit with . (2) A superimpose circuit used in the PAL system, which receives an additional signal and generates at least a first and second additional color difference signal, which is phase-locked to the burst signal of the video signal. an oscillation circuit that oscillates a color subcarrier; a line discrimination circuit that discriminates and outputs the positive inversion of the phase of the burst signal of the video signal for each line; and a first circuit that modulates the first additional color difference signal using the output of the oscillation circuit. a modulation circuit; a second modulation circuit that inverts the phase of the output of the oscillation circuit line by line based on the output of the line discrimination circuit and modulates the second additional color difference signal; a modulated first and second additional color difference signal; A superimpose circuit equipped with a switching circuit that switches between a signal and a playback video signal. (3) Generate an additional color difference signal of the additional signal, generate a color subcarrier phase-locked to the burst signal of the video signal, modulate the additional color difference signal based on the color subcarrier, and generate the modulated additional color difference signal. A superimpose circuit characterized in that the circuit switches between the video signal and the playback video signal.