JPH02222072A - Multi-layer simultaneous wiring system - Google Patents

Abstract

PURPOSE:To improve the wiring accuracy by preparing a wiring layer including >=3 layers having different pattern running directions and performing the calculation of the congestion degree of each layer, the calculation of the using score of each layer, and the production of a wiring pattern respectively for each wiring subject section. CONSTITUTION:A wiring pattern is automatically decided based on the limit information on the wiring as well as a wiring subject section including of the start and target points of a circuit consisting of a multi-layer wiring layer containing plural wiring layers of different pattern running directions. In this case, the coordinates of the start and target points of a wiring pattern forming a wiring subject section and the wiring limit conditions are read out of a design information file 22 and inputted to a computer 21 in a wiring subject section extracting step S1. The congestion degree of each layer is calculated in a congestion degree calculating step S2, and the using score is calculated for each layer in a score calculating step S3. Then a wiring pattern is produced in a wiring pattern producing step S4 and then a wiring pattern is decided S5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for automatically determining wiring information of wiring patterns of multilayer printed circuit boards, multilayer integrated circuits, etc.
The present invention relates to a multilayer simultaneous wiring method suitable for use in determining patterns requiring the shortest wiring, patterns with severe wiring length restrictions, etc.

[Prior Art] Conventionally, multilayer printed circuit boards, multilayer integrated circuits, etc.
It is manufactured by a method in which wiring layers with patterns running in two directions, the axis and the Y-axis, are made into a pair of layers, and after forming a wiring pattern using this pair, the multiple pair layers are laminated with an insulating layer sandwiched between them. was.

This type of conventional technology will be explained below with reference to the drawings.

FIG. 18 is a diagram showing an example of the configuration of a wiring layer of a printed circuit board according to the prior art, and FIG. 19 is a diagram showing an example of the wiring pattern. In FIGS. 18 and 19, 1 is a layer in the X-axis direction, 2 is a layer in the y-axis direction, 3 is an insulating layer, 4 is an obstacle on the substrate, 5 is a pattern starting point, and 6 is a pattern destination point.

As shown in FIG. 18, the printed circuit board according to the prior art has an X-axis direction layer 1. The two wiring layers of the y-axis direction layer 2 are made into a pair, and after the required wiring is performed on this pair of layers, a plurality of paired layers are laminated with the insulating layer 3 interposed therebetween.

When performing automatic wiring on a board configured in this way, the basic idea of the algorithm used in -C is to draw a wiring pattern on a plane using two directions: the y-axis and the Y-axis. It's about exploring. The pattern example shown in FIG. 19 is an example where there is an obstacle 4 on the board that cannot pass the wiring, and from the pattern starting point 5 and the pattern destination point 6, the generated wiring pattern is
It is created by stretching the wiring pattern. In this case, if there is an obstacle 4 on the board as shown in FIG. 19, patterns are successively generated by changing the wiring layer of the wiring pattern and changing the running direction of the pattern.

On the other hand, printed circuit boards, integrated circuits, etc. are becoming larger and more densely packaged year by year, and multi-layering is becoming more and more effective. Furthermore, as the scale increases, consideration of wiring delay has become an important issue, and it is essential to deal with this problem by using the shortest wiring using diagonal wiring patterns.

As a conventional technique for generating wiring patterns using pair layers using such diagonal wiring pattern layers, for example, Japanese Patent Laid-Open No. 58
A technique described in Japanese Patent No.-56500 and the like is known.

FIG. 20 is a diagram explaining layer selection according to this prior art, FIG. 21 is a diagram explaining relay point selection, and FIGS. 22 and 23.
The figure shows an example of the wiring pattern. In FIGS. 21 to 23, 7 is a relay point candidate, 8 is a wiring pattern, and other symbols are the same as in FIG. 19.

In this conventional technique, first, one layer or a combination of two layers is determined based on the angle formed by the line segment connecting the wiring target sections with the y-axis. For example, the wiring direction is Δ that is tilted clockwise by 45 degrees from the
If the χX-axis direction and the ΔγX-axis direction can be used, two wiring layers in these directions are selected as a pair. Second
In the examples shown in FIGS. 0 to 22, the ΔγX-axis direction and the X-axis direction are selected.

Next, depending on the shape of the wiring target section, multiple relay point candidates 7 are selected.
Select.

Finally, the shortest possible pattern among the plurality of wiring patterns set using the selected relay point candidates 7 is determined.

In the wiring method according to the prior art described above, the wiring direction of the wiring layer is limited in advance before wiring pattern exploration, so, for example, as shown in FIG. If there is an obstacle 4 near the section, it is necessary to use a pattern with a determined wiring direction, which may cause the wiring pattern 8 to take a detour, resulting in an increase in the wiring length. In this example, if a pattern in the y-axis direction can also be used, as shown in FIG.
Although it is possible to determine the wiring pattern 8 and avoid a detour of the wiring pattern, it is impossible to avoid such a detour of the wiring pattern in the conventional technique.

[Problems to be Solved by the Invention] The above-mentioned conventional technology that uses wiring layers only in the The problem is that it is difficult to reduce the delay.

In addition, the conventional technology described in the above publication can use diagonal wiring direction layers and can reduce wiring delay, but since the direction of the wiring layers is determined in advance, obstacles such as In some cases, there is a problem in that the pattern may be detoured and the wiring delay may be increased. Furthermore, in this conventional technology, when determining the wiring layer, in order to select the optimal pair layer for the wiring target section, it is necessary to select from all types of combinations depending on the pattern running direction. With diversification, the total number of required distribution JT layers becomes enormous, and there is a problem that selection becomes difficult. Furthermore, since there are variations in the slope of the pattern direction in the wiring target section, the degree of congestion of the wiring pattern on each bare layer is uneven, which is inefficient and makes it impossible to increase the connection rate beyond a certain level. There are problems.

The purpose of the present invention is to solve the problems of the prior art described above, and to diversify the shapes of wiring patterns that can be created through wiring processing using multiple wiring layers, thereby enabling high connection efficiency and shortest wiring, It is possible to improve the wiring length accuracy of the wiring section with a fixed wiring length, and when determining the wiring pattern,
An object of the present invention is to provide a multilayer simultaneous wiring system that makes it possible to average the congestion degree of each layer by considering the congestion degree of each wiring layer.

[Means to solve the problem]

According to the present invention, the above object is to form the wiring layer into three or more wiring layers having different pattern running directions, and to perform the following processes [)) to (4) in this order for each wiring target section. This is achieved by determining the wiring pattern using

(1) Congestion degree calculation for each layer For each layer, (a) Extract the existing wiring pattern from the already determined wiring information file and calculate its pattern length. (b) The size of the usable wiring area, the maximum number of usable channels (the number of patterns that can be created between wiring grids), and the running direction of the pattern are extracted from the board information file, and the length of the pattern that can be created is calculated. (C) Calculate the degree of congestion by layer from the above-mentioned wiring pattern length and createable pattern length.

(2) Calculate score for each layer From the design information file, calculate the angle of the line segment connecting the starting point and destination point of the wiring target section, extract the constraint conditions regarding the wiring length of the wiring target section, and use them based on these. A priority order is determined for each of the possible pattern running directions, and a usage score is calculated for each usable wiring layer based on this priority order, the layer-based congestion degree, and the pattern direction of each wiring layer.

(3) Wiring pattern generation A wiring pattern is created on a lattice point (pattern creation possible point) from the starting point of the relevant wiring target section, where wiring patterns can be created in all directions (pattern creation possible points), and the tip thereof is set as a trial end point. next,
The wiring pattern from this trial end point to the next trial end point is created in the same manner as described above, and is repeated until the trial end point reaches the target point.

As a result, a plurality of wiring pattern candidates are generated. Note that the running direction of the generated wiring pattern candidates is the plane direction 9 consisting of the X-axis direction, y-axis direction, ΔχX-axis direction, ΔyX-axis direction, and the distance between the wiring layers for these plane-direction patterns. A vertical direction 10 is used to connect the . As a result, it is possible to generate a wiring pattern candidate having multiple wiring layers.

(4) Wiring pattern determination When generating wiring pattern candidates as described above, the wiring length of each wiring pattern candidate, the running direction of each wiring pattern candidate with respect to the wiring target section, V, H, (ViaIIo Ie
: When the wiring pattern changes layers, the trial score at each trial end point is calculated based on the necessity of a via hole (created to connect between the eyebrows) and the usage score for each layer determined above. Next, for each wiring pattern candidate, the trial scores at all the trial end points are totaled to obtain the score of each wiring pattern candidate, and the optimum wiring pattern is determined based on the magnitude of the score. However, for a wiring target section for which a wiring pattern length is specified, the wiring pattern candidate with the length closest to the specified length is determined as the optimal wiring pattern.

FIG. 17 is a diagram showing an example of the wiring pattern candidates determined in this way.

It is.

In FIG. 17, a1 to a6 are the trial scores at each trial end point, and the wiring pattern candidates in this example [effect] The determination of the wiring pattern according to the present invention is based on the length of the existing wiring pattern for each wiring target section. Since the degree of congestion for each layer is calculated and the wiring pattern is determined in consideration of this, the usage rate of each layer can be controlled in detail. In addition, when creating a wiring pattern, in order to simultaneously create a wiring pattern for multiple layers, it is possible to generate a variety of wiring pattern candidates by considering all available patterns in the running direction for the starting point and each trial end point. This makes it possible to improve the wire connection efficiency. Furthermore, when determining the wiring pattern,
The optimal one can be selected from a variety of wiring pattern candidates according to the length and detour of the existing wiring pattern in the target wiring section, and high-precision wiring can be achieved with the shortest wiring or with the specified wiring length. You can get results.

〔Example〕

Hereinafter, one embodiment of the multilayer simultaneous wiring system according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart explaining processing in an embodiment of the present invention, FIG. 2 is a hardware configuration diagram of an embodiment of the present invention, and FIG. 3 is an arrangement diagram of an embodiment of the present invention. A diagram showing the configuration of 1IAN, FIG. 4 is a diagram explaining the length of the existing wiring pattern,
Figure 5 is a diagram explaining the calculation of scores for each layer according to the degree of congestion,
FIG. 6 is a diagram showing an example of a wiring pattern for explaining score calculation, FIGS. 7(a) and (b) are perspective views showing examples of wiring pattern candidates, and FIG. 8 is a plan view showing an example of wiring pattern candidates. , Figures 9 to 11 are diagrams showing examples of wiring patterns by specifying wiring lengths, Figures 12 and 13 are diagrams showing examples of wiring patterns to explain the wiring pattern score calculation method, and Figure 14 is a diagram showing examples of wiring patterns by specifying the wiring length. FIG. 15 is a diagram illustrating the relationship between parameters used for calculation and scores, and is a diagram showing an example of scores for wiring pattern candidates. In Figures 2 to 4 and 6 to 13, 2
1 is a computer, 22 is a design information file, 23 is a basic information file, 24 is a wiring information file, 25 to 28
are each wiring layer by direction, and other symbols are shown in FIGS. 18 to 2.
This is the same as in Figure 3.

As shown in FIG. 2, one embodiment of the present invention includes a computer 21 that performs automatic wiring processing, a design information file 22 containing the coordinates of a wiring target section, constraints on wiring of the wiring section, etc., and a wiring pattern. The wiring information file 23 includes a board information file 23 that holds information about the board on which the board is printed, and a wiring information file 24 that holds wiring pattern information determined by automatic wiring processing.

An embodiment of the present invention configured as described above includes wiring target section extraction S1, congestion degree calculation for each layer S2, score/point calculation for each layer, and wiring pattern candidate generation S4, as shown in FIG. The wiring pattern is determined by sequentially executing six processing steps: , wiring pattern determination S5, and wiring pattern writing S6.

The wiring processing for the normal wiring section and the shortest wiring section will be explained below regarding the processing for each stage. In the embodiment of the present invention described below, it is assumed that the optimal wiring pattern is a pattern with the minimum score. Furthermore, as shown in FIG. 3, the layer structure of an embodiment of the present invention includes a layer in the X-axis direction (layer A), a layer in the y-axis direction (layer B), and a layer in the 45° direction with respect to the X-axis (layer A).
0 layer), 135° direction layer (DJi), and 4N wiring layers.

It is assumed that the wiring patterns on each wiring layer can be connected to each other by freely providing the wiring patterns.

Step ■: Extracting the wiring target section (Step Sl) From the design information file 22, the coordinates of the starting point and destination point of the wiring pattern that constitutes the wiring target section, and the constraint conditions (wiring pattern length, wiring pattern shape, etc.) and input it to the computer 21.

Step 2: Calculating the degree of congestion for each layer (step S2) The computer 21 calculates the degree of congestion for each layer using the following formula.

Wiring pattern length =, r7 - completed r1 - r71 - However, l = number of grids in the X direction of the existing wiring pattern ! y=the number of grids in the y direction of the existing wiring pattern.

In other words, the length of the existing wiring pattern is as shown in FIG.
Based on the position of the starting point 5 and the position of the destination point 6 of the pattern, the linear distance of repositioning is determined in units of lattice point distance.

Examples of patterns that can be created in length (maximum number of patterns) - (number of lattices in the non-wiring area on the board) (2) For 45° layer and 135° layer L = (number of lattices in the X-axis direction of the board) × (y-axis of the board) (number of directional grids) × (maximum number of patterns that can be created between grids) XI/,
I'T - (Number of grids in the non-routable area on the board) Step m: Calculate the score for each layer (Step 33) (a) Based on the congestion degree for each layer obtained above, calculate the usability index for each layer. Determine the score. For example, if the degree of congestion of wiring in each layer has a value as shown in FIG. 5, points are given according to each degree of congestion. This score is determined so that the total score for each layer is 100 points, and the above-mentioned congestion degree value and the ratio between layers do not change.

(b) Based on the shape of the wiring target section and the constraint conditions at the time of wiring, the scores for each layer described above are corrected, and usage scores for each layer are calculated. The usage scores for each layer will be explained using an example of the wiring pattern shown in FIG. The wiring target section of the wiring pattern 8 shown in FIG. 6 is between the starting point 5 and the destination point 6, and in this case, the two wirings of the X-axis direction layer (A layer) and the 45° direction layer (B layer) The wiring pattern 8 using layers is the shortest.

Therefore, for the normal wiring section, the X-axis direction layer (A layer)
To make it easier to use the 45° direction layer (CI), for example, subtract 5 from the score based on the congestion degree of the A layer and 0 layer, which are the corresponding layers in Figure 5, and use this as the layer for normal wiring. Separate usage score.Also, 135° direction layer (D layer)
is in the opposite direction to the wiring target section in FIG. 6, so in order to make it easier to use the Y-axis direction layer (B layer) than this layer, for example, the congestion degree of the Y-axis direction Jl (B layer) in FIG. Subtract 3 from the score and calculate this as B for normal wiring.
This is the usage score for each layer, that is, the layer in the Y-axis direction. As a result, the stratified usage score for the normal wiring section is determined as shown in FIG. 5, taking into account the congestion degree of each layer and the shortest wiring according to the angle between the starting point 5 and the destination point 6 of the wiring target section. Also,
For the shortest wiring specified section, it is necessary to emphasize the shortest route rather than the degree of layer congestion, so ignore the degree of layer congestion and make the X-axis direction layer 25.45° direction layer easier to use, for example. , determine the usage score as shown in Figure 5.

Stage ■: Wiring pattern candidate generation (step S4) Now,
It is assumed that a pattern is generated between a starting point 5 and a destination point 6 located at positions as shown in FIG.

In this case, from the starting point 5 to the destination point 6, avoiding the obstacle 4,
Generate wiring pattern candidates in all directions. In FIGS. 7 and 8, RX r R4S+ R12S+ Ry is
Examples of wiring pattern candidates are shown in FIG. 7(a), a perspective view of wiring pattern candidates R,,R,, with interlayer wiring, and FIG.
A perspective view of Y interlayer wiring is shown.

The wiring pattern candidate RX is a pattern generated in the X-axis direction from the starting point 5.
Stretch axial pattern, V, H.

11 and move it to the B layer to generate a pattern in the y-axis direction, and further, in order to make the shortest connection to the destination point, V,)
, 11 to the D layer and directly connected to the target point 6 using a 135° direction pattern.

The wiring pattern candidate RAS is the shortest pattern, and since it is not possible to generate a pattern directly in the 45° direction from the starting point 5 due to the obstacle 4, a pattern in the y-axis direction is generated to avoid the obstacle 4. This is the shortest possible time.

Wiring pattern candidate RI3. is the shortest pattern when a pattern is generated in a direction of 135° from the starting point 5.

Further, the wiring pattern candidate R is the shortest pattern when only the X-axis direction layer and the Y-axis direction layer having low layer-wise usage scores in the normal wiring section are used.

Next, wiring is performed with the pattern length determined by the design information file 2. Examples of wiring with specified wiring length are shown in Figure 9~
This will be explained with reference to FIG.

FIG. 9 is an example of wiring between the starting point 5 and the destination point 6 with a specified length of 11 grids on layers in the X-axis direction and the y-axis direction. However, if an obstacle 4 exists near the destination point 6, the wiring pattern using only the X-axis direction layer and the y-axis direction layer is
0 Wiring pattern as shown in figure! , a two-lattice detour occurs. - In this case, if you use a diagonal pattern, like wiring pattern 2□ in Figure 11,
By shortening the wiring length, it is possible to improve accuracy with respect to a specified pattern length.

Stage V: Wiring pattern determination (Step 55) (1) Calculation of wiring pattern score Shortest wiring pattern R4S explained with FIGS. 7 and 8
A method of calculating wiring pattern scores during normal wiring will be explained with reference to FIG.

At the first trial end point α between the starting point 5 and the destination point 6, from the starting point 5 to the trial end point α, the number of grids is 1 in the vector approaching the destination point, and V, H.

11 is not used, the vector score f=5, V, )(, score V=O according to FIG. 14).

Also, since the wiring layer used is layer B, which is the layer in the y-axis direction,
From Figure 5, the layer score is 10. Similarly, the trial endpoint β
From the trial end point α to the trial end point β, the number of grids is 2 in the vector approaching the target point, and at the trial end point α
- V, H, 11 are used between the C layers, and 4 is used as the wiring layer.
Since we use the 0 layer, which is the 5° direction layer, Fig. 14, 5
From the figure, the vector score f=10. ．． V, H, score V = 2
, L=32 can be obtained. Similarly, objective point 6
At the trial end point γ, which has reached the trial end point β, V, H, and 11 are used between the C and A layers at the trial end point β, and the A layer, which is the layer in the X-axis direction, is used as the wiring layer, so as shown in FIG. From Figure 5, vector scores! =10, ■.

Go to ■■, score V=2X2=4, L=14 can be obtained. The sum of all these scores is the wiring pattern score for the operating wiring of wiring pattern R45, and the value is 87.

Similarly, by using FIG. 14 and FIG. 5, the wiring pattern score at the time of the shortest designated wiring of the wiring pattern RJS can be determined. In this case, each score at each trial end point is shown in FIG.

As described above, the wiring pattern score for each wiring pattern candidate can be obtained, and the wiring pattern score for each wiring pattern candidate explained using FIGS. 7 and 8 is as shown in FIG. .

(2) Wiring pattern determination In one embodiment of the present invention, the one with the minimum wiring pattern score is taken as the optimal solution. Therefore, during normal wiring, the wiring pattern candidate Ry is determined based on the scores shown in FIG. At the time of designated wiring, the wiring pattern candidate R4S is similarly selected and determined as the wiring pattern.

As mentioned above, even for the same wiring section, the
Based on FIG. 4, during film wiring, a wiring pattern using layers in the X-axis direction and Y-axis direction, which have a small degree of congestion, is selected, and the degree of congestion can be averaged. When specifying the shortest wiring, the shortest wiring pattern is selected regardless of the degree of congestion of the wiring layer.

Step (2): Storing the wiring pattern (step 36) Information about the wiring pattern selected in step V (coordinates, wiring eyebrows, etc.) is stored in the wiring information file 24. With the above, the processing for the - wiring target section is completed.

According to the embodiment of the present invention described above, in a normal wiring section, various wiring pattern candidates for all layers are automatically generated in consideration of the degree of congestion in each wiring layer due to the determined wiring pattern. , it becomes possible to automatically determine the optimal wiring pattern for the wiring target section from among them. In addition, in the shortest wiring specified section, by considering all wiring layers when generating a wiring pattern, it becomes possible to automatically determine the shortest wiring backcoup that can be generated. Furthermore, according to an embodiment of the present invention, in a section where the wiring length is specified in advance, all wiring layers are taken into consideration when generating the wiring pattern, thereby flexibly responding to wiring pattern detours, etc. , it becomes possible to automatically determine a wiring pattern with high wiring length accuracy.

One embodiment of the present invention described above relates to the creation of a wiring pattern on a board having four wiring layers, but the present invention is applicable to the creation of a wiring pattern on a board having four wiring layers. is arbitrary and can be applied to creating wiring patterns for printed circuit boards, LSIs, etc.

〔Effect of the invention〕

As explained above, according to the present invention, when creating a wiring pattern, it is possible to take into account all the wiring layers that constitute a printed circuit board, LSI, etc. It becomes possible to select a suitable wiring pattern, and by considering the degree of congestion of each wiring layer due to the existing wiring back-up when determining the wiring pattern, it is possible to control the usage rate of each wiring layer in more detail. As a result, the present invention can improve accuracy during wiring with a high connection rate, shortest wiring length, and specified wiring length.

[Brief explanation of the drawing]

Fig. 1 is a flowchart explaining processing in an embodiment of the present invention, Fig. 2 is a hardware configuration diagram of an embodiment of the invention, and Fig. 3 shows the configuration of a wiring layer in an embodiment of the invention. Figure 4 is a diagram for explaining the length of existing wiring patterns, Figure 5 is a diagram for explaining score calculation for each layer according to the degree of congestion, and Figure 6 is a diagram for explaining wiring pattern examples to explain score calculation. ,
7(a) and 7(b) are perspective views showing examples of wiring pattern candidates, FIG. 8 is a plan view showing examples of wiring pattern candidates, and FIG.
figure. Figures 10 and 11 are diagrams showing examples of wiring patterns by specifying wiring lengths, Figures 12 and 13 are diagrams showing examples of wiring patterns to explain the wiring pattern score calculation method, and Figure 14 is a diagram showing examples of wiring patterns by specifying the wiring length. Figure 15 is a diagram illustrating the relationship between parameters used in the process and scores;
FIG. 16 is a diagram explaining the pattern running direction, FIG. 17 is a diagram showing an example of a wiring pattern candidate, FIG. 18 is a diagram showing an example of the layer structure of a printed circuit board according to the prior art, and FIG. 19 is an example of the wiring pattern. 20 is a diagram illustrating layer selection according to the prior art, FIG. 21 is a diagram illustrating selection of relay points, and FIGS. 22 and 23 are diagrams illustrating examples of wiring patterns. 1-------- layer in the x-axis direction, 2-- layer in the y-axis direction, 3-- insulating layer, 4--- one obstacle, 5--
...Starting point, 6・--1---- Destination point, 7・-・-
Relay point candidate, 8-------One wiring pattern, 9・-
--- Planar direction, 10 --- - Vertical direction, 11
・・・・・・・V, H, 21・・−・−Computer, 22・・・・・・・−Design information file, 23−−
---1. Board information file, 24. --- Wiring information file. Figure 1 Figure Figure Figure 56 μ 6° Auto\JL Figure Figure Figure Figure Figure Figure Figure Figure 1゜Figure Figure Figure Figure Shelf = 87 '! +=44 Figure Figure Figure 2o Figure 4t Prefecture 22 Figure 8 Sakibutton Pattern Figure Figure 18 Figure 19 Figure 21 Figure 23

Claims (2)

[Claims] 1. In a wiring method that automatically determines a wiring pattern based on a wiring target section consisting of a starting point and a destination point and constraint information at the time of wiring of a circuit using a multilayer wiring layer having a plurality of wiring layers having different pattern running directions, the wiring Determining the priority of each wiring layer having a usable pattern running direction in the multilayer wiring layer based on the angle of the line segment connecting the starting point and the destination point of the target section and the constraint conditions regarding the wiring length of the wiring target section. and a function of determining the usage score of each of the usable wiring layers based on the priority order and the pattern running direction, and determining the route of the wiring pattern that advances on a plane between the starting point and the destination point of the wiring target section. A function of performing exploration and layer change exploration of interlayer via holes perpendicular to a plane connecting multiple wiring layers, and generating a plurality of wiring pattern candidates having three or more layers as wiring layers, and A function that determines the score for each wiring layer based on the usage score of each wiring layer used, the length of the wiring pattern, and the presence or absence of via holes between layers, and then determines the optimal wiring pattern based on the scores of each pattern candidate. A multilayer simultaneous wiring method characterized by comprising: 2. For each of the wiring layers, the function further includes a function of determining the ratio of the length of the existing wiring pattern to the allowable length of the new wiring pattern and calculating a degree of congestion for each wiring layer, and a function of determining the usage score of the wiring layer. Claim 1, characterized in that the usage score of the wiring layer is determined by adding the congestion degree of
Multi-layer simultaneous wiring method described in section.