JPH02218214A - Pseudo-random noise code generator - Google Patents

Abstract

PURPOSE:To allocate code data as a channel number as they are by providing a second shiftregister, for which second pattern data different from first code pattern data are inputted, the initial state of a shiftregister in a prescribed step is fixed and the initial state of the other shiftregister can be changed. CONSTITUTION:In an MSRG 1, MSRG 2 and MSRG 3, two kinds of m-sequence codes can be obtained by supplying the different code pattern data to a PTN 1 and PTN 2. Since the same code pattern data are supplied to the MSRG 2 and MSRG 3, the same kind of the m-sequence code can be obtained. However, concerning the initial state, an n-1 bit is made common for B2-Bn terminals. Then, since 1 bit of a remained B1 terminal is fixed to an 'H' level in the MSRG 2 and fixed an 'L' level in the MSRG 3, the code of a different phase is obtained. Accordingly, in an E1 and E2, the GOLD code of a different pattern is generated without fail.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to pseudo-random noise used in applications requiring code division multiplexed signals such as spread spectrum communication (hereinafter abbreviated as SSC). Regarding code generators.

[Summary of the invention] In an m-sequence code generator having a simple shift register and a modular shift register configuration, three m-series code generators are used, one m-sequence code generator generates code 1, and the other two Codes with the same pattern but different phases y 1
, Y 2 , 1 and Vl and l and v2
to generate two different GOLD codes.

Furthermore, in the two m-sequence code generators that generate the codes v1 and v2, n-1 bits out of the n-bit initial states can be commonly set from the outside,
The remaining 1 bit is fixed to a different state on both sides, and n
- Obtain a pair of GOLD codes with different patterns that do not overlap each other for 1-bit code data.

[Prior Art] In applications that require code division multiplexed signals such as SSC, a pseudorandom noise code generator (hereinafter referred to as a code generator in this specification) is required to have a changeable output code pattern. is required. Conventionally, a circuit configuration as shown in FIG. 5 has been used as a code generator capable of generating an arbitrary m-sequence code by external control of the code period, code pattern, and code phase.

In FIG. 5, SR1 to SRm-1 and SRr are flip-flops, E1 to E, and n are exclusive OR gates, and both constitute a so-called modular shift register. Furthermore, MUX 1 is a multiplexer that controls the number of stages of the modular shift register;
AN is an AND gate that specifies whether or not a signal is fed back from the final stage output of the modular shift register to each stage, and DS.

~DS, is a data select circuit that sets the initial value of the modular shift register. That is, data 01 to CI are used to specify the address of MUXI, the number of stages of the modular shift register is determined, and the code period is determined, and data 82 to al are used to feed back signals from the final stage of the modular shift register to each stage. Determine the state, code pattern, and data b1~
The initial value of the modular shift register can be determined by b and n, and the phase of the code can be controlled independently.
It is possible to generate any m-sequence code. Three pieces of code data necessary for controlling this code are input in a time-division manner from common data lines DAT 1 to n in order to reduce the number of input terminals. LAT 1.

LAT3 and LAT4 are code pattern data C2~am and code phase data b, respectively.

It is a latch circuit for inputting and holding ~bn and code period data C1~C□, and DECl
is a decoder circuit that uses 2-bit signals of 5ELO, SET, and 1 to select a latch circuit for writing data. Since the output of the decoder circuit becomes active only when the latch enable signal LE is at the rHJ level, the timing of writing data to the latch circuit can be controlled by the latch enable signal. After setting the code data, output of a new code is started by the STB signal, but to prevent the code from switching while setting the code data, LAT2 and LA
By T5, the code pattern data and code period data are held in the double structure latch circuit. In addition, CLK
is a clock signal output terminal, and C0DE is a code output terminal.

By the way, in code division multiplex communication, for reasons of signal secrecy, prevention of interference, and multichannelization, GOLD codes, which have far more patterns of same-period codes than m-sequence codes, are often used.

The GOLD code is a code obtained by adding multiple m-sequence codes with the same period and different patterns using mod, 2, but it can be obtained by adding (2″1-1) m-sequence code generators with n film configuration from r pieces. It is known that (r-1) types of patterns can be obtained.Using a conventional code generator, G
FIG. 6 shows an example of a circuit configuration for obtaining an OLD code. In FIG. 6, PNGI and PNG2 are code generators having the configuration shown in FIG. 5, El is a mod, an exclusive OR gate for performing addition of 2, and FFI is
From the difference between the delay time of PNGI and PH10 E
This is a flip-flop provided to remove the hazard that occurs in l and obtain a code output synchronized with the clock. By changing the mutual phase difference from two m-sequence codes with a period of 2ffl-1, 21-1 types of GOLD codes can be obtained, but in the circuit shown in Fig. 6, by changing the pattern of the m-sequence codes, even more Various types of GOLD codes can be obtained.

[Problems to be Solved by the Invention] In the field of code division multiplex communication such as SSC, code patterns with the same period are much more common than m-sequence codes for the reasons of signal secrecy, interference prevention, and multichannelization.
It is advantageous to use LD codes. Conventionally, as a code generator whose code can be externally controlled, for example, Patent Application 2 "Pseudorandom Noise Code Generator" filed by the present applicant on the same date
The configuration shown in FIG. 2 is considered.

FIG. 3 shows a specific example of MSRG.

The feature of this method is that the period and pattern of the two m-sequence codes are fixed, and only the phase difference between the two codes is changed to generate various patterns. Therefore, the code control data is used by the code generator. The initial state is 1 to 2''-1 (decimal system), and by assigning the code data to the channel number as is, there is an advantage that microcomputer control or complicated driver circuits are not required for code setting.

Now, based on this configuration, code shift keying (
Let us consider the configuration of a code generator that is compatible with Code 5ift Keying (hereinafter abbreviated as C8K in this specification). C8K is a communication method in which two types of codes correspond to the information If OI+ and 11'''. Therefore, in order to make C8K possible, it is necessary to be able to generate two types of GOLD codes at the same time. Conventionally, as a method for simultaneously generating multiple GOLD codes from one m-sequence code generator, there is a method described in Japanese Patent Application No. 1983-200825, which was proposed by the present applicant on August 10, 1988. In other words, in addition to the code output from the m-sequence code generator, this is input to a flip-flop to obtain a code whose phase is delayed, and these and the code outputs from other m-sequence code generators are input. This is a method of obtaining GOLD codes with different patterns based on the GOLD code. Fig. 4 shows an example of the configuration of a C8K code generator using this method.

In FIG. 4, MSRG 1 and MSRG2 are n
The membrane-configured modular shift register circuits El and E2 add two m-sequence codes mod, 2,
an exclusive OR gate for generating the GOLD code;
FFI, FF2 and FF3 are flip-flops, P, for removing hazards occurring in the exclusive OR gate and outputting codes in synchronization with the clock signal.
TN]- and PTN2 are memory circuits that store code pattern data specifying the feedback connection methods of MSRGI and MSRG2, respectively, and LAT 1 is a
This is a latch circuit that inputs code phase data specifying the initial state of SRG2 from the outside and holds it. Also, DSL
selects one of the outputs of El or E2, and FF
The data select circuit that outputs to 3, DS2 is
When the output of the code is started by the STB signal, F
This is a data select circuit that gives an initial value to F4.

Further, FF4 is a flip-flop for obtaining a code output delayed by one chip phase with respect to the code output from the SIn terminal of MSRG2.

For explanation of operation, MSRGI and MSRG2
The m-sequence codes obtained from the CO terminal of are represented by {circle around (2)} and ■ (■), respectively, using vectors, and the state transition matrix is represented by T.

Since the SIn terminals of MSRGI and MSRG2 are the input signals to the final stage flip-flop of the modular shift register (that is, the flip-flop whose output is connected to the C○ terminal), the sign obtained from the SIn terminal is , respectively ↓, TtI and Ty which are one chip phase ahead of V. Therefore El
The output of is 1゛renΦTtr, the output of FF4 is y, E
The output of 2 is TLteV, and GOLDI and GOLD whose phase is delayed by 1 chip by the flip-flop.
It can be seen that GOLD codes with different patterns of additional ΦV and ΦT −'v are obtained at the two terminals, respectively. Also, from the C and SK terminals for C8K output,
Depending on the state of C3KI signal 1ΦV or u
The code of teT-1-sz is output, and it can be seen that C8K is possible.

By the way, in this method, MS R is controlled by external control.
Since the phase of the G 2 code can be changed, the two code pairs used in C8K can generally be expressed as ΦTI Lt and ΦT'−'UL. Here, 1
is any integer. Therefore, in order to avoid code overlap with other channels in C8K, it is necessary to satisfy, for example, the following condition.

i=2m (0≦m≦2”-1-1)・・
(1) where m is an integer. However, an m-sequence code generator with n stages is 1 to 2"-1
Since it can be regarded as a counting circuit that randomly counts (decimal) numbers, it is clear that simply giving an even number as an initial state cannot be used. In order to provide code phase data that satisfies the condition of equation (1), it is necessary to derive a state equation from the configuration of the code generator and analyze the initial state.

As described above, by applying the above method, it is possible to easily configure a code generator compatible with C8K, but in applying the above method, it becomes necessary to analyze the code data to be set, and the code generator shown in Fig. 2 This has the disadvantage that the advantage of being able to directly allocate the code data of the code generator to the channel number is lost.

[Object of the Invention] An object of the present invention is to provide a code generator for C8K that can allocate code data to a channel number as is.

[Means for Solving the Problems] In order to achieve the above object, a code generator according to the present invention includes a first shift register into which first code pattern data is input and whose initial state is fixed; Second code pattern data different from the first code pattern data is input, and the second shift register is configured such that the initial state of the shift register of a predetermined number of stages is fixed and other stages can be changed; 2 code pattern data is input, the initial state of the shift register of a predetermined number of stages is fixed, and the others are configured to be changeable, and codes with the same pattern and different phases are generated for the second shift register. a third shift register, the first shift register output and the second shift register output are mod, 2;
and means for adding the output of the first shift register and the output of the third shift register mod.2, and the gist thereof is to generate different GOLD codes.

[Operation] Since it is possible to use continuous code data from 1 to 21-1 as a code generator for C8K, there is no need for microcomputer control or a complicated driver circuit for code setting.

[Examples] The present invention will be explained in more detail below using Examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.

FIG. 1 shows an example of the configuration of a code generator according to the present invention. 1st
In the figure, MSRGI, MSRG2 and MSRG3
is a modular shift register circuit with an n-stage configuration, a specific example of which is shown in FIG. and M.S.R.
This is a latch circuit that externally inputs and holds n-1 bits of data out of the n-bit initial state of G3. Also, El and E2 are respectively MS RG
1 and MSRG2 sign output and MSRGI
and mod the code output of MSRG3.

Exclusive OR gate for addition by 2, FF1, FF
2 and FF3 are flip-flops provided to remove hazards occurring in the exclusive OR gate and obtain a code output synchronized with the clock signal;
SL is the GOLD code generated by El or E2
Select one of the GOLD codes generated by the FF according to the state of the C3KI signal applied from the outside.
This is a data selection circuit that outputs data to 3.

The operation of the above embodiment will be explained below.

In Figure 1, by giving different code pattern data to PTNI and PTN2, MSRGl
and MSRG2. Two types of m-sequence codes can be obtained in MSRG3. Also, MSRG2. MSRG3
Since the same code pattern data is given, the same type of m-sequence code is obtained, but regarding the initial state, B2 to Bn
The n-1 bits of the terminals are common, and the remaining 1 bit of the B1 terminal is fixed at the rHJ level in MSRG2 and at the rLJ level in MSRG3, resulting in codes with different phases. Therefore, GOLD codes with different patterns are always generated in El and E2. Also MSRG
Since the initial states of MSRG2.I are all fixed at "H" level, MSRG2. B2~Bn of MSRG3
If the initial state of n bits of is changed, a pair of non-overlapping GOLD codes with different patterns can be obtained.

The data that can be input from the n-1 bit data line of DATI-n-1 is O~2'n-1-1 (decimal).
There are 2M-1 pieces, of which o (decimal) is MSR
MS in order to set the initial state of G3 to all “L” level.
No m-sequence code output can be obtained from RG 3 . Therefore, the code data that can actually be used for C8K is 21-1 pieces from 1 to 21-''-1 (decimal).

By assigning code data from 1 to 21-1-1 (decimal) as is as a channel number, the user can eliminate the need for microcomputer control or complicated driver circuits.

In this specification, a code generator with a modular shift register configuration was taken as an example, but by changing the initial state, different types of GOLs can be generated.
The D code can be obtained in the same way in the case of a simple shift register configuration, and it goes without saying that the present invention is also applicable to a code generator having a simple shift register configuration.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a C8K code generator that can allocate code data as is as a channel number.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a pseudo-random noise code generator according to the present invention, FIG. 2 is a diagram showing the configuration of a GOLD code generator that can directly allocate code data to five channel numbers, and FIG. Figure 4 shows a circuit in which the circuit in Figure 2 is extended to support C8K, Figure 5 shows a conventional M4G,
FIG. 6 is a circuit diagram of a GOLD code generation circuit using a conventional pseudo-random noise code generator. Patent applicant Clarion Co., Ltd.

Claims (1)

[Claims] A first shift register into which first code pattern data is input and whose initial state is fixed, and second code pattern data different from the first code pattern data is input. At the same time, a second shift register is configured in which the initial state of the shift register of a predetermined number of stages is fixed and the others are changeable, and the second code pattern data is inputted,
The initial state of the shift register of a predetermined number of stages is fixed, and the others are configured to be changeable, and the third shift register generates codes having the same pattern and different phases with respect to the second shift register, and the first shift register The shift register output and the second shift register output are mod. A means of adding by 2,
Mod. the first shift register output and the third shift register output. and means for adding in 2 different GOs.
A pseudorandom noise code generator characterized in that it generates an LD code.