JPH0221774Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is used, for example, in a high-resolution frequency synthesizer that can generate any frequency, and relates to a phase accumulator that periodically generates a signal.In particular, this invention uses a large-capacity RAM that can be purchased at low cost as a frequency register. The frequency data can be switched instantly by simply selecting the address.

<Background of the invention> A phase accumulator is used, for example, in a high-resolution frequency synthesizer shown in FIG. This is shown in "Utility Model Application Publication No. 53-152552" and includes a reference frequency oscillator 11 and a phase comparator 13.
, a low-pass wave generator 14 , and a signal-controlled oscillator 15
, a signal canceling circuit 16, a frequency divider 17, and a phase accumulator 18.
2 to obtain an arbitrarily set frequency.
Here, the phase accumulator 18 operates the signal erasing circuit 16 at each set period to remove the signal output from the signal controlled oscillator 15.
The oscillation frequency of the reference frequency oscillator is r, the frequency divider 17
Assuming that the frequency division ratio is N, and the phase accumulator 18 generates B signals during A clock periods to operate the signal canceling circuit 16, the oscillation frequency o from the output terminal 12 is o=(N+B/ A) It is designed to generate a frequency that is an arbitrary multiple of the reference frequency.

Conventionally, the phase accumulator 18 shown in FIG. 2 has been used. This is setting device 21
It is composed of, for example, two 64-bit registers (phase register 22 and frequency register 23), and a 64-bit full adder 24. Here, the setting device 21
A certain value is written to the frequency register 23 through the full adder 24, and the value stored in the phase register 22 and the value stored in the frequency register 23 are added together. If the scale value is exceeded, a carry signal is output to the terminal 25, and the remainder is written into the phase register 22 again. That is, if the full scale value of the full adder 24 is A, and the value written in the frequency register 23 is B, then B signals out of A clocks are output. However, this case has the disadvantage that the longer the bit, the larger the hardware such as full adders and relays. Another drawback is that rewriting the contents of the frequency register 23 requires transferring 64-bit data from the setter 21, which takes time.

Therefore, it is also possible to provide two frequency registers so that when one is operating in the phase accumulator, the frequency data of the other can be rewritten from the setter at any time. However, for example, when changing the oscillation frequency of a frequency synthesizer continuously, while one frequency register is operating in the phase accumulator,
The process of transferring 64-bit data to the other frequency register must be repeated repeatedly.
The control is complex and there are limits to its switching speed.

<Purpose of the invention> This invention aims to provide a phase accumulator that can instantly switch output data using a large capacity RAM that can be purchased at low cost.

<Summary of the invention> The phase accumulator according to this invention uses a large-capacity RAM as a frequency register to store a large amount of data corresponding to the oscillation frequency of a frequency synthesizer, for example, and outputs it by simply selecting the address on the control side. This allows data to be changed quickly.

<Example of the invention> Fig. 3 shows an example of the invention. In the figure, the same parts as in FIG. 2 are indicated by the same symbols. This is for example
It uses a frequency register 34 consisting of a large capacity RAM of 2048 x 8 bits, and therefore by using 8 x 8 bits of memory for each piece of data.
Can store 256 pieces of data. Furthermore, by time-divisionally performing calculations on 64 bits into 8.times.8 bits, for example, the amount of cables and hardware constituting the full adder can be reduced. This will be explained in detail below.

The upper digit address selection circuit 32 selects the 34 upper digit addresses of the frequency register. For example, when the upper digit address 254 is selected, the address counting circuit 31 selects the 34 upper digit addresses of the frequency register. ,5,6,7,0,1,...
and address 2540 of frequency register 34,
The contents of 2541, 2542, . . . are sequentially read out and supplied to the control circuit 33 and full adder 35, respectively. The control circuit 33 supplies the contents of the 8-bit register of the address read from the phase register 22 to the 8-bit full adder 35, and adds the contents of the 8-bit register read from the frequency register 34, and as a result, The contents of the lower 8 bits obtained from the full adder 35 are written into the same address of the phase register 22 again. Reference numeral 39 denotes a signal sending circuit, which includes, for example, a carry register 36, a timing control circuit 37, and an AND circuit 38. If the content added by the full adder 35 exceeds 8 bits, the carry register 36 receives the signal from the full adder 35, temporarily stores it, and sends a carry signal to the full adder 35 with the next clock signal. send. However, when the contents of the highest address 2547 are added, a signal is supplied from the timing control circuit 37 to the clear terminal, so even if a carry signal is received, the contents are cleared, so the next clock signal completes the operation. No clock signal is provided to adder 35. Further, the timing control circuit 37 outputs a signal every time the address counting circuit 31 reads the contents of the highest address 2547, and outputs a signal to the carry register 3.
6 is cleared, and the AND circuit 38 is opened and the full adder 35 outputs a carry signal, that is, a signal indicating that the full scale value (for example, the maximum value indicated by 64 bits) has been exceeded. , which is supplied to the terminal 25.

Now, set the full scale value to A, frequency register 34
Let Bn be the value written to the upper digit address n of
The upper digit address selection circuit 32 selects the upper digit address n.
When selected and operated, a Bn signal among 8 Ax clocks is output to the terminal 25. When changing this output data, it is only necessary to use the upper digit address selection circuit 32 to switch to the upper digit address in which the desired value of the frequency register 34 is stored in advance, so the output data can be switched extremely quickly compared to conventional methods. be able to.

<Effects of the invention> As explained above, in this invention, a large capacity RAM is used as a frequency register to store multiple values, and when changing output data, the value stored in the frequency register is rewritten. Because you only need to select the address where the desired value is stored, the output data can be switched extremely quickly. Therefore, even when used in a frequency synthesizer, for example, the output data can be switched continuously with simple operations. A phase accumulator whose oscillation frequency can be varied is obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining an example of the use of a phase accumulator, FIG. 2 is a circuit diagram of a conventional phase accumulator, and FIG. 3 is a circuit diagram showing an embodiment of the phase accumulator according to this invention. 11: Reference frequency oscillator, 13: Phase comparator,
14: Low pass wave generator, 15: Voltage controlled oscillator,
16: Signal cancellation circuit, 17: Frequency divider, 18: Phase accumulator, 21: Setter, 22: Phase register, 23, 34: Frequency register, 24, 3
5: Full adder, 31: Address counting circuit, 32:
Upper digit address selection circuit, 33: Control circuit, 3
6: Carry register, 37: Timing control circuit, 39: Signal sending circuit.

Claims (1)

[Claims for Utility Model Registration] A. A clock signal source; B. A phase register; C. A frequency register having a capacity multiple times that of the phase register and divided into the same capacity as the phase register by the upper digit address. , D, an upper digit address selection circuit that selects an upper digit address of the frequency register; F. a full adder that adds the contents of the phase register and the frequency register read by the address counting circuit; G; a control circuit that supplies the contents of the phase register to the full adder and then writes the result of the operation to the same address of the phase register; H: when the operations of the phase register and the frequency register are completed; , a signal sending circuit that sends out a carry signal when the calculation result exceeds a full scale value, and a phase accumulator comprising: