JPH02214945A - Test mode enabling circuit for generating test enabled signal - Google Patents

Abstract

PURPOSE: To prevent the test mode from being set without intention by generating generating an enabling signal, which executes a test determined by a test mode code, by an enabling circuit. CONSTITUTION: Port latches 51 and 52 are coupled for the purpose of receiving the output of an I/O buffer 32, and the output terminal of the latch 52 is coupled to a test mode enabling circuit 55, and the output terminal of the latch 51 is coupled to various circuits which require the test mode(TM) code to perform a specific test. When a proper TM code is written in the latch 51 to perform a specific test as a first condition and a test mode enabling code is written in the other latch 52 as a second condition and a high voltage is supplied to a high voltage detector circuit 53, a test mode enabling circuit 55 generates the test mode enabling signal which enables the test mode. Thus, the test mode is prevented from being set without intention.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of memory devices, and in particular to external memories constituted by microcontrollers.

[Conventional technology]

In the semiconductor memory field, the design and manufacture of erasable programmable read only memories (EPROMs) is well known. These EFROM devices are formed on semiconductor chips and are typically configured as standardized capacity memories, such as 32Kt or 64Kt. These memory chips are typically placed in standard packages. Semiconductor memory devices, such as EPROMs, are coupled for operation with other semiconductor devices. In most cases, the EPROM is coupled to a processor that controls the transfer of data between the EPROM and the memory device. In a basic configuration, a memory location in an EPROM is accessed by a processor when the processor generates an address signal on address lines coupled to the memory. Depending on control signals provided by the processor, data is written into, or programmed into, or read from memory. Data transfer is accomplished by placing appropriate information on a data bus coupled to the memory. Unless the EPROM is part of a larger structure, such as a programmable logic array device, the EPROM
ROM does not include processing circuitry other than the circuitry necessary to perform addressing and data transfer.

One group of processors used to work with EPROMs is known as a microcontroller. Microcontrollers are specialized processors used to serve special applications, including custom applications. These controllers include everything necessary for operation and can typically include a processor, logic circuits, timing circuits, control circuits, buffers, latches, and on-chip memory. In most cases, specific application software is embedded in the controller chip. These controllers have inputs/outputs (Ilo) for passing information back and forth.
) including boats.

However, when external memory, such as the EFROM described above, is coupled to a given controller, it is always coupled to one or more ports of the controller. That is, if a given microcontroller requires off-chip memory for a given function of the controller, the off-chip memory is coupled to one or more ports of the controller. Il
Those boats are lost to use o. Without separate off-chip circuitry, coupling external memory to the microcontroller imposes severe constraints on its I10 performance. The reason is that the external memory monopolizes one or more ports of the microcontroller.

[Problem to be solved by the invention]

What is needed is a technique for coupling external memory to a microcontroller without reducing the number of I10 ports on the controller.

[Means to solve the problem]

The present invention provides an external memory to be coupled to the microcontroller, but also includes a boat expander to bring back into use those ports that are no longer in use due to the coupling of the boat expander to the microcontroller. This is what we provide. In short, the boat expander increases the total number of ports from the microcontroller while also coupling external memory to the microcontroller. The boat expander of the present invention is manufactured in a single semiconductor device and requires the use of special adhesive circuits.

The boat expander of the preferred embodiment is coupled to two boats of the microcontroller. Each boat is an 8-bit port. A 16-bit address signal and an 8-bit data signal are multiplexed on the bus that couples the boat expander to the two ports of the microcontroller. Boat extender is 32 pies)
It includes an EPROM, non-volatile configuration registers, and special function registers/boat controllers that provide external memory and boat expansion capabilities to the microcontroller. The boat expander's EFROM provides external memory to the microcontroller. However, data transfer between the I10 device and the occupied boat occurs via the expansion port of the boat expander.

The boat extender essentially acts as a data transfer point between the I10 device and the microcontroller. Therefore, data transfer can take place between the microcontroller and the EPROM of the boat expander or between the microcontroller and an external device via the boat expander. The configuration registers constitute a set of registers programmable by the microcontroller to direct and address the 9EFROM or special function registers. The boat extender of the present invention also includes special test activation circuitry that prevents accidental entry into test mode. To enter exam mode, enter a valid exam mode code,
It must be written to one of the boat latches coupled to the microcontroller. As a second condition, a valid test mode enable code must be written to the other port latches coupled to the microcontroller. Next, the read signal, whose voltage is approximately 12 volts, must be sustained for a sufficiently long time. When all three conditions are met, the boat extender enters its test mode. The duration of the read signal is measured by a pulse width detector to ensure that short pulses such as glitches and noise pulses do not trigger the test mode as intended. The three requirements that must be met provide sufficient security to prevent unintentional entry into test mode.

The following discussion describes a device that performs boat expansion and provides off-chip memory. In the following description, numerous details are set forth, such as specific memory capacities, signal lines, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the invention may be practiced without such specific details. In other instances, well-known structures and processes have not been described in detail in order not to obscure the present invention in unnecessary detail.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

Reference is first made to FIG. 1, where a conventional technique for coupling external memory to a microcontroller is shown. Microcontroller 1
EFROMll is shown as the external memory coupled to 2. Microcontroller 12 communicates with external devices via multiple ports. The particular example shown in FIG. 1 shows a microcontroller 12 having four bauds) 0-3. A specific example is shown in Figure 1, where the input/output (I
Various types of microcontrollers having lo) ports are well known in the art. A specific example of a conventional microcontroller is
Intel Corporation located in Clara (8anta C1ara)
8051.8096.801 manufactured by )
Includes equipment associated with the .88 microcontroller family.

In the example shown in FIG. 1, two of the ports of microcontroller 12, ports 0 and 2, are connected to bus 13.
4 is coupled to external memory EPROM11. Bus 13.14 is a bidirectional bus for transferring information between EPROM 11 and bidirectional port 0.2 of microcontroller 12.

Various conventional techniques are known for coupling address and data signals to buses 13 and 14. Furthermore, given that a given bus 13 or 14 is used only for coupling address information from the microcontroller 12 to the EFROM II, they need not be bidirectional buses. A control signal is also coupled to control line 15 between microcontroller 12 and EPROM 11 .

In typical operation, microcontroller 12 generates address signals. Their address signals are EPRO
It is coupled to EPROM 11 via at least one of buses 13 and 14 for accessing the address locations of M11. Data is then written via buses 13 and/or 14 to the EPRO, Mll or EPROM
11. It should be appreciated that the address and data signals can be multiplexed so that they can be combined onto a given bus.

The use of external memory IJk, such as EPROM 11, requires dedicating two ports in the example shown in FIG. Microcontroller 12 is left with only ports 1 and 3 for its I10 communications. I1
Buses 16 and 11 are coupled to ports 1 and 3, respectively, for 0 data transfers. As shown in FIG.
With one boat, the microcontroller 12 can only utilize the other two boats 1 and 3. Boat O and 2
In order to recover the data, it is necessary to use a specialized "glue" circuit to make the necessary connections between the board and the EPROM 11 to the ports O and 2.

Reference is now made to FIG. 2, in which the boat expander 20 of the present invention is shown coupled to a four-boat microcontroller 12a, which is equivalent to microcontroller 12 of FIG. The boat expander 20 includes an EPROM 2). This EPROM
2) is equivalent to EPROM 11 shown in FIG.

Boat extender 20 is coupled to boats O and 2 of microcontroller 12m via bus 13a141. A control signal is coupled between the microcontroller 12)L and the boat extender 20 via a control line 15m. Boats 1 and 3 are bus 16
a and 17a, respectively, to the various I10 devices. In order to indicate in other figures the same parts as shown in Fig. 1, the reference numbers denoting the parts shown in Fig. 1 are appended with the suffix ral to indicate the corresponding parts in the other figures. I'll decide.

Address and data information is provided from ports 0 and 2 of microcontroller 12a, and EPROM 2) is accessed as described with reference to FIG. EPROM
In addition to 2), boat expander 20 includes boats) A and B. The purpose of having boats A and B is to store external memory 2)
When Ilo is coupled to baud 0 and 2, the use of baud 0 and 2 for Ilo is again done. To do this, the port extender 20 of the present invention receives signals from bauds 0 and 2 and selects the destination of those signals.

microcontroller 12a boat 0.2 and EPROM2)
When transferring data between external memories in the form of
The boat extender 20 causes signals to be sent to and from the EPROM 2) via the buses 13m, 14m. However, assuming ports 0 and 2 are used for Ilo, the signal is on bus 13a.

14m to the boats A and B of the boat expander 20. Bus 1 connected to boats A and B respectively
8.19 allows data transfer between I10 devices and port ABO. By selecting EPROM2) or baud) B and A to operate on bus 13m, 14m, ports O and 2 of the microcontroller 12m can access external memory in the form of EPROM2) or boat B The I10 device can be accessed via and A. Thus, the boat expander of the present invention recovers ports lost when external memory is coupled to those same ports of the microcontroller.

Reference is now made to FIG. 3, in which the boat dilator 20 of the present invention is shown in detail. Boat 2 of microcontroller 12a is coupled to address buffer 25 of boat expander 20 via bus 14a. The address buffer 25 is coupled to an address latch 27. The boat O of the microcontroller 12) is coupled via the bus 13 & to the address buffer 26 of the boat expander 20, which address buffer 2
6 is coupled to address latch 2B. The output terminals of address latches 27 and 28 are the output terminals of EPROM 2), configuration register 30, or special function register/boat control (S FR/
PC) unit 31.

Although a variety of techniques can be used to perform address pin/data transfers, the preferred embodiment of the present invention utilizes the following techniques that are primarily suitable for the microcontrollers described above.

During the first period, address bits Ao-7 are supplied from the microcontroller 12m to the bus 13a, and the address bits Ao-7 are supplied to the bus 13a.
8-15 are supplied to bus 14&. Sixteen address bits are then provided to the address latches 27,28 for output from those latches. During the second period,
Data pins Do to 7 are supplied to the internal bidirectional data bus 39 via the bus 13a and the I10 buffer 32.

Its data bus 39 is coupled to data bus multiplexer 33. This data bus multiplexer is EPRO
M2) selects the configuration register 30 or SFR/PC 31 and connects it to the bus 39 to perform data transfer. The output terminal of address latch 27 is coupled to main control circuit 36 in addition to EPROM 2).

A portion of address signal A, ~15 is compared to preprogrammed pits in configuration register 30 and EPRO
M2), the configuration register 30, and the SFR/PC 31 to be accessed. In the preferred embodiment, the upper five bits are used, but the number of bits used is a matter of design choice. In addition, the microcontroller 12
A control signal from & is also applied to the main control circuit 36 via line 15&. The main control circuit 36 sends control signals to the address latches 27 and 28, the I10 buffer 32, and the EPRO
M2), configuration register 30, SFR/PC 31,
multiplexer 33 and boat buffers 34.35. Pot buffers 34 and 35 are coupled to boards A and B, respectively. Boat buffer 34.35 is SF
It is also bidirectionally coupled to the SFB/PC 31 in order to transfer data between the R/PC 31 and ports A and H.

Boat buffers 34.35 are also coupled to bidirectional bus 19.18. I10 buffer 32 to hold the signal
Other well-known circuitry, such as latches coupled to the board and boatback 734.35, are not shown.

Although a variety of control signals may be used, a representative example of the control signals used by the boat extender 20 of the preferred embodiment is shown in FIG. Chip enable signal CE/(symbol 1
(will be used to indicate a low activated state)
enables the master when asserted. If the signal CE/ is not asserted, the boat expander 2) is in a standby state and cannot be accessed. However, the boat keeps it's current running state. RD/ is used to indicate the read state from the SFR/PC device 31. WR/(PGM/) is used to write or program the boat extender 2). A to allow the address to flow through latches 27.28
LE signals are used. Vpp (R8T) programs the supply voltage during programming and provides reset during other modes. EPROM2) or configuration register 30
The program storage enable signal PSEN/ is used to indicate the read status from the boat expander 2, and that signal is used under certain conditions in conjunction with the RD/ signal to indicate the read status from the boat expander 2.
) to perform the read operation.

Next, the operation will be explained. Boat expander 20 allows three memory planes to be accessed by 16-bit address signals from microcontroller 12a.

Appropriate unit mapped to boat extender 20 2).
To select 30 or 31, memory mapping is actually performed by microcontroller 12a. The three memory planes are EPROM2), let configuration register 3
0 and SFR/PC unit 31.

The three planes that are mapped are shown in FIG.

Those three memory planes are EPROM plane 40
, SFR/RAM plane 41 and configuration plane 42
Each is composed of: When an SFR/RAM plane is selected, 8 FR/PC unit 31 instructions can occupy two byte planes within the plane. In the preferred embodiment, only 5 bytes are actually used for SFR/PC unit instructions. RAM is the part that is rarely used.
It can be used for various purposes. Other address locations are available for accessing RAM located within or external to microcontroller 12m. In FIG. 4 address locations are shown in hexadecimal notation. An identifier is also used in the plain address 0000 to provide information regarding the boat extender 20, such as the manufacturer's name, product model, etc.

Configuration plane 42 is inaccessible in normal operating modes. EPROM plane 40 and SFR/RAM
Only plane 41 can be accessed.

However, during programming/verification mode, EPROM plane 40 and configuration plane 42 are accessible. The preferred embodiment EPROM 2) is a 32K x 8 byte device. A 16-bit address can access 64 bytes, so 32 bytes in the preferred embodiment)'iEPROM
It can be mapped to various locations on plane 40. One configuration register 300, shown as a non-volatile register, is
Provides the starting address for mapping EPROM 2 in plane 40. The default location is shown to be in the lower half of EPROM plane 40, indicated by addresses 0000-7FFF. EPROM plane 40 can be mapped to two 32 byte EPROM'ff:.

In a preferred embodiment, a special function register (8FR)
is provided at the byte location 2 of the SFR/RAM plane 41. The default location is the top 2 byte locations of the SFR/RAM plane. Another configuration register 30 (by 2) determines the location of the SFR block. It is accessed by reading or writing to the baud A and B SFH of the baud extender 20.

The SFR/PC unit 31 controls the transfer of information between ports A and B in accordance with the SFR.

First, the boat extender 20 of the present invention is connected to the microcontroller 1.
2a, configuration registers 30 are programmed to configure the operation of boat expander 20. In this embodiment, three non-volatile registers make up configuration register 30. The first register is used to map byte EFROM2) to 32 in plane 40. The default location is at address location 0000. In this embodiment, this first register is set to J, EPROM by internally combining the PSEN/ and RD/ signals.
It is also used to combine planes and SFR/RAM planes. The second configuration register is also used to provide base addresses for special function registers. As mentioned above, this embodiment uses byte boundaries at two so that any two of the SFR/RAM planes 41 can have SFRs at byte boundaries. The default is at address F800.

The third configuration register is a transistor-transistor logic (TTL) or complementary metal-oxide-semiconductor (
used to configure each boat A and B to obtain a level of I10 performance compatible with CMO8). Furthermore,
This third register also allows supplementing the polarity of R8T to provide a programmable reset.

Once the configuration registers are programmed, the addresses that access EPROM 2) and special function registers 31 are programmed. If the microcontroller 12a wants to access the EFROM, the microcontroller 12a
The address signal from a must match the mapped address. For example, if the EFROM is in its default location, addresses 0000-7FFF can access EPROM2). Alternatively, if at least one of boats A and B is to perform a data transfer, microcontroller 12& supplies an address corresponding to SFH in SFR/RAM plane 41. That S
Assuming that the FR is in the SFR/RAM plane 41,
It exists between F2O3-FFFF. Microcontroller 1
Data transfer between 2m and at least one of boats A and B is performed by accessing SFR locations and storing data in SFH. Boats are interactive;
Can be read and written.

Other address locations in the SFR/RAM plane 41 are used to address the RAM locations of the microcontroller 12 & or other memory mapped devices. Therefore, the boat extender 2o of the present invention can provide external EPROM memory to the associated microcontroller, while at the same time special function registers transfer data between the microcontroller and the two extended boards (A, H). It can be so. A configuration program 30 is programmed to allow special function registers (EPROM 2) to be mapped to various locations.

With this programmed mapping technique, jj), E
This allows greater flexibility in addressing PROM2) and extended baud A and B.

Although one mapping technique has been described in this preferred embodiment, EPROM 2) and SFR/PC device 31
It should be understood that a variety of mapping techniques can be used to map the For example, overlay techniques can be used so that SFR registers can be mapped onto unused portions of the EPROM plane, or EPROM and SFR registers can be placed on top of each other. Furthermore, in the four-boat microcontroller arrangement shown in FIG.
A second boat expander is connected to buses 13& and 14a to form a boat that accesses bytes to 64 of the EPROM.
It should be understood that it can be combined with In that case,
The two mapping techniques can be combined so that the second EFROM can be mapped for access by address signals between addresses 8000-FFFF of FIG. By using a 32-byte EFROM, two such EPROMs can be accessed with 16-bit addressing technology.

It should be understood that the various pine pink techniques described above are illustrative and not intended to limit the invention. Various other techniques can be easily implemented without departing from the spirit of the invention.

Further, other units can be easily used in place of the existing device, such as using a static RAM in place of the EPROM 2), without departing from the gist of the present invention. In addition, although preferred embodiments have been described in which the capacity of the EFROM and the number of bits of the address line and data line are set to specific values, these examples are for illustration only.
The actual value is a matter of design choice.

Test mode enablement The test mode is a non-user mode that is typically used to apply stress to a component and to determine the margin of the component. Since the test mode is used strictly for testing manufactured parts, care should be taken that the user of the part does not place the part in that test mode. Whether intended or not, using a component in test mode can cause damage to equipment associated with the component. Some test mode enablement techniques utilize high voltage detectors to place parts into specific test modes. In some cases, equipment may be placed in test mode due to noisy conditions, thereby causing damage to itself or associated equipment.
Sometimes inaccurate information may be read or written.

To prevent unintended entry into test mode, the boat expander 20 of the present invention utilizes special circuitry to prevent this. Special test activation circuitry is provided in the boat expander 20 to generate a test mode enable signal to enable the test mode. Reference is now made to FIG. Two boat latches 51 and 52 are I10 buffer 3
2 is coupled to receive the output of 2. An output terminal of latch 52 is coupled to a test mode enable circuit 55,
One output terminal is coupled to various circuits that require a test mode code to perform a particular test. Read signal RD/ is coupled as an input to high voltage detector circuit 53. High voltage detection circuit 53 detects the presence of high voltage necessary to enter test mode. The high voltage detection signal is applied to filter 54, and the signal F-waved by the filter is applied to test mode enabling circuit 55.

In operation, three conditions must exist before the preferred embodiment boat extender 20 enters its test mode. The first condition is that the proper test mode (TM) code must be written to latch 51 to perform a particular test. The second condition is to enable test mode (
TME) code must be written to the other latch 52. Inputs to the boat latches 51.52 are provided by microcontrollers or other signal generators (for testing) via buses 14m, 13m. In the preferred embodiment, latches 51 and 52 are driven by the latches for baud A and B, respectively.

However, it should be understood that latches 51 and 52 are not limited to use as boat latches. appropriate T
The circuit 5 is configured such that the test mode enable circuit 55 is activated only when the ME code is provided by the latch 52.
5 is pre-programmed.

The third condition is that a high voltage must be supplied to the high voltage detector circuit 53. A high voltage is present when the RD/signal goes to a high voltage state, such as a voltage higher than the power supply voltage vCC. In the preferred embodiment, 12V DC is used. When the RD/ signal is 12 volts, the RD/ signal causes the high voltage detector circuit 53 to generate a detection signal. The detection signal is coupled through filter 54 to test mode enable circuit 55. Whenever a high voltage detection signal is applied to the test mode enable circuit 55 and the appropriate TM code is present, the test mode enable circuit generates a test mode enable signal to enable the test mode.

Filter circuit 54 includes a pulse width detector 56 made up of a series of series coupled inverters (two inverters 57, 58 are shown in FIG. 5) and a Nandt gate 59. The Nandts gate 590 input terminal is the input terminal of the first inverter 57 υ, and the output terminal of the Nandts gate 59 is the output terminal of the last inverter 58. Pulse width detector 56 operates to filter out short pulses, such as glitches, so that high voltages are not unintentionally generated. That is, if the signal RD/ becomes higher than the power supply voltage VCC due to the voltage spy 7, and the power supply voltage VCC becomes lower, and the high voltage detection circuit 53 generates a high voltage detection signal, the predetermined pulse width The high voltage detection signal cannot be coupled through filter 54 due to the presence of pulse width detector 56, which does not pass very narrow pulses. The minimum pulse width that can pass through pulse width detector 56 is determined by the delay in the series inverter string. The pulse width of the signal that can pass through the pulse width detector 56 is sufficiently wide so that the pulse is still present at the input terminal of the inverter 57 after being subjected to the delay of the inverter string represented by inverters 5T and 58. Must.

Therefore, three conditions must exist in order to enter test mode to perform a correct test. That is, the boat extender 20 receives a valid test mode code to perform a particular test, receives a valid test mode enable code that matches a pre-programmed code, and receives a 12V read signal. That is to have for a long time. Only when those three conditions exist can this boat extender perform a correct test. In another embodiment, test mode enabling circuit 55
The TM code can be held in latch 51 using the test mode enable signal from .

That is, latch 51 cannot receive a TM code until the test mode enable signal is generated.

Although the test mode enabling technique of the present invention has been described with respect to a boat extender, the test mode enabling technique can easily be implemented with other devices. For example, EPROM or static R
A memory, such as an AM, can be put into its test mode by requiring a valid code to be written to its latches, and then a control signal, such as a read signal, is held at a predetermined level for a sufficient period of time. It can be moved to

Only when these three conditions are met will the boat extender perform the desired test. Additionally, other devices can be used in place of latches to implement the "hold-enabling" technique of the present invention.

What has been described above is a boat expander that has internal memory and special protection circuitry that prevents unintentional entry into test mode. Providing external memory to the associated device couples the boat expander to operate with the associated processor or device, but also restores the use of the boat lost by coupling to the external memory. No separate adhesive circuit is required. Although the boat expander of the present invention is manufactured with one semiconductor chip, it is not important to do so for the implementation of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram illustrating how two ports are lost when external memory is coupled to a microcontroller; FIG. A schematic diagram illustrating how a boat that is lost when being joined to two boats is made available again; FIG. 3 is a block diagram illustrating the boat extender of the present invention; FIG. 4 is a diagram showing the use of the boat extender of the present invention; FIG. 5 is a block diagram illustrating activation of the test mode of the boat expander of the present invention. 20...Boat extender, 25, 26...Address buffer, 27.28-...Address latch, 30
---Configuration register, 31--Special function register and boat controller, 32--I10 buffer, 3
4, 35...Boat buffer, 36...Main control circuit, 51, 52...Port latch, 53...
High voltage detection! , 54...Fist filter, 5511・Φ・
Test mode enabling circuit, 56...Pulse width detector.

Claims (2)

[Claims] (1) a first latch for receiving a test mode code, a second latch for receiving a test mode enable code, a voltage detector for detecting a test activation voltage, and coupling the voltage detector to the second latch; an enabling circuit, wherein the test mode enabling code is compared to a preprogrammed value stored in the enabling circuit;
If the test mode enable code matches the value and the test activation voltage is present, the enable circuit generates an enable signal to perform a test determined by the test mode code. A test mode enabling circuit generating a test enabling signal, characterized in that: (2) a first latch that receives a test mode code, a second latch that receives a test mode enable code, a voltage detector that detects a test start voltage and generates a test start signal; a filter coupled to filter the test activation signal received from the voltage detector; and an enabling circuit coupled to the filter and the second latch, the test mode enabling code configured to filter the test activation signal received from the voltage detector; If the test mode enable code matches the pre-programmed value and the test activation voltage is present when compared to a pre-programmed value stored in the enable circuit, then the enable circuit A test enable signal for placing a semiconductor device in a test mode for performing a given test on the semiconductor device, characterized in that it generates an enable signal for performing a test determined by the test mode code. A test mode enabling circuit that generates.