JPH02207321A - Bidirectional fifo memory - Google Patents

Abstract

PURPOSE:To control the direction of data flow by means of two devices by providing a register which outputs a port selecting signal corresponding to a set state. CONSTITUTION:For example, when a register setting signal RS1 from a first device 101 is set at a high level, a register 3 is set at a state in which a port selecting signal PS as the high level is outputted. When a register setting signal RS2 from a second device 102 is set at the high level, the register 3 is set at the state in which the port selecting signal PS at a low level is outputted. For example, when the port selecting signal PS is at the high level, a first data input/output port in a port select control circuit 2 is connected to a data output bus OB, and a second data input/output port is connected to a data input bus IB. Thus the direction of the data flow can be controlled by either one of the first and second devices 101 and 102.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bidirectional FIFO memory, and particularly to a bidirectional FIFO memory that is provided with two data input/output buses and that writes data from two directions in the order in which it was written. Bidirectional FIF that can be read
Regarding O memory.

[Conventional technology]

Conventionally, FIFO memory has been used as a memory that temporarily stores and outputs data sequences without changing the order in which they arrive, in order to efficiently transmit data between devices with different data processing speeds.

FIG. 4 shows an example of a conventional bidirectional FIFO memory that can read and write data to and from different devices.

This bidirectional FIFO memory sequentially stores each piece of data arriving from the data input bus IB in the order of arrival, and outputs each stored data sequentially to the data output bus OB in the order of arrival.
IFO memory 1 and first and second devices 101 and 102
and first and second data input/output buses l0Bt, l0B2, which are respectively connected to the first and second data input/output buses l0B1. comprising first and second data input/output ports respectively correspondingly connected to l0B2;
Port select control for controlling the connection between the first and second data input/output ports and the data input bus IB and data output bus OB according to the port select signal PS input from one port select signal input terminal T'ps Since there is only one port select signal input terminal TP5, it is connected to either one of the first and second devices 101 and 102, and the port select signal PS is input from either one. It was supposed to output .

For example, when the port select signal PS is high level,
The first data input/output port is connected to the data output bus OB, and the second data input/output port is connected to the data input bus IB.
connected to. When the port select signal PS is at a low level, the first data input/output port is connected to the data input bus IB, and the second data input/output port is connected to the data output bus OB.

[Problem to be solved by the invention]

The conventional bidirectional FIFO memory described above has a first and second
Since there is only one port select signal input terminal T'ps that controls the connection between the data input/output port of the data input/output port, the data input bus IB, and the data output bus OB, the first and second There is a drawback in that the direction in which data flows can only be controlled from one of the devices 101 and 102.

An object of the present invention is to provide a bidirectional FIFO that can control the direction of data flow from either the first or second device.
The purpose is to provide memory.

[Means to solve the problem]

The bidirectional FIFO memory of the present invention includes a FIFO memory that sequentially stores each data arriving from a data input bus in the order of arrival, and outputs the stored data to the condylar data output bus in the order of arrival; first and second data input/output buses that are respectively connected to the second device and transmit data; and first and second data input/output buses that are respectively connected to the first and second data input/output buses. data input/output ports, and the first
and a port select control circuit that controls the connection between the second data input/output port and the data input bus and the data output bus, and a port select control circuit that can set two states, and selects the port select according to the set state. It has a register for outputting a signal, and means for setting the state of the register by the first and second devices.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIFO memory 1. The port select control circuit 2, the first and second data input/output buses IOBlrOB2 each have the same configuration and function as the conventional bidirectional F'IFO memory shown in FIG. They are also interconnected and operate in the same way.

The register 3 can set two states, and outputs the port select signal ps according to the set state.

The setting of the state of this register 3 is performed by the first and second devices 1.
Register setting signals RS, , R from 01 and 102, respectively.
Perform according to 3. For example, when the register setting signal R81 from the first device 101 is set to high level, the register 3
is set to output a high-level port select signal PS, and the register setting signal R from the second device 102 is set to output a high-level port select signal PS.
32 is set to a high level, the register 3 is set to output a low level port select signal PS.

FIG. 2 is a circuit diagram showing a specific example of the port select control circuit 2 of this embodiment.

Connections between the first and second data input/output ports 2OA, 20B and the data input bus IB and data output bus OB in the port select control circuit 2 when the port select signal PS is at high level and when the port select signal PS is at low level The connection is the same as before.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this embodiment, the state of the register 3^ that outputs the port select signal PS is transmitted to the first and second devices 101 and 102.
The settings are made using specific bits (hereinafter referred to as register setting bits) of each data input from the register.

Each data input from the first and second devices 101 and 102 is sequentially written into the FIFO memory 1^ via the port select control circuit 2 and the data input bus IB. At this time, the register setting bits of each data are sequentially stored in the register setting bit area 11 in correspondence with each data, and when read out, they are sequentially read out in correspondence with each data and input into the register 3A. Register 3A sets the state according to the contents of this register setting bit and responds to this state.
;outputs the jj-to select signal PS.

Therefore, there is an advantage that a cycle for setting the state of the register 3A from the first and second devices 101 and 102 is not necessary.

〔Effect of the invention〕

As explained above, the present invention has a register that can set two states and outputs a port select signal according to the set state, and a register that is connected to two data input/output buses from two devices. Conventionally, by providing means for setting the state of the device and controlling the direction of data flow using this port select signal, it has been possible to control the direction of data flow in only one of the two devices. However, the advantage is that it can be controlled from both devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a circuit diagram showing a specific example of the port select control circuit of the embodiment shown in Fig. 1, Fig. 3 is a block diagram showing a second embodiment of the present invention, and Fig. 4 is a conventional bidirectional FIFO. FIG. 2 is a block diagram showing an example of a memory. 1, IA... FIFO memory, 2... Port select control circuit, 3, 3A... Register, 11... Register setting bit area, 2OA, 20B... Data input/output port, 21A, 21B, 22A, 22g...
Tri-state buffer, 101. l0IA...1st
device, 102.1024... second device, IB...
-Data input bus, l0B1. l0B2...Data input/output bus, OB...Data output bus. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a FIFO memory that sequentially stores each data arriving from a data input bus in the order of arrival, and outputs each of the stored data sequentially to the data output bus in the order of arrival;
first and second data input/output buses that are connected to the corresponding devices and transmit data;
The first and second data input/output ports are connected to the data input/output bus in correspondence with each other, and the first and second data input/output ports are connected to the data input/output bus and the data output bus in accordance with a port select signal. a port select control circuit that controls connection with the bus; a register that can set two states and outputs the port select signal according to the set state;
and means for setting the state of the register by the device.