JPH02206263A - Delay detecting circuit - Google Patents

Abstract

PURPOSE:To always obtain the optimal demodulating characteristic of PSK demodulation by comparing the phase of a received signal with the phase of an output on the intermediate stage of a shift register, and controlling the frequency of the voltage controlled oscillator of the sample clock of the shift register. CONSTITUTION:A received signal Rin and the output of a shift register 1 for delaying having (m) stages is multiplied by a multiplier 5, only a low frequency component is fetched by a low pass filter 6, and the demodulated output is obtained. The demodulated output is identified at timing optimal for identification when an eye pattern aperture from a data timing reproducing circuit 8 is maximal by a discriminator 7, and data are reproduced. Further the input Rin of the shift register 1 having the (m) shift stages for a delay element and a shift output (k) on the intermediate stage of the (m) stages are inputted to input terminals (a) and (b) of a phase comparator 21 of a PLL circuit 2, an error voltage out of a phase error is impressed as the control voltage of a voltage control oscillator 22, and a frequency fS of the voltage controlled oscillator 22 is made variable.

Description

[Detailed Description of the Invention] [Summary] P in a PSK conversion digital mobile radio receiving device
Regarding the delay detection circuit of the SK demodulator, an object of the present invention is to provide a delay detection circuit in which the eye pattern aperture of the delay detection output does not deteriorate due to fluctuations in the oscillation frequency ωL of the local oscillator of the receiver, which is inevitable in mobile radio. A PLL circuit that controls the oscillation frequency fs of the voltage-controlled oscillator that supplies the sample clock to the shift register based on the output error of a phase comparator that compares the phase of the received signal Rin with the phase of the output of the intermediate stage of the delay shift register. 2 (first invention), or multiplying the received signal Rin by the output of the delay shift register and extracting the low frequency component with a low pass filter, converting it into ^/D and reading it into the arithmetic unit CPU, N at the optimal timing obtained by the timing regeneration circuit
Signal processing in which the absolute value of the difference between the two peak values of the cumulative distribution of the N sample data obtained by sampling is repeated, and the output value is repeatedly added and subtracted depending on the sign of the difference between the absolute value and the value at the time of previous sampling. Due to the D/A conversion output of the circuit,
Either the sample clock control loop 3 is configured to control the oscillation frequency fs of the voltage controlled oscillator for supplying the sample clock to the shift register so that the eye pattern opening of the demodulated output is maximized (second invention), or the signal processing circuit and A stage number selection loop 4 is constituted by a selection circuit that selects the shift output of an intermediate stage of the m-stage shift register so that the eye pattern aperture of the demodulated output is maximized by the output of the arithmetic unit CPU of the same signal processing circuit. (Third invention) Accordingly, the delay IT (·m/fs) of the delay shift register is configured to be varied so as to always satisfy a predetermined condition for delayed detection.

[Industrial Application Field] The present invention relates to mobile radio communication using digital modulation, and particularly to PS
The present invention relates to a delay detection circuit of a PSK demodulator that demodulates a PSK modulated signal in a K modulation mobile radio communication receiving device.

In pre-mobile vAii11 communications, it is necessary to function even under poor radio wave propagation environments with interruptions in received waves and high-speed fading, etc., so PSK demodulators used in mobile radios are required to develop technology suitable for mobile radios. A delay detection circuit that does not require reproducing a carrier signal synchronized with the received input, such as PSK demodulation using synchronous detection in fixed radio, is considered to be promising.

(Prior Art) To explain the configuration of a conventional delay detection circuit when demodulating a two-phase PSK signal, as shown in FIG. 5, in PSK modulation on the transmitting side (not shown), one
A summation conversion is performed in which the sum of the previous bit of transmission data Y and -1 is calculated and the output bit is obtained.

If the transmitted data string after conversion is Y□, then Y = y
It is expressed as i-+ + X, (1). Using this Y as a PSK modulation signal, the sign of Yi is 1.
, 0, the phase of the carrier wave is set to 0. A two-phase PSK modulated wave changed to π is transmitted to the receiving side shown in the figure, but this PS
K modulation wave 1? (t) is expressed by the following formula.

R(t)=CO5(ωLt+y, π) (2) Here, ω
L is the carrier frequency. On the receiving side, this radio frequency ω
. The PSX modulated wave of is received by the antenna 10, mixed with the oscillation wave of the reception local oscillator 20 of frequency ωL by the mixer 30, and the frequency is converted to obtain the received signal L(t) = C0S ((
ω. −ωL)t+V,π] (3) is obtained. This received signal L(t) is processed by a delay circuit 1 of a shift register, for example.
The signal delayed by one symbol time T of the transmission data is L(t - T) = COS ((ω. - ωL Xt T) + Y =
−+π] (4). Therefore, in order to perform delayed detection of the received signal, when the signals of equations (3) and (4) are multiplied by the multiplier 5, D=L(t)χL(L-T)=172・COS ((ω. -ωL)T+(Y
.

y t-1) π] = 1/2 -CO3 ((ω.-<IJL)T0Xs
x ) (5) is obtained, and the low-pass filter 6 extracts only its low frequency components. Here, (ωL-ωL)T=2ng (n is a natural number), (6)
When ωLET is set so as to satisfy the equation (5), the equation (5) becomes D<172>CO5(X i π)(7), and a demodulated output is obtained. The output of the multiplier 5 is passed to the discriminator 7, and the positive polarity is determined by the sign 1. By encoding the negative with the code 0, the original data string xi is reproduced without error and FSX demodulation is performed. FIG. 6A shows an eye pattern aperture of the demodulated output representing the margin for the output of equation (7) to be identified by the discriminator 7 when the transmission bandwidth is limited on the transmitting side.

[Problem to be solved by the invention]

As mentioned above, in the conventional delay detection circuit, when the oscillation frequency ωL of the local oscillator 20 of the receiver fluctuates (in the case of a mobile radio, the local oscillation frequency ωL tends to fluctuate due to changes in the surrounding conditions), ) is no longer satisfied, the eye pattern aperture of the PSK demodulated output decreases, and the demodulation characteristics deteriorate as shown in FIG. 6B. Especially delay circuit 1
When the one symbol time 'r of the transmission data that delays the received signal L(1) is large (when the data rate is slow),
Frequency after frequency conversion of the mixer 30 output due to fluctuations in the oscillation frequency ωL of the local oscillator 20 of the receiver (ω.-ωL)
As the product Δω·T of the variation Δω and time T approaches 2nπ, the degree of allowable deterioration of the eye pattern aperture of the demodulated output becomes critical, which poses a practical problem for mobile radio. The present invention provides delayed detection in which the eye pattern aperture of the output of the low-pass filter 6 that is allowed by the discriminator 7 does not deteriorate even if the oscillation frequency ωL of the local oscillator 20 of the receiver, which is inevitable in mobile radio, fluctuates to a certain degree. The task is to provide a circuit.

[Means to solve the problem]

This problem is solved by the antenna 10 as shown in the principle diagram of FIG.
PSK modulated signal R(t) of radio frequency ωゎ received at
is the output of the local oscillator 20 with the oscillation frequency ωL and the mixer 3
The sample clock frequency is fs and the number of shift stages is m, which delays the received signal 11 inches mixed and frequency-converted at 0 by an integral multiple of one symbol time of the transmission data.
The output of the delay shift register (1) whose delay time T is given by the formula T=m/f is multiplied by the multiplier 5, and only the low frequency component thereof is extracted by the low-pass filter (6) to reproduce the timing of the data. In the delay detection circuit of the PSK demodulator that reproduces the identification (7) data at the optimum timing reproduced by the circuit (8), the phase of the input received signal Rin and the output of the intermediate stage of the delay shift register 1 are compared. The output error of the phase comparator 21 constitutes a PLL circuit 2 that controls the oscillation frequency fs of the voltage-controlled oscillator 22 that supplies the sample clock to the shift register l (first invention), or the output error is extracted by the low-pass filter 6. The low frequency component is A/D converted, encoded, read into the arithmetic unit CPU, and sampled N times at the optimum timing obtained by the timing regeneration circuit 8, and two peak values of the cumulative distribution of the obtained N sample data are obtained. The D/A conversion output of the signal processing circuit 31 calculates the absolute value of the difference and repeats addition and subtraction of the output value to the D/A converter depending on the sign of the difference between the absolute value and the value at the time of previous sampling. A sample clock control loop 3 is configured to control the oscillation frequency fs of the voltage controlled oscillator 12 for supplying the sample clock to the shift register 1 so that the aperture of the demodulated eye pattern of the output of the shift register 1 is maximized (second invention). , the same signal processing circuit 41 as the signal processing circuit 31
Based on the output of the arithmetic unit cpυ, the selection circuit 42 selects the shift output of the intermediate stage of the m-stage shift register 1 so that the aperture of the demodulated eye pattern extracted by the low-pass filter 6 is maximized. (third invention), the delay amount T of the shift register 1 is adjusted so that the multiplier 5 always satisfies the predetermined conditional expression (6) for delayed detection.
This problem is solved by the configuration of the present invention in which = m/fs is varied.

In the principle diagram of FIG. 1 showing the configuration of the delay detection circuit of the present invention, 1 is the radio frequency ω of PSK modulation received by the antenna 10. The received signal R(t) is mixed with the oscillation frequency ωL of the local oscillator 20 by the mixer 30 and frequency-converted.
This is a delay circuit element that takes input in and delays it by an integral multiple of the time of one symbol of transmission data, the frequency of the sample clock for bit shifting is fs, and the number of shift stages is m.
This is a delay shift register in which the delay time T of a stage can be expressed by the formula T=m/fS.

2 is related to the first invention, and includes a phase comparator 2 between the received signal Rin and the output of an intermediate stage of the m-stage shift register l.
This is a PLL circuit that controls the oscillation frequency fs of the voltage-controlled oscillator 22 that supplies the sample clock to the shift register 1 based on an output error of The delay amount T (·m/fs) of the shift register 1 is varied so as to satisfy (6).

3 is related to the second invention, in which a low frequency component extracted by a low-pass filter 6 from the output obtained by multiplying the received signal Rin and the output of the delay shift register 1 by a multiplier 5 is converted into an A/
D-convert the data, encode it, read it into the arithmetic unit CPU, sample it N times at the optimal timing obtained by the timing recovery circuit 8, and find the absolute value of the difference between the two peak values of the cumulative distribution of the obtained N sample data. The demodulated eye pattern of the output of the low-pass filter 6 is generated by the D/A conversion output of the signal processing circuit 31, which repeats addition and subtraction of the output value to the D/A converter depending on the sign of the difference between the absolute value and the value at the time of previous sampling. This is a sample clock control loop that controls the oscillation frequency fs of the voltage controlled oscillator 32 that supplies the sample clock to the shift register 1 so that the aperture of the shift register 1 is maximized.

4 is for the third invention, and the signal processing circuit 31
By the output of the arithmetic unit CPU of the same signal processing circuit 41,
This is a stage number selection loop comprised of a selection circuit 43 that selects the shift output of the intermediate stage of the one-stage shift register 1 so that the eye pattern aperture of the demodulated output extracted by the low-pass filter 6 is maximized.

And PLL circuit 2. Sample clock control wholesale loop 3
, or the stage number selection loop 4, the received signal Ri
n and the output of the shift register 1 that delays the received signal Rin by an integer multiple of the transmission data symbol time. Shift register 1 delay M
Vary and set T.

[Effect]

The delay shift register 1 receives the radio frequency ω received by the antenna 10. The received signal sequence R(t) of PSK modulation is mixed with the output of the local oscillator 20 having the oscillation frequency ωL in the mixer 30, and the frequency-converted received signal Rin is inputted and delayed by an integral multiple of the time of one symbol of the transmission data. let Since the frequency of the sample clock for bit shifting is fs and the number of shift stages is m, the delay time T can be expressed by the formula T=m/fs. In the first aspect of the present invention, PL
The L circuit 2 inputs the phase of the received signal Rin and the shift register l.
The frequency fs of the voltage controlled oscillator 22 of the sample clock of the shift register 1 is controlled by the output error of the phase comparator 21 which compares the phase with the output of the intermediate stage of the received signal R.
The delay amount T of the shift register 1 that satisfies the predetermined relational expression (6) for differential detection that identifies the low frequency component of the product of 1n and the shift output of the final stage l of the shift register 1 without error is T=m/
Set fs. Therefore the radio frequency ω. Even if the oscillation frequency ωL of the receiving local oscillator 20 that frequency-converts the received signal R(t) of Since the delay and IT are set, there is no deterioration of the demodulated eye pattern aperture of the output of the multiplier 5, and the problem is solved because the optimum demodulation characteristics of PSK demodulation can always be obtained.

In the second aspect of the present invention, the sample clock control loop 3
However, the low frequency component of the product of the human input signal Rin and the final stage output m of the m-stage shift register 1 is processed by the signal processing circuit 31 as follows.
First, it is A/D converted, encoded, and read into the arithmetic unit CPυ.
Sampling is performed N times at the optimum timing obtained by the timing regeneration circuit 8, and the absolute value of the difference between the two peak values of the cumulative distribution of the obtained N sample data is determined, and the difference between this absolute value and the value at the time of previous sampling is determined. The output value is repeatedly added and subtracted to the D/A converter depending on the positive and negative values of Since the oscillation frequency fs of the voltage controlled oscillator 32 that supplies the sample clock is controlled, the delay amount T (·m/fs) of the shift register 1 is adjusted so that the low frequency component satisfies the predetermined relational expression (6) for delayed detection. Set.

In the third aspect of the present invention, the stage number selection loop 4 is configured to include arithmetic unit cp of the same signal processing circuit 41 as the signal processing circuit 31.
Based on the output of signal u, the selection circuit 42 selects the shift output of the intermediate stage of the m-stage shift register 1 so that the opening of the eye pattern of the demodulated output extracted by the low-pass filter 6 is maximized. The delay amount T (
= m/fs). Therefore, in any of the first, second, and third aspects of the present invention, the radio frequency ω. Even if the oscillation frequency ωL of the receiving local oscillator 20 that converts the frequency of the received signal R(t) of the PLL circuit 2. Since the delay IJT of the shift register 1 is set by one of the sample clock control loop 39 and the stage number selection loop 4 so that the multiplier 5 satisfies the predetermined relational expression (6) for delayed detection, the eye pattern of the demodulated output is The problem is solved because the aperture does not deteriorate and the optimum demodulation characteristics of PSK demodulation can always be obtained.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the delay detection circuit according to the first embodiment of the present invention, and is shown in FIG. 7(a).

(b), (C), and (d) are explanatory diagrams for explaining the operation. And FIGS. 3 and 4 show the second invention,
FIG. 3 is a block diagram showing the configuration of a delay detection circuit according to an embodiment of the third invention. In both cases, the delay circuit element is applied to a two-phase PSK delay detector, and the sample clock is fs (I
lz), and is composed of a shift register 1 having m shift stages, and its delay time T is determined by the following equation.

T = m/fs (8) In the delayed detection PSK demodulator, the radio frequency ω received by the antenna 10. The received signal Rin obtained by frequency-converting the received signal R(t) of PSK modulation using the output ωL of the local oscillator 20 is multiplied by the output of the shift register 1 with m stages for delay in the multiplier 5, and the low frequency Only the low frequency components are extracted by the pass filter 6, and a demodulated output expressed by the above equation (5) is obtained. This demodulated output is identified by the discriminator 7 at the optimum timing for identification, at which the eye pattern opening from the data timing reproducing circuit 8 is maximized, and the data is reproduced.

In the embodiment of the first invention in FIG. 2
1, and the error voltage o of the phase error is input to the input terminals a and b of
ut is applied as a control voltage to the voltage controlled oscillator 22 (automatic oscillator vCO1 or crystal oscillator VCXO), and the oscillation frequency fs of the voltage controlled oscillator 22 is varied. Here, k is given by (m-k)/fs-π/2/(ω0-ωL) (9). The phase difference between this human input Rin and the stage-delayed output is ±π/2 due to the phase 0°π of the input two-phase PSK signal Rin. This PLL circuit 20 phase comparator 2
1, the relationship between the phase error of the input terminals a and b and the output voltage Vout is shown in FIG. 7 (a) of the explanatory diagram. The characteristics of the voltage controlled oscillator are shown in FIG. 7(b). From this, the phase stable point of the I'LL circuit 2 is shown in (a) in Figure 7.
The phase error of the characteristics of the PLL circuit is at two points of ±π/2, which is the input Rin and m of the shift register 1 of the delay element.
This corresponds to the phase difference sail π of the output after the stage shift.

Therefore, the PLL circuit 2 always converges the two-phase PSK modulated wave so as to satisfy the following equation.

(ω.-ωL)xT=nπ (n is a natural number> (10
) However, if n converges to an odd number in Equation (10), the sign of the output of Equation (5) will be reversed and the bit sign will be reversed in the reproduced data. The data timing regeneration circuit 5 determines when the synchronization signal is detected, or the frequency conversion local oscillator 20 determines ±π/
By avoiding fluctuations in the oscillation frequency ωL that would cause a phase error of more than 2, a correct reproduced data string can be obtained.

FIG. 7(C) shows a configuration example of the phase comparator 21, and the seventh
(d) of the figure shows the operation time chart. The configuration of the phase comparator shown in FIG. 7(C) is as follows: edge detector 211, edge detector 212. RS flip-flop 213. Differential amplifier 214. It consists of a low-pass filter 215, and the edge detector 211 and the edge detector 212 are shown in FIG.
d) As shown in the time chart, detect the rising and falling edges of the two input signals a and b whose phases are to be compared, generate pulses c and d, and input them to the RS flip-flop 213. RS flip-flop 213
is set and reset at the rising or falling edge of the b input. From this, l? At the output port of the S flip-flop 213, as shown in e of the time chart of FIG.
A rectangular signal with a pulse width corresponding to the phase difference between the two digital signal inputs a and b is obtained.

After converting the output port of this RS flip-flop 213 and its inverted output Q into a waveform that changes around the voltage Oν as shown in f in FIG. 7(d) using the operational amplifier of the differential amplifier 214, the low frequency By using the filter 215 as a loop filter, a DC voltage having a value proportional to the pulse width is obtained. This DC voltage is used as the error voltage Vc to control the oscillation frequency f of the voltage controlled oscillator 22 of the PLL circuit 2, and as shown in FIG. 7(c), the oscillation frequency f when the error voltage Vc=O.

control so that The time constant of the loop filter 215 of the PLL circuit 2 changes due to fluctuations in the input signals a and b of the PLL circuit 2 due to high-speed fading.
The oscillation frequency f is set to be long enough not to fluctuate, and the PLL circuit 2 is set to have an appropriate pull-in time.

In the embodiment of the second invention shown in FIG.
The shifted output m of the shift register 1 of the stage is multiplied by the multiplier 5.
A low-pass filter 6 extracts only the low frequency components to obtain a demodulated output expressed by the above equation (5), and this demodulated output is passed to a discriminator 7 to identify the one with the largest eye pattern aperture. The output of the low-pass filter 6 is A/D converted by the A/D converter 311 of the signal processing circuit 31 of the sample clock control loop 3 and converted into a CF. 'U read into 312,
The calculation is performed according to an algorithm that maximizes the eye pattern aperture, which will be described later, and the obtained value is converted into a D/A converter 313
The converted signal is applied as a control voltage to the VCO (variable) of the voltage controlled oscillator 32, and its oscillation frequency fs is varied to set the sample clock fs of the shift register 1.

Below is the signal processing circuit 3 of sample clock control loop 3.
1 shows the calculation algorithm of the CPU 312 of No. 1. ■D/
Output O to the A converter 313 and initialize it. ■A/D
The input value νi from the converter 311 is sampled N times at the optimal timing obtained by the timing recovery circuit 8.

(2) Find the cumulative distribution for the N data values V obtained.

(2) The cumulative distribution has two peak values corresponding to the eye pattern aperture. Let these be V o and V t, respectively.
The absolute value of the difference Δν0=vH−vL is determined.

(2) Increment or decrement the output value ΔvO to the D/A converter 313.

(2) Repeat steps (2) to (2) to obtain the value ΔVK=VM-VL.

■ The difference from the previous sampling value ΔV K-1 is positive Δ
If VK-ΔV K-1>0, return to ① and continue the same operation; if negative ΔvK-ΔV X-1<0, return to ② and perform the opposite operation.

The CPU 312 repeats the above calculation and controls the oscillation frequency f of the voltage controlled oscillator 22 so that the ση of the eye pattern is maximized. and ■A/D converter 31
The number of samples N for sampling the input 4fl Vi from 1 is such that the output value from the CPU 312 to the D/A converter 313 fluctuates due to high-speed fading, and the VCO oscillation frequency f of the voltage controlled oscillator 32 does not fluctuate. Set the number to be large enough to obtain an appropriate convergence time.

In the embodiment of the third invention shown in FIG. 4, the stage number selection loop 4 includes a signal processing circuit 41 that is the same as the signal processing circuit 31, a selection circuit 42 that selects the shift output of an intermediate stage of the m-stage shift register l, and a multiplier. 5 and a low-pass filter 6, and the output of the arithmetic unit CPU 412 of the signal processing circuit 41 is used to select m stages of shift register 1
Since the shift output in the middle stage of is selected by the m-to-l selector of the selection circuit 42, the shift register 1 is selected so that the low frequency component of the output of the low-pass filter 6 always satisfies the predetermined relational expression (6) of delay detection. The delay WT (,·m/fs) is set.

The algorithm for controlling the selection port 842 by the output of the arithmetic unit CPU 412 of the signal processing circuit 41 to select the shift output in the middle stage of the shift register l and switching it so that the eye pattern aperture is maximized is as shown in FIG. This is similar to the embodiment of the second invention.

As described above, in any of the embodiment of the first invention shown in FIG. 2, the embodiment of the second invention shown in FIG. 3, and the embodiment of the third invention shown in FIG. Even if the oscillation frequency ωL of the receiving local oscillator 20 that converts the frequency of the received signal R(t) of the PLL circuit 2. Since the delay amount T of the shift register 1 is varied and set by either the sample clock control loop 3 or the stage number selection loop 4 so as to satisfy the predetermined relational expression (6) for delayed detection, the output of the multiplier 5 can be demodulated. The eye pattern aperture does not deteriorate, and the optimum demodulation characteristics of PSK demodulation can always be obtained without any problem.

Although the above embodiments have been described with respect to two-phase PSK demodulation, it goes without saying that the present invention can also be applied to multi-phase PS demodulation.

〔Effect of the invention〕

As explained above, according to the present invention, in the delay detector of the receiver used for PSK demodulation, even if the oscillation frequency of the local oscillator for frequency conversion of the receiver fluctuates, the eye pattern of the demodulated output deteriorates. Therefore, it is possible to obtain the effect that a PSK modulated mobile radio receiver always has optimal demodulation characteristics.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of a delay detection circuit according to the present invention. FIG. 2 is a block diagram showing the configuration of a delay detection circuit according to an embodiment of the first invention. FIG. FIG. 4 is a block diagram showing the configuration of a delay detection circuit according to an embodiment of the invention. FIG. 4 is a block diagram showing the configuration of a delay detection circuit according to a third embodiment of the invention. FIG. 5 is a block diagram of a conventional delay detection circuit. 6 is a demodulation eye pattern for explaining the operation of a conventional delay detection circuit, and FIG. 7 (a), (b), (C), and (d) are the first
FIG. 2 is an explanatory diagram for explaining the invention in detail. In the figure, 1 is a delay shift register, 2 is a PLL circuit, 21 is a phase comparator, 22 is a voltage controlled oscillator, 3 is a sample clock control loop, 31 is a signal processing circuit, 311 is a to/D converter, and 312 is a CPU, 313 is a D/A converter, 32
4 is a voltage controlled oscillator, 4 is a stage selection loop, 41 is a signal processing circuit, 411 is an A/D converter, 412 is a CPU, 4
2 is a shift stage number selection circuit, 5 is a multiplier, 6 is a low-pass filter, 7 is a discriminator, 8 is a timing recovery circuit, 10 is an antenna, 20 is a local oscillator, and 30 is a mixer. \0 (d) Kuimuchi v-) Explanatory diagram of Honmeimei's 1st Umei Daibon 4J'l Figure 7 (A-2)

Claims (1)

[Claims] 1. The received signal (Rin) obtained by mixing the received radio frequency PSK modulated signal with the output of the local oscillator (20) of the oscillation frequency ω_L and converting the frequency is Multiply (5) with a signal delayed by an integer multiple, extract only the low frequency component with a low-pass filter (6), identify (7) at the optimal timing reproduced by the data timing regeneration circuit (8), and process the data. In the delay detection circuit of the PSK demodulator to be reproduced, a shift register (1) is used as a means for delaying transmission data, and a phase comparator that compares the phase of the input (Rin) of the shift register and the output (k) of an intermediate stage. The voltage controlled oscillator (22) of the PLL circuit (2) is provided with a PLL circuit (2) that controls the oscillation frequency fs of the voltage controlled oscillator (22) that supplies a sample clock to the shift register based on the output error of the PLL circuit (21). The output of the oscillation frequency fs of the local oscillator (20) is used as the sample clock of the delay shift register (1).
1. A delay detection circuit characterized in that said shift register (1) always delays a received signal (Rin) by a predetermined time T even if the oscillation frequency ω_L of ) changes. 2. The received signal (Rin), which is frequency-converted by mixing the received radio frequency PSK modulated signal with the output of the local oscillator (20) of oscillation frequency ω_L, is delayed by an integer multiple of one symbol time of the transmission data. The signal is multiplied (5), only its low frequency components are extracted with a low-pass filter (6), and the data is identified at the optimal timing at which the reproduced eye pattern aperture (8) is maximized (7). In the delay detection circuit of the PSK demodulator that reproduces data, a shift register (1
), the low frequency components extracted by the low-pass filter (6) are encoded, read into the arithmetic unit CPU, and sampled N times at the optimal timing obtained by the timing recovery circuit (8), resulting in N samples. Based on the D/A conversion output of the signal processing circuit (31), which calculates the absolute value of the difference between two peak values of the cumulative distribution of data and repeats addition and subtraction of the output value depending on the sign of the difference between the absolute value and the value at the time of previous sampling. The shift register (
Voltage controlled oscillator (3) that supplies the sample clock to (1)
2) includes a sample clock control loop (3) for controlling the oscillation frequency fs of the sample clock control loop (3), and uses the output fs of the voltage controlled oscillator (32) of the sample clock control loop (3) as the sample clock of the shift register (1). Therefore, even if the oscillation frequency ω_L of the local oscillator (20) changes, the shift register (
A delay detection circuit characterized in that 1) delays a received signal (Rin) by a predetermined time T. 3. The received signal (Rin), which is frequency-converted by mixing the PSK modulated signal of the received radio frequency with the output of the local oscillator (20) of oscillation frequency ω_L, is delayed by an integral multiple of the time of one symbol of the transmission data. The signal is multiplied (5), only its low frequency components are extracted with a low-pass filter (6), and the data is identified at the optimal timing at which the reproduced eye pattern aperture (8) is maximized (9). In the delay detection circuit of the PSK demodulator that reproduces data, the low frequency components extracted by the low-pass filter (6) are encoded and read into the arithmetic unit CPU, and the timing regeneration circuit (8)
Sampling is performed N times at the optimal timing obtained by , and the absolute value of the difference between the two peak values of the cumulative distribution of the obtained N sample data is determined and output based on the sign or negative of the difference between the absolute value and the value at the time of previous sampling. A stage number selection loop (42) comprising a selection circuit (42) that selects the shift output of the intermediate stage of the shift register (1) so that the eye pattern aperture is maximized by the output of the signal processing circuit (41) that repeats addition and subtraction of values. 4), and even if the oscillation frequency ω_L of the local oscillator (20) fluctuates due to the shift output selected by the selection circuit (42) of the stage number selection loop (4), the shift register (1) always maintains the predetermined time T. A delay detection circuit characterized in that it delays a received signal (Rin) by .