JPH02192760A - Excess voltage absorbing circuit for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively protect the first stage of an input circuit by a method wherein, in a semiconductor integrated circuit, an excess voltage absorbing means is arranged between each of an input line, a plurality of power supply lines and ground lines. CONSTITUTION:When a first stage input circuit 3 and an internal circuit 4 are connected with different power supply lines L1, L3 and ground lines L2, L4, a PMOSTr 11 and a NMOSTr 12 are arranged between the input line L5 and the power supply line L3 and the ground line L4, in addition to the conventional PMOSTr 1 and NMOSTr 2. According to this constitution, when an excess voltage is applied to an external terminal 5 in the manner in which any power sources of the positive power supply lines L1, L3, and the ground lines L2, L4 as a reference, its discharging route is surely present, and the excess voltage is discharged to any of the power supplies. As a result, the first stage input circuit 3 can be protected from the destruction caused by the excess voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an overvoltage absorption circuit for a semiconductor integrated circuit device that absorbs an overvoltage applied to an external terminal to protect an internal circuit. The present invention relates to an overvoltage absorption circuit for a semiconductor integrated circuit device that is supplied with power from a power supply line.

[Prior Art] In a semiconductor integrated circuit device, when multiple power supply voltages are required due to the operation of the circuit, or when multiple power supply voltages are required,
There are cases where it is necessary to separate the power supply line or the ground line for reasons of ground line noise countermeasures.

In such a case, the semiconductor integrated circuit is provided with a plurality of separated power supply lines or ground lines, and the power supply voltage is applied to the internal circuit from the plurality of power supply terminals or ground terminals via these power supply lines or ground lines. We are trying to supply it.

As a typical example, FIG. 2 shows a configuration example of a semiconductor integrated circuit provided with two power supply lines and a ground line. In this circuit, the first input stage circuit 3 and the internal circuit 4 are connected to different power supply lines. That is, the input first stage circuit 3 consisting of transistors 7 and 8 connected in a complementary pair is connected to a first power supply line Ll and a first ground line L2, and is supplied with a power supply VDDI and a ground V5gl through these. It becomes. In addition, transistors 9 connected in a complementary pair
．． 10 is connected to a second power supply line L3 and a second ground line L4, and is connected to a power supply VDD via these
2 and ground V! is2 is supplied.

The reason why the power supply and ground supplied to the input first-stage circuit 3 and the power supply and ground supplied to the internal circuit 4 are separated in this way is that the power supply V generated by the operation of the internal circuit 4 or the output buffer (not shown) DD2 and ground V ss
This is to prevent the fluctuation of 2 from being transmitted to the input first stage circuit 3 and the input voltage margin of this input first stage circuit 3 from deteriorating.

By the way, conventionally, in this type of CMO3 semiconductor integrated circuit device, an overvoltage absorption circuit 6 as shown in FIG. 2, for example, has been used as a protection circuit against static electricity and other surge voltages applied to the input terminal 5. There is.

This overvoltage absorption circuit 6 has a source and a gate both connected to a power supply line L1, and a drain connected to an input line L5 that connects an input terminal (external terminal) 5 and an input part of the input first stage circuit 3.
A P-channel MOS transistor 1 connected to the transistor 1, and an N-channel MOS transistor 2 whose source and gate are both connected to the ground line L2 and whose drain is connected to the input line L5 together with the train of the transistor 1. There is. Transistor 1 has a voltage of -15 [V] or less at its drain with its source as a reference, and transistor 2 has a voltage of +15 [V] at its drain with its source as a reference.
When a higher voltage is applied, punch-through functions to bring the source and train into a conductive state.

The conventional overvoltage absorption circuit 6 configured as described above uses the ground VssI as a reference when a surge voltage such as positive static electricity is applied to the input terminal 5, as a punch-through current of the transistor 2, and as a punch-through current of the transistor 2. When a negative surge voltage is applied, the surge voltage is discharged to the ground VSS+ as a channel current of the transistor 2 through the transistor 2 and the ground line L2. On the other hand, with reference to the power supply VDDI, when a positive surge voltage is applied to the input terminal 5, the channel current of transistor 1 is applied, and when a negative surge voltage is applied, the punch-through current of transistor 1 As a result, the surge voltage is discharged to the power supply VDDI via the transistor 1 and the power supply line. In this way, the surge voltage applied to the input terminal 5 is transferred to the power supply V001 through the transistor 1 and the transistor 2, respectively.
and ground VssI, the input first stage F
Destruction of the gate oxide films and the like of the transistors 7 and 8 constituting #13 can be prevented.

[Problems to be Solved by the Invention] The conventional overvoltage absorption circuit described above has, for example, a power supply VDDI and a ground ■ss! on the power supply line and the ground line L2, respectively. In a state where V is not applied, that is, in a floating state, the power supply V
When a surge voltage is applied to the input terminal 5 using DD2 or the ground Vs52 as a reference, it is discharged to the power line or the ground line L2 through the transistors 1 to 1 or the transistor 2; Since the ground line L2 is in a floating state, it can absorb only a small amount of surge charge corresponding to its parasitic capacitance. In addition, input terminal 5
Since there is no current path between the power supply VDD2 and the ground line Vs5□, most of the static electricity applied to the input terminal 5 is applied to the gates of the transistors 7 and 8 that constitute the input first stage circuit 3.

As a result, the transistors 7 configuring the input first stage circuit 3.
This leads to destruction of the gate oxide film of transistor 1.
and a power line L1 and a ground line L2 via the transistor 2.
There is a problem in that the discharged and accumulated charge causes breakdown of the junction between the source and substrate of the transistors 7 and 8, or breakdown of the insulating film between the input line L5 and the substrate.

The present invention has been made in view of such problems, and includes:
In a semiconductor integrated circuit device in which multiple circuits are connected to different power supply lines and ground lines, sufficient circuit protection is provided against overvoltage applied between the input terminal and any of the power supply lines or ground lines. An object of the present invention is to provide an overvoltage absorption circuit for a semiconductor integrated circuit device that can be used in a semiconductor integrated circuit device.

[Means for Solving the Problems] An overvoltage absorption circuit for a semiconductor integrated circuit device according to the present invention includes:
A first circuit connected between a first positive power line and a first negative power line, the input part of which is connected to an external terminal, and a second positive power line and a second negative power line. Provided on an input line connecting the input section of the first circuit and the external terminal in a semiconductor integrated circuit device having a second circuit connected therebetween, the input line absorbs an overvoltage applied to the external terminal. In the overvoltage absorption circuit of a semiconductor integrated circuit device, between the input line and at least one of the first positive power supply line and the first negative power supply line, and between the input line and the second positive power supply line and the The device is characterized in that it includes means that is connected to at least one of the second negative power supply lines and that conducts when an overvoltage is applied to the external terminal.

[Function] According to the present invention, not only between the input line connecting the external terminal and the input section of the first circuit and the first positive power line and the negative power line, but also between the input line and the second positive power line Means for absorbing overvoltage is also provided between the power supply line and the negative power supply line. This overvoltage absorbing means becomes conductive when an overvoltage is applied to the external terminal, and acts to form a charge discharge path with the first circuit or the second circuit. Therefore, even if overvoltage is applied to the external terminal with reference to either the first positive power supply line, the second positive power supply line, the first negative power supply line, or the second negative power supply line, the discharge path will always be Since the first circuit exists and is discharged to either power source, it is possible to prevent the first circuit from being destroyed due to overvoltage.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an example of a circuit configuration to which an overvoltage absorption circuit according to an embodiment of the present invention is applied. The difference from the conventional circuit shown in FIG. 2 is that an overvoltage absorption circuit 16 is connected between the input line L5 connecting the input terminal 5 and the input part of the input first stage circuit 3, the power supply line L1, and the ground line L2. In addition to the P-channel MO3) transistor 1 and the N-channel MOS transistor 2 provided in the input line L5 and the power supply line L
3 and the ground line L4, respectively, a P-channel M○S transistor 11 and an N-channel MO9)-transistor 12 are newly provided. That is, the source and gate of the L transistor 11 are both connected to the power supply VDD2 via the power supply line L3, and its drain is connected to the input line connecting the input terminal 5 and the input part of the input first stage circuit 3. There is. In addition, both the source and gate of the N-channel MO3) transistor 12 are connected to the ground V s via the ground line L4.
s2, and its train is connected together with the drain of transistor 11 to input line L5. The transistor 11 has a drain voltage of -15[V with respect to its source.
] or below, and when a voltage of +15 [V] or more is applied to the drain of the transistor 7 with respect to the source, the transistor 7 functions so that the source and drain are electrically connected by punch-through. Further, since the other components are the same as those of the conventional example shown in FIG. 2, their explanation will be omitted.

Next, the operation of the circuit of this embodiment configured as described above will be explained.

Transistor 1 and transistor 2 operate in the same manner as in the conventional example. That is, power supply VDDI or ground ■55. A surge voltage, for example, positive static electricity, applied to the input terminal 5 with reference to , is discharged as a punch-through current of the transistor 2 with respect to the ground vssl, and as a channel current of the transistor 1 with respect to the power supply VDDI. Further, the negative surge voltage applied to the input terminal 5 is converted into a channel current of the transistor 2 with respect to the ground Vssl, and the negative surge voltage is applied to the power supply Vssl.
It is discharged to DD1 as a punch-through current of transistor 1. As a result, the surge voltage applied to the input terminals with reference to the power source VoD or ground VSSI is suppressed to below the gate oxide film breakdown voltage of the transistors 7 and 8 constituting the input first stage circuit 3, and the surge voltage applied to the input first stage circuit 3 can be prevented from being destroyed.

In addition, the surge voltage applied to the input terminal 5 with reference to the power supply VDD2 or the ground Vgg By functioning in the same manner as the transistor 1 for voot, it is discharged to the power supply voa2 or the ground ss2, and damage to the input first stage circuit 3 due to surge voltage can be prevented.

Here, when the input terminal 5 is connected to the power source Voos or the power source VDD2 as a reference, if only the channel current or punch-through current of the transistor 1 or the transistor 11 is applied, the power source VDDI
Alternatively, if a large surge voltage that cannot be fully discharged is applied to the power supply DD2, the excess voltage is discharged to the ground line L2 or L4 by the channel current or punch-through current of the transistor 2 or transistor 12, respectively. Ru.

As a result, the potential of the ground line L2 or the ground line L4 increases, but the potential of the transistor 78 connected between the power line L1 and the ground line L2 and forming the input first stage circuit 3 or between the power line L3 and the ground line M L4 The charge accumulated in the grounding line L2 or the grounding line L4 is discharged to the power line L1 or the power line L3, respectively, by the channel current and punch-through current of the transistors 9, 10, etc. connected between the ground line and the internal circuit 4, and constitutes the internal circuit 4. Ru.

Therefore, from input terminal 5 to power supply V 001 and power supply VDD
For transistor 1, the discharge path to transistor 2 is through transistor 2 and input first stage circuit 3, and for transistor 11, it is through transistor 12 and internal circuit 4.
There are parallel paths through transistors 1 and 11.
If not installed, these paths will discharge to the power supply V DDI and the power supply VDD□, respectively.

Similarly, input terminal 5 is connected to ground V 551 or ground VS
Based on S□, transistor 2 or transistor 1
2 channel current or punch-through current only to ground Vs
When a large surge voltage that cannot be fully discharged is applied to sl or ground VSS2, the excess voltage is applied to the path from transistor 1 to ground V551 via input first stage circuit 3, or from transistor 11 to internal circuit 4. is discharged to ground v sst and ground vssz by a path to ground VSS□ through the ground VSS□.

As is clear from the above description, transistor 1 and transistor 11, transistor 1 and transistor 12
, transistor 2 and transistor 11, and transistor 2 and transistor 12, a discharge path is formed between input terminal 5 and each power supply and each ground, and the surge withstand voltage can be improved. , as in this embodiment, transistors 1 and 2 and transistor 11
By providing all of the above characteristics, the discharge capacity can be further improved. As a result, surge charges such as static electricity and noise can be quickly moved, the power supply potential and ground potential can be rapidly stabilized, and the withstand voltage for surges such as static electricity can be greatly improved.

Note that the threshold voltage and punch-through start voltage of the P-channel MO transistor 1.2 and the N-channel MOS transistor 11, 12 described above can be changed by modifying the manufacturing process, and the discharge capacity can be changed depending on the purpose. can be adjusted and used.

The present invention also provides a P-channel MOS transistor 1.2.
By appropriately adding discharge means corresponding to the N-channel MOS transistors 11 and 12, the present invention can be applied to a semiconductor integrated circuit device having an arbitrary number of power supplies and grounds.

[Effects of the Invention] As explained above, the present invention prevents surge voltage between the input line connecting the input part of the input first stage circuit and the input terminal and at least one of the power supply and ground of the plurality of power supply/ground line pairs. A discharge path is provided. Therefore, even if a surge voltage is applied to the input terminal with reference to either power supply or ground, the surge voltage can be discharged to either power supply or ground, and the input first stage circuit can be protected from surge voltage such as static electricity. can be effectively protected.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of application of an overvoltage absorption circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an application example of a conventional overvoltage absorption circuit. 1.7, 9, 11. P channel MO3) transistor, 2
, 8, 10, 12. N-channel MOS transistor, 3
; Input first stage circuit, 4; Internal circuit, 5; Input terminal, 6, 1
6; Overvoltage absorption circuit, LlL; Power line, L2. L4
, ground wire, VDDIVooz; power supply, V 551 V
55□; Grounding applicant: NEC IG Microcomputer System Co., Ltd.

Claims (1)

[Claims] (1) A first circuit connected between a first positive power line and a first negative power line, the input part of which is connected to an external terminal, and a second positive power line and a second negative power line. The second wire connected between
The first circuit in the semiconductor integrated circuit device having a circuit of
In the overvoltage absorption circuit of a semiconductor integrated circuit device, which is provided on an input line connecting an input section of the circuit and the external terminal, and absorbs an overvoltage applied to the external terminal, the input line and the first positive power supply line and at least one of the first negative power supply line, and between the input line and the second negative power supply line.
Overvoltage absorption for a semiconductor integrated circuit device, characterized in that the device is provided with a means connected between the positive power supply line and at least one of the second negative power supply line, and conductive when an overvoltage is applied to the external terminal. circuit.