JPH02188863A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To quickly recover the fault of a CPU by executing a process request given to the faulty CPU after transferring this request to a nondefective CPU at occurrence of the CPU fault. CONSTITUTION:A mailbox control table 26, a 1st queue pointer 24a, and a 2nd queue pointer 24b are produced in a shared memory 6 by the function of a system controller SCM 100. When the SCM 100 detects the fault of a 2nd CPU 102, the SCM 100 checks the contents of a 1st queue in terms of the CPU 102 and then checks the presence or absence of another CPU that performs the same process as long as a 1st communication buffer 22a connected to the pointer 24a contains a message. If the presence of the CPU is confirmed, the process request of the faulty CPU 102 is connected to the queue of a normal CPU, e.g., a 3rd CPU 103. As a result, the process request of the faulty CPU is succeeded by a normal CPU and executed. Thus the CPU fault can be quickly recovered.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multiprocessor system in which a plurality of processors communicate with each other to execute predetermined processing.

[Conventional technology]

The purpose of a multiprocessor system is to divide the system functions and assign them to dedicated processors for high-speed processing, and by arranging multiple processors with similar functions, the system can be used in the event of a failure of some processors. The goal is to achieve high reliability of the system by performing a back-amplification. In a multiprocessor system, communication between processors is essential, and conventionally there have been the following types of communication. FIG. 5 is a block diagram showing a conventional multiprocessor system disclosed in, for example, Japanese Patent Publication No. 62-39789, and FIG. 6 is an explanatory diagram showing an outline of communication between the processors. In the figure, 1 is a high-speed bus, 2 to 5 are processors each equipped with a dedicated function and connected to the high-speed bus l,
2 is a job processor (hereinafter referred to as JOBP), 3 is a file control processor (hereinafter referred to as FCP),
4 is an input/output device control processor (hereinafter referred to as 10P), and 5 is a communication control processor (hereinafter referred to as CCP). In addition, 7 is the FCP
3 is a file connected to and controlled by the l0P4, 8 is a ring bus connected to the l0P4, and 9 is a plurality of input/output devices connected to the ring bus 8 and controlled by the l0P4 (hereinafter referred to as I10). It is. Furthermore, 10 is a communication line controlled by the CCP 5, and 11 is another system connected via this communication line 10. Further, 22 is a communication buffer that stores processing requests from each processor, 23 is a device control table that records the usage status of the above-mentioned 109, 24 is a queue pointer for inter-processor communication for l0PJ, 25 is JOB
Queue pointer for interprocessor communication for PZ. These communication buffer 22, device control table 23, and each queue pointer 24, 25 are all set in the shared memory I76. Next, the operation will be explained. Here, as an example, communication between processors in input/output execution control between 10P4, which drives each 1109 and executes interrupt processing, etc. via ring bus 8, and JOBP2 will be described. Here, in FIG. 6, solid line arrows indicate the flow of data, and broken line arrows indicate the flow of control signals. In JOBP2, which processes a user task, control information necessary for input/output execution is created in the communication buffer 22 by an input/output request macro instruction issued by the user task, and then l
Queue pointer 2 for interprocessor communication for 0P4
4 ■, and performs inter-processor communication side input to l0P4 ■. Thereafter, the user task waits for the human output execution to be completed in order to synchronize the program processing and the input/output execution processing, and control is transferred to another task. In 10P4, in response to the inter-processor communication input from JOBP2, the requested 110 device number is retrieved from the communication buffer 22 connected to the queue pointer 24 to the own processor, and the device number is stored in the device control table (DVCB). 23 to check whether l109 is in use. If l109 is free, communication buffer 22
■ Create input/output operation commands and data to be passed to T109 from the control information of ■, and send a start command to T109■
. In l109, after the input/output operation is completed, an input/output completion report is returned to 10P4 (■). 10P4 receives the input/output completion report ■ from l109, stores the input/output result in the communication buffer 22, and connects the communication buffer 22 to the queue pointer 25 for inter-processor communication for JOBP Z.■ , JOBP 2
For this purpose, the inter-processor communication side is involved.■. J received inter-processor contact from l0P4.
In OBP 2, the queue pointer 25 to the own processor
The communication buffer 22 connected to is deleted from the queue (1), the input/output processing result is returned as a return code to the input/output request macro instruction issuing task, and the task is released from the waiting state for input/output execution to be completed. This completes a series of I10 input/output controls. In this way, all inter-processor communication between JOBP 2 and each dedicated processor can be performed by the procedure shown in FIG. Here, in such a multiprocessor system, multiple JOBPs are processed for the purpose of improving processing capacity and reliability.
2 may be used to configure the system. At this time, in order to prevent the entire system from becoming inoperable due to a failure in one JOBP, processor configuration control is required to disconnect the failed JOBP from the system, reconfigure the system with the remaining JOBPs, and continue processing. . Processor failures are generally detected by timeout processing, in which a processing request is not reported as completed even after a certain period of time has elapsed. 1=6 The process of disconnecting the faulty JOBP is as follows. (1) Processing of the task being executed in the faulty JOBP is aborted. (2) Deletion of the communication buffer that stores the processing requests issued by other processors for the failed JOBP. (3) Delete the communication buffer that stores processing requests issued from the faulty JOBP to other processors. (4) Stopping the failed JOBP. The processes in items (2) and (3) above can be performed by the communication buffer 22 deletion method described above. That is, the process in item (2) is performed by deleting the communication bumper 22 connected to the queue pointer 25 for inter-processor communication for the faulty JOBP, and the process in item (3) is performed by deleting the communication bumper 22 connected to the queue pointer 25 for inter-processor communication for the failed JOBP. By searching the communication buffer 22 that has been sent from the queue pointer 25, which is also set on the shared memory 6, and checking whether the processor number indicated there matches the processor number of the failed JOBP, This is achieved by detecting whether each communication request is for a faulty JOBP and deleting the communication request issued by the faulty JOBP.

[Problem to be solved by the invention]

Conventional multiprocessor systems are configured as described above, so when a processor failure occurs, the communication buffer 22 that stores processing requests related to the failed processor must be deleted, and recovery from the failure occurs. There was a problem in that the recovery process took a long time. This invention was made in order to solve the above-mentioned problems.The multiprocessor system according to the present invention provides a multiprocessor system that can quickly recover from the failure when a processor failure occurs. The system controller includes a system controller that, upon detecting a faulty processor, connects a processing request related to the faulty processor to a queue of processing requests of other normal processors that perform the same type of processing.

[For use]

In the multiprocessor system according to the present invention, a system controller that detects a faulty processor connects a processing request related to the faulty processor to a processing request queue of other normal processors that perform the same type of processing. Allow another normal processor to take over execution of the processing request.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a high-speed bus, and 6 is a shared memory, which are the same or equivalent parts to those in the conventional system denoted by the same reference numerals in FIG. 5, and detailed explanations thereof will be omitted. Also, 10
1 to 104 are a plurality of processors (hereinafter referred to as CPUs) connected to the high-speed bus 1, and in this embodiment, to simplify the explanation, first CPUI O1 to fourth cp
There are 4 u104 units. 100 is connected to the high-speed bus 1 and determines the normality of each CPUI 01 to 104, and when a faulty CPU is detected, the faulty CPU
A system controller (hereinafter referred to as SCM) connects processing requests related to the PU to a queue of processing requests of other normal CPUs, and 110 is an I10 connected to the high-speed bus 1.
The controller 111 is this I10 controller 110
Ilo is controlled by Ilo. FIG. 2 is an explanatory diagram showing the connection of communication buffers to queues in the shared memory 6. In the figure, 22a is a first communication buffer, 22b is a second communication buffer, 24a is a first queue pointer to which the first communication buffer 22a is connected, and 24b is a first queue pointer to which the second communication buffer 22b is connected. 26 is a mailbox management table for managing mailboxes. Next, the operation will be explained. First, the functions of SCMloo will be explained. SCMloo allocates work to each CPU10I to 104. SCMI OO has a function of reading a program from 110111 and loading it to CPU 10I-104, thereby allocating work to each CPUI 01-104. Now, it is assumed that work A is given to the first CPUI O1, work B is given to the second CPUI 02 and third CPUI 03, and no work is given to the 40th CPU. SCMloo generates a processing request queue in the shared memory 6 in response to requests from each of the CPUs I0I to 104. The processing request source CPU requests the SCM 100 to generate a mailbox, and the processing request destination CPU requests the SCM 100 to generate a queue related to the mailbox. Now, the first CPUI
A request to create a mailbox was made from 01, and
Assuming that the second CPU 102 and the third CPU 103 request generation of a queue for the mailbox, the mailbox management table 26 and the first queue pointer 24a are stored in the shared memory 6 by the action of SCMloo. , and a second queue pointer 24b are generated. SCMloo is also responsible for sending and receiving processing requests (messages). That is, SCMloo
When receiving a message transmission request from each CPUI 01 to 104, it stores the message in the communication buffers 22a and 22b in the shared memory 6, and sends the message to each CPUI 01 to 104.
4, the communication buffers 22a and 2
Extract the contents of 2b and select the corresponding CP from 101 to 104.
Give to U. Next, actual communication between processors in such a multiprocessor system will be explained. When the first CPUl0I requests SCMloo to send a message, SCMlo,0 sends the message to the first communication buffer 22a connected to the first queue pointer 24a or to the second queue pointer 24b.
The data is stored in the second communication buffer 22b connected to the second communication buffer 22b. Next, the second CPU 102 sends the message reception request to the SC
When done for Mloo, SCMloo is the first communication buffer 22a connected to the first queue pointer 24a.
The message is retrieved from the CPU 102 and passed to the second CPU 102. Further, the third CPU 103 sends a message reception request to
When done for CMloo, SCMloo is the second communication buffer 22 connected to the second queue pointer 24b.
The message is taken out from b and passed to the CPU 103. In this way, from the first CPUI O1 to the second CPU
Communication to U102 or third CPU 103 is performed. Next, processing at the time of failure will be explained. FIG. 3 is a flowchart showing the processing procedure. For example, assume that a failure occurs in the second CPU 102. SCMloo sequentially measures the health of each CPUI 01-104 (step 5T1), and when detecting a failure of the second CPUI O2, checks the contents of the first queue regarding this second CPU 102. As a result, the first communication buffer 2 connected to the first queue pointer 24a
If there is a message on 2a, check whether there are other CPUs that perform the same processing, and if there are, the 20th CPU 10 that caused the failure
2 processing request (message) is connected to the queue of a normal CPU, for example, the third CPUI 03 (step 5T).
3). That is, the message in the first communication buffer 22a is copied to the second communication buffer 22b connected to the second queue pointer 24b related to the normal third CPU 103. After that, the queue of the second CPU 102 that has caused the failure is deleted (step 5T4), and each CPUI O1
-1'04(7) When it is detected that all checks have been completed, the process ends (step 5T5). As described above, the processing request of the second CPUI O2 in which the failure has occurred is taken over and executed by the normal third CPU 103. Further, in the above embodiment, the processing request of the faulty CPU is handed over to another normally executing CPU, but this may be handed over to a standby cPU. FIG. 4 is a flowchart showing the processing procedure. Here, as described above, the fourth CPU 104 is a standby CPU, and normally does not perform any processing. SCMloo is the second CPU 102 in step STI.
When it is detected that a failure has occurred in the CPU, the presence or absence of a CPU on standby is detected (step 5T6). As a result, since the fourth CPU 104 is on standby, it is given the same work as the failed second CPU 102 (step 5T7). Next, the fourth CP waiting
After UI 04 makes a queue creation request (step 5T
8), connect the processing request of the failed second CPUI O2 to the queue of the fourth CPU 104 that replaces it (
Step 5T9). After that, the second failure C that caused the failure
The queue of the PU 102 is deleted (step 5T4), and the process is completed after checking that all CPUs have been checked (step 5T5). As a result of the above, the processing request of the second CPU 102 that has caused the failure is taken over and executed by the normal fourth CPU 104 that is on standby.

【Effect of the invention】

As described above, according to the present invention, when an abnormality occurs in a CPU, the abnormal CPU processing request is transferred to another normal CPU to continue execution, thereby providing a multiprocessor system that can quickly recover from the failure. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the connection of the communication buffer to the queue, and FIG. 3 is a flowchart showing the processing procedure in the event of a failure. , FIG. 4 is a flowchart showing the processing procedure at the time of failure according to another embodiment of the present invention,
FIG. 5 is a block diagram showing a conventional multiprocessor system, and FIG. 6 is an explanatory diagram showing an outline of communication between programs. 1 is high-speed bus, 6 is shared memory, 100 is SCM, 10
1 to 104 are CPUs, 22a and 22b are communication buffers,
24a and 24b are queue pointers. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A process comprising a plurality of processors and a shared memory whose contents can be commonly referenced and updated by each of the processors, and transmitted from the requesting processor to the requesting processor on the shared memory. A plurality of communication buffers that store request contents and a queue pointer that sequentially connects the plurality of communication buffers to form a queue structure are set, and the processing request is sent to the request source via the communication buffer. In a multiprocessor system in which communication is transmitted from the processor to the request destination processor, when the normality of each of the processors is sequentially determined and a faulty processor is detected, the communication buffer connected to the queue pointer regarding the faulty processor is 2. A multiprocessor system, comprising: a system controller for transferring said processing request stored in said processing request to said communication buffer connected to said queue pointer for other normal processors that perform the same type of processing.