JPH02184945A - Information processor - Google Patents

Abstract

PURPOSE:To shorten a time up to the reception of data by means of another processor by transferring the data from a buffer storing device to the other processor when the data required by the other processor are detected by means of the buffer storing device. CONSTITUTION:In a processor 1, which repeats the request of the data from another processor 2 to a main storing device 3, when the request data exist in a buffer storing device 12, the data are transferred from the buffer storing device 12 to the other processor 2. Consequently the data required by the other processor 2 can be transferred faster than they are read from the main storing device 3. Thus the time to receive the data by means of the other processor 2 can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Gokou E. The present invention relates to an information processing device, and particularly to an information processing device having a multiprocessor configuration.

Conventionally, this type of information processing apparatus has a multiprocessor configuration consisting of a processor 4 connected to a main storage device 3 and a processor 2 connected to the processor 4, as shown in FIG. It has become.

FIG. 5 is a diagram showing the operation of the information processing device having the multiprocessor configuration shown in FIG. 3. In FIG. When you request
The operation is shown when the requested data does not exist in the buffer storage device 22 (at the time of a miss).

If the requested data does not exist in the buffer storage device 22, the buffer storage device 22 transmits the request signal line 20.
2, the data is requested from the processor 4 connected to the main memory 3.

In the processor 4, the request adjustment circuit 43
, upon receiving a request from the WI storage device 22, the request adjusting circuit 43 receives the request from the II storage device 42 sent via the request signal line 204 (if the request from the arithmetic processing unit 41 via the signal line 203 is a mishit). (requests to the main memory 3) are adjusted, and these requests are ordered.

If there is no request conflict, the request adjustment circuit 43 requests data from the buffer storage device 22 to the main storage device 3 via the request signal line 205.

The data read from the main memory 3 is sent to the data distribution circuit 844 in the processor 4 via the request data line 206.
The data distribution circuit 44 selects the destination of the data.

In this case, the data distribution circuit 44 selects the processor 2 based on the request source identification signal sent from the request adjustment circuit 43 via the selection signal line 207, and selects the processor 2 via the request data line 208. Data is sent to 22. In the buffer storage device 22, the data is sent to the arithmetic processing unit 21 via a request data line 210.

Further, in the data distribution circuit 44, the request adjustment circuit 43
If the request source identification signal from the Mffi storage device 42 is indicated, the data is sent to the Mffi storage device 42 via the request data line 2.9.

Thereafter, the M'tM storage device 42 sends the data to the arithmetic processing device 41 via the request data line 211.

In such a conventional information processing device, when the processor 4 relays a data request from the processor 2,
The data was directly requested from the main storage device 3 without checking whether the data existed in the buffer storage device 42 of the processor 4.

Therefore, when the processor 4 is executing the program block A as shown in FIG.
In the case where processor 2 executes the program in area A2, that is, in the case where processors 2 and 4 simultaneously execute the program in area A2 on different data,
Although the program block A exists in the buffer storage device 3!42 in the processor 4, the processor 2
l! Program block A containing program A2 had to be read from main memory 3.

Therefore, since the processor 4 has to relay data requests from the processor 2 to the main storage device 3, there is a drawback that a large amount of time has to be spent before the processor 2 receives the program block A.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the prior art as described above. An object of the present invention is to provide an information processing device that can shorten the time required to receive the data.

An information processing device according to the present invention includes first and second processors each having a first and second buffer storage device, and a main storage device connected to the first processor. a processing device, a detection means for detecting whether data requested by a data request from the second processor to the main storage device exists in the first buffer storage device; and the detection means and means for transferring the data from the first buffer storage device to the second buffer storage device when the presence of the data is detected in the first buffer storage device. .

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, a processor 1 has a request signal line 10.
5 and the request data line 106 to the main storage device 3.
The processor 2 is connected to the request signal line 1.
02 and a request data line 108.

In the processor 2, when the arithmetic processing unit 21 requests data to the buffer storage device 22 via the request signal line 101, the buffer storage device 22 requests data from the arithmetic processing device 21.
The presence or absence of the data (hit or miss) is detected in response to a data request from , and if it is a hit, the data is transferred to the arithmetic processing unit 21 via the request data@110.

In addition, if there is a mishit, the request signal line 102
Request data by request data line 10
Request data line 1 transfers the data transferred by 8.
10 to the arithmetic processing unit 21.

A request adjustment circuit 13 in the processor 1 requests data from the processor 2 via a request signal line 102 and requests data from the processor 1 via a request signal line 103.
1, and when a conflict between them is detected, the requests are ordered and sent to the buffer storage device 12 via the request signal line 104.
Request data from .

The buffer storage device 12 receives the request signal! 11104 detects a hit or miss in the data in response to a request from the request adjustment circuit 13, and if the request is from the arithmetic processing unit 11, the data is transferred to the request data line 111. If the request is from the processor 2, the data is transferred to the data distribution circuit 14 via the request data line 112.

If there is a mishit, the request signal line 105 causes the main memory r! 1.3, and if the request is from the arithmetic processing unit 11, the data transferred from the main storage device 3 via the request data line 106 is received from the data distribution circuit 14 via the request data line 109, The data is transferred to the arithmetic processing unit 11 via the request data line 111, and if the request is from the processor 2, nothing is done to the data transferred from the main storage device 3 via the request data line 106.

The data distribution circuit 14 receives data transferred from the main storage device 3 via the request data line 10G or data transferred from the buffer storage device 12 via the request data line 112, and identifies the request source from the request adjustment circuit 13 via the selection signal line 107. Select the data transfer destination based on the signal.

That is, if the request source identification signal from the request adjustment circuit 13 indicates the arithmetic processing unit 11, the data is sent via the request data line 109 to &! ! If the request source identification signal from the request adjustment circuit 13 indicates the processor 2, the data is transferred to the buffer storage device 22 of the processor 2 via the request data line 108.

FIG. 2 is a diagram showing the operation of one embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

For example, when processor 1 is executing program block A as shown in FIG.
The operation in the case where the processor 2 executes the program in area A2, that is, in the case where the processor 1.2 simultaneously executes the program in area A2 on different data will be described below.

Processor 2 executes the program in area A2 according to interprocessor communication command A1 from processor 1.
When data is requested to the buffer storage device 22, the buffer storage device 22 detects whether or not the data exists in response to the request.

At this time, if the request results in a miss in the memory storage device 22, the buffer storage device 22 requests data from the processor 1 via the request signal line 102.

The request adjustment circuit 13 in the processor 1 sends the request from the processor 2 to the buffer storage device 12 if the data request from the processor 2 does not conflict with the data request from the arithmetic processing unit 11.

Since processor 1 is executing program block A in buffer storage device 12, request adjustment port F! 411
3 detects a hit in the data and transfers the data to the data distribution circuit 14 via the request data line 112.

When the data distribution circuit 14 receives the transfer data from the M'll storage device 12 via the request data line 112, since the request source identification signal from the request adjustment circuit 13 via the selection signal line 107 indicates the processor 2,
The data is transferred to the buffer storage device 22 of the processor 2 via the request data line 108.

In the processor 2, the program in area A2 is executed based on the data transferred to the buffer storage device 22.

Therefore, in the processor 2, since the program block A exists in the Mm storage device 12 of the processor 1, the program block A containing the program in the area A2 is not read out from the main storage device 3, as shown in FIG. , the program in area A2 can be executed faster than the conventional method shown in FIG.

In this way, in the processor 1 that relays a data request from another processor 2 to the main memory 3, if the data of the request exists in the buffer storage 12, the data is transferred from the buffer storage 12 to the other processor 1. By transferring the data to the processor 2 of the other processor 2, the data requested from the other processor 2 can be transferred faster than reading it from the main memory 3. time can be reduced.

As explained above, according to the present invention, data requested by a data request from another processor to the main memory is stored in the memory of the own processor connected to the main memory. requested data by detecting whether it exists or not, and transferring the data from the buffer storage to another processor when the presence of the data is detected in the H,area storage. When the data exists in a buffer storage device within the own processor connected to the main memory, the time required for other processors to receive the data can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the operation of an embodiment of the present invention, FIG. 3 is a block diagram showing the configuration of a conventional example, and FIG. 4 is a block diagram showing the configuration of a conventional example. FIG. 5 is a diagram showing an example of a program block including a program that can be microtasked, and FIG. 5 is a diagram showing the operation of a conventional example. Explanation of symbols of main parts 1.2...Processor 3...Main storage device 12.22...Buffer storage device 13...Request adjustment circuit 14. ...Data distribution circuit diagram 2

Claims (1)

[Claims] (1) a first buffer storage device each having a first buffer storage device and a second buffer storage device;
and an information processing device including a second processor and a main storage connected to the first processor, wherein data requested by a data request from the second processor to the main storage is a detection means for detecting whether or not the data exists in the first buffer storage device; and when the presence of the data is detected in the first buffer storage device by the detection means, the data An information processing apparatus comprising: means for transferring the data to the second buffer storage device.