JPH02168743A - Selective call communication system and receiver - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency in the case of sending same information by allocating a call signal used to call each paging receiver individually or in the unit of prescribed groups and a call signal to call lots of receivers simultaneously to independent frames respectively and sending the signals in time division. CONSTITUTION:A call number of a paging receiver inputted by a general individual is inputted to a collation circuit 7 via a public telephone line 3 and an input and output circuit 6. Moreover, a call number for offering information inputted from an information offer company is inputted to the collation circuit 7 via a private line and the input and output circuit 6. The collation circuit 7 sends the call number whose coincidence is detected to a signal processing circuit 9 and sends a different command to the input and output circuit 6 and the signal processing circuit 9 based on the call number subject to coincidence processing. The signal processing circuit 9 expands the call number from the collation circuit 7 into an address data and a frame data to generate an address code word corresponding to the address data and also to generate a message code word corresponding to the message data inputted from an information offer company or the like.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a selective call communication system and receiver.

[Prior art and its problems] Conventional selective call communication system, for example, POC3A as a call signal
In the selective paging communication system using the G code, paging receivers are divided into eight groups, and the paging signal transmitted from the wireless base station is also time-divisionally transmitted in eight frames corresponding to the grouping. The receiver receives a call only at the timing related to the frame corresponding to the group to which it belongs (i.e. receives the call in a time-sharing manner).
Furthermore, due to battery life concerns, the power is turned off at timings related to other frames in which there is no possibility that the paging receiver will be called.

By the way, in recent years, information providing companies that provide stock price information, gold market information, etc. using this selective call communication method are being established one after another. In the case of a call, the paging receivers of the subscriber receiving the information are generally distributed in each frame, so the information provider makes the call at each timing related to all eight frames, and transmits the same information in each frame. This results in extremely low transmission efficiency.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and provides a selective paging communication system with high transmission efficiency when transmitting the same information to a large number of paging receivers, and a paging receiver used in the method. The purpose is to provide.

[Summary of the Invention] The present invention is capable of generating a paging signal for paging each paging receiver individually or in a certain group, and a paging signal for paging a large number of receivers all at once, in separate frames. The key point is that the paging receiver is allocated a plurality of frame registers and at least l address registers corresponding to each frame register, in addition to transmitting data in one time division.

"Implementation N" The present invention will be specifically described below based on an embodiment shown in the drawings.

First, referring to FIG. 1, we will explain the POCSA used in this example.
The transmission signal format of the G code signal will be explained. 1st
Figure (A) shows the overall format, and the transmission signal is a preamble signal A and a plurality of batches B, C...
...It's getting better. Preamble signal A is for bit synchronization between the transmitting signal and the receiver. rlolol
576 consecutive bits are a repeating pattern of "1" and "'0" of "ol...". In addition, the same figure (B) shows the format of each batch mentioned above, and the synchronization code S
It consists of 8 frames from 1st to 8th.
One frame consists of two code words. Both the synchronization code SC and one code word have a 32-bit configuration, and the code word is divided into an address code word indicating a calling number and a message code word indicating a message. The address code word is shown in (C) of the same figure, and the message code word is shown in (D) of the same figure. The address code word is
The first bit is a message flag that distinguishes whether it is an address code word or a message code word. In the case of an address code word, this bit is '0'. The second to 19th bits are address bits that represent address data. 20. The 21st bit is a function bit indicating the display format and sound format, the 22nd to 31st bits are the BCH parity pit, and the 32nd bit is the even parity bit.The first bit of the message code word is the message flag and the message code. "Work" indicating a word is set, the 2nd to 21st bits are message bits representing message data, and the 22nd to 31st bits are BCH.
The 32nd parity bit is an even parity bit. Further, in the synchronization code word SC, 32 bits are a specific pattern.

The above-mentioned signal is a signal that selectively calls the paging receiver based on the address data of the address code word and the order of the frame in which the address code word is transmitted. Therefore, each paging receiver is assigned one address and one frame for receiving individual calls. Note that two addresses may be assigned as necessary. In this case, one address is used for normal individual calls, and the other address is used for emergency calls or simultaneous calls for a group of several paging receivers including the receiver to which the same frame as the receiver is assigned. Used for calling. Additionally, for paging receivers that have a contract to receive information provision services,
In addition to the addresses and frames for receiving individual calls, addresses and frames for receiving information providing services are further allocated. It is preferable that the frame for receiving the information providing service be the same frame even if there are many types of information to be provided.

More preferably, the frame for receiving the information provision service is a frame adjacent to the transmission timing of the synchronization code, that is, the first or eighth frame. With this selective calling communication system, it is possible to simultaneously call a large number of paging receivers that have contracted to receive information provision services and provide them with information. In addition, with paging receivers, even if you have a contract to receive multiple information services, you only need one frame to receive the information services.
It can save battery. When sending a message, an address code word is added to the beginning, and then a message code word of the required length is sent. Please note that transmission is 62.5m5 per word (
In order to reduce reception errors on the receiver side, the same content (address and message) is sent after a predetermined time.
For example, it will be retransmitted after 60 seconds.

FIG. 2 is a block diagram showing the system configuration of a base station in the wireless paging system. The telephone 1 and the personal computer 2 with communication functions are input terminals for general individuals to input the calling number of the paging receiver and a message to the paging receiver. These are connected to a base station control center 4 via a public telephone line 3. An information providing company 5 that provides various information to paging receiver owners is connected to the control center 4 via a dedicated line.

The control center 4 is equipped with an input/output circuit 6 having a built-in modem and a response circuit at the connection part with the public telephone line 3 and the private line. A calling number of a paging receiver inputted by an ordinary individual from a telephone 1 or a personal computer 2 is inputted to a verification circuit 7 via a public telephone line 3 and an input/output circuit 6. Further, a call number for providing information inputted from an information providing company is inputted to a verification circuit 7 via a dedicated line and an input/output circuit 6. The verification circuit 7 verifies the input calling number with the calling number stored in the subscriber memory 8. The calling numbers stored in the subscriber memory 8 include individual calling numbers assigned to each paging receiver, and information provision numbers assigned to each information provider or each type of information provided by the information provider. There is a calling number for. All call numbers for providing this information are assigned a call number whose frame data is the same when expanded into address data and frame data, for example, a call number whose frame data is "'8". During the verification process in the verification circuit 7, if the input calling number does not match any of the calling numbers stored in the subscriber memory 8, a command is sent to the response circuit in the input/output circuit 6. In addition, a message is sent to the calling party to the effect that the entered calling number is not registered. On the other hand, if the input calling number matches the calling number stored in the subscriber memory 8, the verification circuit 7
sends out the detected matching calling number to the signal processing circuit 9, and also sends different commands to the input/output circuit 6 and the signal processing circuit 9 based on the matching detected calling number.

For example, if the detected matching calling number is a calling number assigned to a tone-only paging receiver, the input/output circuit 6 will send the message ``Start calling.''

Please hang up and wait. A command is given to the signal processing circuit 9 to send a message such as j to the calling party, and a command to send a calling signal is given to the signal processing circuit 9. If the detected calling number is a calling number assigned to a display type paging receiver, a command is sent to the input/output circuit 6 to send a message such as "Please enter a message" to the calling party. is given to the signal processing circuit 9, and a command is given to the signal processing circuit 9 to process message data later input from the caller. In addition, if the detected calling number is a calling number for providing information, the information providing company sends a message or signal to the input/output circuit 6 indicating that the message (information to be provided) may be input. A command is given to the signal processing circuit 9 to process message data later inputted from the information providing company.

The signal processing circuit 9 expands the calling number from the verification circuit 7 into address data and frame data, and creates an atto1/scode word corresponding to the address data. It also creates a message code word corresponding to message data input from an information provider or the like. Note that if the message data cannot be stored in one message code word, a plurality of message code words are created. The address code word is transmitted to the transmitter 10 at any frame timing in the batch format shown in FIG. 1(B) based on the frame data,
The message codeword is transmitted to the transmitter IO successively following the address codeword. The transmitter 10 sends out the address code word and message code word sent from the signal processing circuit 9 as a radio signal from the antenna 11.

FIG. 3 shows the circuit configuration of an embodiment of a paging receiver used in the selective call communication method described in Section 1. That is, the configuration is such that the CPU 21 is at the center and the other circuit sections are connected to it. , C
PU21. controls each circuit section according to a built-in ROM program. 22 is the antenna, 23 is the 7 antenna 22
1, which is a receiving unit that demodulates the radio waves received by the receiver; i)-
The ROM 25 stores frame I/- frames and address data etc. assigned to the receiver, and transfers the stored frame data etc. to the decoder section 24 under the control of the decoder section 24.
Send to. The decoder section 24 decodes the received signal demodulated by the receiving section 23 based on the data from the ID-ROM 25, sends it to the CPU 21, and also switches the switch SW.
This is the circuit section that controls 2.

The switch SW2 is turned on/off by the decoder section 24.
Then, the power supply supplied from the power supply 26 to the receiving unit 23 via the switch SW + is interrupted. switch SW
+ is a manual switch that is turned on and off by the user's operation, and cuts off the power supply from the electric current A26 to the decoder section 24 and the like. The message memory 27 is a memory whose memory area is divided into a plurality of areas and stores received messages in different memory areas depending on the type of message. The switch circuit 28 is a circuit unit that includes a large number of switches and sends a switch input signal corresponding to an operated switch to the CPU 21.

The LED driver 29 is under the control of the CPU 21.
Points are deducted from D30 to notify that there is a call. The buzzer driver 31 controls the buzzer 32 under the control of the CPU 21.
and performs various notifications such as call notifications. Display section 3
3 is under the control of the CPU 21 and the message memory 27
This is a circuit section that displays received messages etc. stored in the .

FIG. 4 shows the structure of the decoder section 24 in detail. The bit synchronization circuit 40 inputs a received signal consisting of a bit string of l" and "o'' demodulated by the receiving section 23, and synchronizes this bit string with an internal clock generated by a timing control circuit 41, which will be described later. This circuit takes the synchronized bit string and sends the received signal as a synchronized bit string to the preamble detection circuit 42, the synchronization signal detection circuit 43, and the BCH correction circuit 44. The timing M valve circuit 41 includes an oscillation circuit, a 32-decimal bit counter, a 17-decimal word counter, etc., and generates a clock having the same frequency as the frequency of the received signal, as well as a preamble detection circuit 42 and a synchronization signal detection circuit 43. The decoder section 24 receives a detection signal and frame data set in frame registers 49 and 50, which will be described later, to control the timing of the entire decoder section 24, and determines the signal read timing and the operation order of each circuit section. The preamble detection circuit 42 is a circuit that detects the preamble signal A in the received signal, that is, the bit string from the beat synchronization circuit 40, and for example, continuously detects 8 bits.
When the repetition of 0'' and 1'' is detected, it is assumed that the preamble signal A has been detected, and a detection signal is sent to the timing control circuit 41. The synchronization signal detection circuit 43 is a circuit that detects the synchronization code SC in the received signal and sends the detection signal to the timing control circuit 41 and the SC mismatch counter 45, which will be described later. The BCH correction circuit 44 is shown in FIG.
) As shown in (D), BCH error correction processing is performed on the received signal to which the BCH parity code is added, and the corrected data is sent to the data processing circuit 66 and the AT/S comparison circuits 57 to 62. uncorrectable x, -,
If there is a knee, an error flag signal is sent. The SC mismatch counter 45 is configured by the timing control circuit 41
J count is increased by the carry output of the word counter in the synchronous signal detection circuit 43, and the counter reset by the detection signal of the synchronization signal detection circuit 43 is reset. This circuit sends a signal to the battery save signal decoder 46 when the set permissible number of synchronization deviations has been reached. The battery save signal decoder 46 is connected to the timing control circuit 41
, SC mismatch counter 45 or the CPU 21 to control the switch SW2 on and off.

The ID-ROM control decoder 47 outputs the CPU2! when the switch SWI is turned on. This circuit receives a signal sent from the ROM 25 and sends the signal to the ROM 25 to control it. The SC retry register 48, frame register 49.50 and address registers 51-56 are controlled by the ID-ROM control decoder 47.
This is a register that stores data sequentially sent from the D-ROM 25. That is, the SC retry register 48 indicates the allowable number of synchronization errors, the frame register 49 indicates the frame number related to individual calling of the paging receiver, for example, 2 (second frame), and the frame register 50 indicates the frame number for receiving information provision services, etc. A frame number related to simultaneous calling, for example 8 (eighth frame), is set, and the address registers 51 and 52 are registers in which addresses in frames related to the frame number set in the frame register 49 are respectively set. For example, the address register 51 is set with an address used when calling only the relevant receiver individually, and the address register 52 is
is set as an address used when calling a group of several receivers including the receiver at once. Note that the address registers 51 and 52 are controlled by the frame register 49 under the control of the timing control circuit 41, and send the set addresses to the address comparison circuits 57 and 58, respectively. address register 53
-・56 indicates that the address in the frame related to the frame number set in the frame register 50 is
Each register is set to receive contract information, for example, address register 53 receives gold market information, address register 54 receives company A stock price information, address register 55 receives weather forecast for a specific region, and address register 56 receives information on horse racing. The respective addresses are set. Note that the address registers 53-56 are controlled by a frame register 50 under the control of the timing control circuit 4, and send the set addresses to address comparison circuits 59-62, respectively. Address comparison circuit 57
~62 are controlled by the timing control circuit 41, and BCH
The address sent from the correction circuit 44 is compared with the addresses sent from the address registers 51 to 56, respectively, and if they match, a match detection signal is sent to the address message decoder 64 via the OR gate 63. This circuit also sends out the coincidence detection signal and the 2-bit function bit data added to the detected address data to the address processing circuit 65.The output of the OR gate 63 is sent to the battery as a reception continuation command signal. It is also sent to the save signal decoder 46.

The address message decoder 64 is a circuit that receives a signal sent through the OR gate 63, first sends an operation command signal to the address processing circuit 65, and then, after a certain period of time has elapsed, sends an operation command signal to the data processing circuit 66. be. The address processing circuit 65 operates upon receiving the operation command signal from the address message decoder 64, and the address type related to the address comparison circuit (any of address comparison circuits 57 to 62) that is sending the coincidence detection signal at that time. This is a circuit that converts data and function data into parallel bit signals used by the CPU 21 and sends them to the CPU 21. For example, a total of 8 bits of parallel signals consisting of 6 bits output from each address comparison circuit and 2 bits of function bits of the detected address. to appear. Further, the data processing circuit 66 receives an operation command signal from the address message decoder 64 and starts operation, and the timing control circuit 41
This circuit converts a message given as a serial signal from the BCH correction circuit 44 into a parallel bit signal used by the CPU 21 and sends it to the CPU 21 under the control of the CPU 21 .

FIG. 5 shows the appearance of the paging receiver of this embodiment.

The display section 33 on the top surface of the main body section 34 includes a first sub-display section 33a, a second sub-display section 33b, a second main display section 33c, and a second main display section 33d. A display indicating whether the buzzer 32 is set to sound or not (used for meetings, etc.), that is, whether it is set to sound or silence, and a display indicating the battery life of the power source 26, etc. When a message is received, the second sub-display section 33b displays a message indicating which of the address registers 51 to 56 the message was received from, and which memory of the message memory 27 the message was received. A display will appear to indicate whether the data has been stored. The received messages, etc. are displayed on the first main display section 33c'8 and the second main display section 33d. The time will be displayed and
In normal times (other than when the received contents are displayed on the first main display section 33C1 and the second main display section 33d are being checked), the current time is displayed. Also, the main body part 34-L
A mode switch SW3, a read switch SW4, and a page switch SW5 are arranged on the surface. Mode switch S
W3 is a switch used for switching modes; a normal mode for displaying on the display section 33 a message received each time it is operated or received by the address of the address register 51, 52 and stored in the message memory 27;
The mode is sequentially and cyclically switched between a correction mode for correcting the current time displayed on the second main display section 33c and a display mode for displaying various types of provided information received and stored. The readout switch SWA is a switch operated to sequentially display on the display section 33 several messages received in the past and stored in the message memory 27. Page switch SW
5 is a switch for displaying the subsequent message data portion when the received message specified by the readout switch SW4 cannot be displayed on one screen.

Next, the operation of the paging receiver configured as described above will be explained.

When the user turns on the switch SW+ shown in FIG. ).This allows ■D-
The ROM control decoder 47 sends a control signal to the IDR, 0M25 to output its stored data. And I
Various data stored in the D-ROM 25, that is, address data assigned to the paging receiver, frame data related to those address data, and SC retry data are stored in address registers 51 to 56 and frame registers 49 and 50, respectively. , is set in the SC retry register 48. Further, after outputting a start signal to the ID-ROM control decoder 47, the CPU 21 sends a control signal to the battery save signal decoder 46, which causes the battery save signal decoder 46 to enter a preamble search operation. That is, as shown in FIG. 6, the switch SW2 is turned on for one word time (the time required to receive one word of transmission data) with a period of 17 word times. On the other hand, since the preamble signal A is continuously sent for 18 words each time, it is inevitable that the switch SW2 is in the on state while the preamble signal A is sent twice. There is a timing when the preamble signal A is sent. When the preamble signal A is sent while this switch SW2 is in the on state, the power supply 2
6 to the receiving section 23 via switches SWI and SW2.
(see FIG. 2), and the preamble signal A passes through the antenna 22 and the receiving section 23 and is input as a bit string to the bit synchronization circuit 40 of the decoder section 24.

This preamble signal A is transmitted to this bit synchronization circuit 4.
0, the signal is synchronized with the circuit operation timing, and then sent to the preamble detection circuit 42. At this time, the preamble detection circuit 42 detects that the sent signal is the preamble signal A, that is, that the repetition of 0'' and 1'' continues for 8 bits or more, and sends a detection signal to the timing control circuit 41. Upon receiving the detection signal, the timing control circuit 41 sends a control signal to the battery save signal decoder 46 to stop the preamble search operation and perform a synchronization code search operation in which the switch SW2 is kept on (see FIG. 6). In other words, the synchronization signal detection circuit 43, which sequentially inputs the bit string from the bit synchronization circuit 40, receives this and
It is checked in units of 32 bits (one word, ie, the number of bits of the synchronization code Sc), including the 31 bits sent before, whether a predetermined synchronization code pattern is formed. When the synchronization signal detection circuit 43 detects the synchronization code SC, the detection signal from the synchronization signal detection circuit 43 resets the bit counter and word counter in the timing control circuit 41. This establishes word synchronization. Then, the timing control circuit 41 sends a control signal to the battery save signal decoder 46, and as shown in FIG. 7, the timing when the synchronization code is sent,
The switch SW7 is turned on only at the timing of frames to which the paging receiver is assigned, that is, frame numbers 2 and 8, and power is supplied to the receiving section 23 only at those timings. (supplies power) and performs reception. That is, the paging receiver performs reception only when there is a possibility that it will be called. If the synchronization code Sc is not detected within 64 words after entering the synchronization code search operation, the process returns to the preamble search operation.

” At the timing of frame number 2, an address code word is received and the address is beeped).
The signal is sent from the synchronization circuit 40 to the BCH correction circuit 44, where BCH error correction processing is performed, and then provided to address comparison circuits 57-62. Also, at this timing, a control signal is sent from the timing control circuit 41 to the frame register 49 regardless of whether or not the above-mentioned address is received, and as a result, a control signal is given from the frame register 49 to the address registers 51 and 52 that it manages. , address data set in these are sent as bit strings to address comparison circuits 57 and 58, respectively.

On the other hand, the address comparison circuits 57 and 58, when an address is sent from the BCH correction circuit 44,
It compares the address assigned to the paging receiver (that is, the address set in the address registers 51 and 52 and the address sent from it) and determines whether they match or whether the paging receiver is called. determine whether At this time, address comparison circuit 5
7. When any of 58 detects an address match,
A detection signal from the address comparison circuit is sent via an OR gate 63 to a battery save signal decoder 46 and an address message decoder 64. The battery save signal decoder 46 receives this detection signal and switches the switch S.
W2 continues to be kept on and reception continues. Further, upon receiving the detection signal, the address message decoder 64 first sends an operation command signal to the address processing circuit 65. As a result, the address processing circuit 65 transmits the address type data related to the address comparison circuit (one of the address comparison circuits 57 and 58) that sent the detection signal as described above, that is, the output signals of all address comparison circuits 57 to 62. The function bit data added to the received address is converted into a parallel bit signal used by the CPU 21 and sent to the CPU 21. This allows CPU2
1 later sends an operation command signal to the buzzer driver 31,
The buzzer 32 can be driven to emit a sound and an operation command signal can be sent to the LED driver 29 to cause the LED 30 to blink, allowing the user to easily recognize that there is a call.

After the above operations, the address message decoder 64
An operation command signal is sent to the data processing circuit 66. As a result, the data processing circuit 66 sequentially takes in the message bit string of the message code word sent following the address code word related to the address from the BCH correction circuit 44 and converts it into a parallel bit signal used by the CPU 21. and sends it to the CPU 21.

The CPU 21 stores the message sent as described in 1 above in the message memory 27, confirms that it is message data, checks for erroneous reception, etc., and then displays the message on the display unit 33. do.

Further, if no address is received at the timing of frame number 2, and an address is received at the timing of frame number 8, the address is sent from the bit synchronization circuit 4o to the BCH correction circuit 44, BCH error correction processing is performed here, and then provided to address comparison circuits 57-62. On the other hand, at this timing, a control signal is sent from the timing control circuit 41 to the frame register 50 regardless of whether or not the above-mentioned address is received. are given, and the addresses set therein are sent to address comparison circuits 59-62, respectively.

Therefore, when an address is sent via the BCH correction circuit 44, the address comparison circuits 59-62 compare it with the address assigned to the receiver (that is, the address set in the address registers 53-56). and the addresses sent from them).

At this time, when any of the address comparison circuits 59 to 62 detects a match between the addresses (that is, when there is a call to the paging receiver concerned), a detection signal from the address comparison circuit is sent via the OR gate 63 to save the battery. Signal decoder 46 and address message decoder 6
Sent to 4. Upon receiving the detection signal, the battery save signal decoder 46 continues reception, and the address message decoder 64 sends an operation command signal to the address processing circuit 65. As a result, the address processing circuit 65
As described above, the address type data related to the address comparison circuit that sent the detection signal and the function bit data added to the received address are converted into parallel bit signals used by the CPU 21 and sent to the CPU 21. In this case, since the message that the CPU 21 subsequently receives is the contract information, there is no need to notify the user of the call using the LED 30 or the buzzer 32 as in the case of the individual call or group call described above. (The contract information storage area may be configured to be able to set the call notification on/off) and select the corresponding contract information storage area in the message memory 27 according to the contents of the parallel bit signal from the address comparison circuit 65.

After the above operations, the address message decoder 64 sends an operation command signal to the data processing circuit 66. As a result, the data processing circuit 66 sequentially takes in from the BCH correction circuit 44 the bit string related to the message of the message code word sent following the address code word related to address 1, and parallel bits used by the CPU 21. It is converted into a signal and sent to the CPU 21.

The CPU 21 stores the sent message in the selected contract information storage area in the message memory 27, performs a predetermined check, and then stores the sent message (i.e., gold market price, stock price information of Company A). etc.) on display section 3
Display on 3.

Note that the CPU 21 sequentially displays the sent data on the display unit 33 as described above, but the first bit (message bit) of the sent word becomes O,
When the address code word becomes another address code word, a signal is sent to the battery save signal decoder 46 to release the continuous on state of the switch sw2 and return to normal intermittent reception operation.

Further, the received message and its address stored in the message memory 27 as described above can be displayed on the display section 33 for confirmation in the following manner. That is, what is received at the addresses in the address registers 51 and 52 is sequentially displayed on the display section 3 by selecting the normal mode with the mode switch SW3 and then operating the readout switch SW4.
3, and the information received at the addresses in the address registers 53 to 56 is sequentially designated by the mode switch SW3, and the mode for displaying the information received at each address is set to the mode for displaying the desired type of information. After that, the user operates the readout switch Sw4 to sequentially display the information sent at that address on the display section 33.

In this embodiment, a large number of paging receivers are called at the same time, and the call to provide predetermined information is performed in the eighth frame adjacent to the synchronization code word (see FIG. 7). In this way, when paging is performed in the 8th frame or the 1st frame adjacent to the synchronization code word, the connection of switch SW2 between the synchronization code word and the frame can be omitted in those paging receivers, and the information The power savings are commensurate with many paging receivers being served.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the scope of the present invention.

[Effects of the Invention] As detailed above, the present invention provides a paging signal that calls each paging receiver individually or in a certain group, and a paging signal that calls a large number of receivers all at once. This invention relates to a selective call communication system and receiver in which the paging receiver is allocated to independent frames and transmitted in a time-division manner, and the paging receiver is provided with a plurality of frame registers and at least l address registers corresponding to each frame register. Therefore, it is possible to provide a selective call communication system with high transmission efficiency when transmitting the same information to a large number of paging receivers, and a paging receiver used in the system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a transmission format in a selective call communication system according to an embodiment of the present invention, FIG. 2 is a diagram showing a system configuration of a radio paging system base station according to an embodiment of the present invention, and FIG. 4 is a diagram showing the circuit configuration of the paging receiver, FIG. 4 is a diagram showing the detailed configuration of the decoder section in FIG. 3, and FIG. 5 is a diagram showing the external appearance of the paging receiver.
FIG. 6 is a diagram explaining the preamble search operation and synchronization code search operation of the paging receiver, and FIG. 7 is a diagram showing the reception state of the paging receiver. 7...Verification circuit, 8...Subscriber memory, 9...Signal processing circuit, 10...
Transmitter, 11...Antenna, 21・Old-CP
U, 22... Antenna, 23... Receiving section, 24... Decoder section, 25 Old... IDR
OM, 26...Power supply, 27...Message memory, 28.Old...Switch circuit, 29...
...LED driver, 30...LED, 31
... Buzzer driver, 32 ... Buzzer, 33 ... Display unit, 40 ... Bit synchronization circuit, 41 ... Timing control circuit, 42・
...Preamble detection circuit, 43 ... Synchronization signal detection circuit, 44 ... BCH correction circuit, 4
5...SC mismatch counter, 46...
Battery save signal decoder, 47...ID
-ROM control decoder, 48...SC retry register, 49...frame register, 50...
...Frame register, 51 to 56...
Address register, 57-62...address comparison circuit, 64...address message decoder, 65...address processing circuit, 66...
・Data processing circuit.

Claims (3)

[Claims] (1) A selective calling method in which a calling signal that calls each receiver individually and a calling signal that calls multiple receivers simultaneously are assigned to independent frames and transmitted in a time-division manner. (2) The base station transmits an individual paging signal for each receiver in a frame corresponding to the group to which the receiver belongs, and also transmits a paging signal for simultaneously paging multiple receivers in a specific frame adjacent to the synchronization code word. In this selective calling method, the receiver receives only a predetermined period of time that includes the frame corresponding to the group to which the receiver belongs and the specific frame. (3) A selective call receiver having a plurality of frame registers and at least one address register corresponding to each frame register.