JPH02162444A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To prevent the uncorrectable malfunctions caused by the accumulation of error bits by securing such a constitution where a CPU corrects the soft error of a RAM in a data reading period of the RAM and writes again the normal data and a normal check bit into the RAM. CONSTITUTION:A data register inputs the error correction pulse output signal outputted from an error correction code ECC circuit 13. A timing circuit 8 inputs the read and write signals outputted from a CPU 5 as well as the error correction pulse output signal, outputs the memory read signals to a RAM 10, the circuit 13, and a bus transceiver 16, and outputs the memory write signal to the RAM 10. If the data read out of the RAM 10 has an error, this data is corrected by the circuit 13. In this case, this corrected data and a check bit are written again into the RAM 10. Thus the normal data and a normal check bit are written into the RAM 10. Then it is possible to prevent the accumulation of error data and to prevent the occurrence of uncorrectable malfunctions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on bit errors in memory circuits used, for example, in the field of computer application. This invention relates to preventing malfunctions of arithmetic processing units.

[Conventional technology]

In general, high-density digital circuit elements are affected by external factors 1, for example, when high-energy particles such as radiation are incident, R
This causes a phenomenon called a soft error in which the logic of a digital element such as an AM (Randos Access Memory) is inverted. If such a phenomenon occurs in the RAM constituting the arithmetic processing device, it may cause serious trouble to the arithmetic processing device.

Especially in outer space, the incidence of high-energy particles is high (
, Reliability": From the point in F, it was necessary to take measures to improve the reliability of the CPU (Central
Processing tlnit) as a means to avoid RAM soft errors.
A correction code) circuit is additionally used. What is an ECC circuit? When data is written from the CPU to the RAM, a specific pattern (called a check pit) is added to the data according to the written data, and the RA
Write to M. Also, when CPt1 reads data from the RAM, it compares the data already written in the RAM with the check pit, and if the error in RA- can be corrected, the CPU reads out the corrected data and performs the error correction. If a RAM error cannot be corrected, the error is not corrected, but an error detection pulse is output.

FIG. 3 is a block diagram showing a conventional arithmetic processing device. In FIG. 1, (5) is CPU, (la) is CP[I(5
), (1) is an address bus that combines the address signal (L4) with one arbitrary integer,
(10) is the RAM into which the address bus (1) signal is input.
, (2a) is a first bidirectional data signal that inputs and outputs data from the CPU (5), and (2) is a first bidirectional data bus that combines an arbitrary integer j of first bidirectional data signals. , (13) is an ECC circuit that outputs the signal of the first bidirectional data bus (2), and (6a) is an ECC circuit (13) that outputs the signal of the first bidirectional data bus (2).
) and a second bidirectional data signal that outputs the data signal of RAM (10), and (6) is a second bidirectional data signal that outputs the data signal of RAM (10).
a) is a second bidirectional data bus consisting of an arbitrary integer number j; (7a) is an ECC circuit (13) and a RAM (10);
Input/output the check bit signal. Bidirectional check pit signal (7) is bidirectional check bit signal (7a)
is a bidirectional check bit bus whose length is set to an arbitrary integer, (3) is a read signal that instructs the CPU (5) to read data from the RAM (10), and (4) is a read signal that the CPU (5) uses to read data from the RAM (10).
A write signal that instructs AM (1G) to write data,
(11) is an error correction pulse signal output (12) that outputs a signal when an error is corrected from each signal of the second bidirectional data bus (6) and bidirectional check bit bus (7) by the ECC circuit (I3). ) is the ECC circuit (13)
This is an error detection pulse signal output that outputs a signal when an error is detected from the respective signals of the second bidirectional data bus (6) and the bidirectional check bit bus (7).

A conventional arithmetic processing device is configured as described above. Next, the operation will be explained.

CPU (5) stores data in RAM (10) 1. : When writing, the CPU (5) outputs the address signal from the address bus (1) and simultaneously outputs the address signal from the first bidirectional data bus (2).
Output the write data to. Further, the CPU (5) outputs a write signal (4) to the RAM (to). At this time,
The ECC circuit (13) receives the input first bidirectional data bus (
A check pit corresponding to the data in step 2) is generated, the data is output to the second bidirectional data bus (6), and at the same time a check bit signal is output to the bidirectional check bit bus (7). The RAM (10) receives the input address bus ('l) signal and the second bidirectional data bus (6).
, bidirectional check bit bus (7) signal, CPU
It is written at the timing of the write signal (4) from (5).

When the CPU (5) reads data from the RAM (10), the CPU (5) reads data from the RAM (10) using the address bus (1).
10) Specify the address. Further, the CPU (5) outputs a read request to the read signal (3), and outputs the read request to the RAM (10
) to make a request. The RAM (10) to which an address is specified and a read request is given outputs the data signal and check pit signal corresponding to the address to the second bidirectional data bus (6) and the bidirectional check/l check bit bus (7). do. The ECC circuit (which receives the signals of the second bidirectional data bus (6) and the bidirectional check bit bus (7)) (
13) is put into an error correction state by the read signal (3) output from the CPU (5), and is connected to the second bidirectional data bus (6).
) and the bidirectional check bit bus (7), and if there is no error, the data signal of the second bidirectional data bus (6) is directly transmitted to the first bidirectional data bus (6). Output to bus (2). CPU (5) is F
, the data signal of the first bidirectional data bus (2) outputted by the CC circuit (13) is read, and the read processing is completed.

Here, a case will be described in which a soft error that causes bit inversion occurs in the write data of the RAM (10) due to an external factor. When the data signal of the RAM (IQ) is read and error bits are included in the signals of the second bidirectional data bus (6) and the bidirectional check path (7), the error is detected by the ECC circuit (13). When the error is correctable, the error bit of the signal on the second bidirectional data bus (6) is corrected, the corrected data is output to the first bidirectional data bus (2), and the error correction pulse is Therefore, the CPU outputs a signal to the correction pulse output (11).
The data signal read by (5) from I'lAM (1G) is normal. In addition, when an error cannot be corrected by the ECC circuit (13), the ECC circuit (13)
13) outputs error-containing data to the first bidirectional data bus (1), and outputs a signal indicating that an error has been detected to the error detection pulse output (12).

[Problem to be solved by the invention]

Since the arithmetic processing unit described in I- is configured as described above, it was not possible to correct error bits that exceeded the error correction capability of the ECC circuit, and reading error data into the CPU could cause malfunctions. . in general.

It is known that most soft errors that occur in a RAM due to a single external factor are single pit errors. Therefore, it can be seen that there is a high probability that multiple bit errors that exceed the error correction capability of the ECC circuit occur because a single bit error causes a soft error again at the same address and erroneous bits accumulate. In other words, there is a problem in that RAMI causes malfunctions due to accumulation of soft errors that occur.

[Means to solve the problem]

The arithmetic processing device according to the present invention, when an error has occurred in the data read from the RAM, converts the data into an EC.
The error is corrected using the C circuit. At this time, by writing the error corrected iE data and check bits back to the RAMI, normal data and normal check pits are written to the RAM. By writing normal data every time an error is corrected in this way, the accumulation of error data is prevented.
This prevents malfunctions due to inability to correct errors.

[Effect]

In the arithmetic processing device of the present invention, when a soft error occurs in the RAM when the CPU reads data from the RAM, and the error is corrected by the ECC circuit, the arithmetic processing device applies an error correction pulse to the error correction data resulting from this error correction. Using a trigger, the data is stored in a register, and the data in the register, which is corrected for errors and becomes normal data, is used as data for the CPU, and at the same time, a check pit is added again using the ECC circuit using the data in the register, and the data is written into the RAM 1 again.

〔Example〕

An embodiment of the present invention will be described below.

In Figure 1, (1) to (7), and (10) to (
13) is completely the same as the conventional arithmetic processing device described above.

(16) is a bus transceiver that separates the data direction of the data signal of the first bidirectional data bus (2); (+4)
(1) is an output data bus separated from the bus transceiver (16) in the data direction to the output side; (15) is an input data bus separated from the bus transceiver (16) in the data direction to the input side; (17) ) inputs the signal of the above output data bus (14), and inputs the signal of the above ECC circuit (13).
) is a data register that inputs the error correction pulse signal output from the CPU (5) as a timing signal and outputs the signal to the input data bus (15).
(8) is a timing circuit into which the read signal (3) and write signal (4) outputted from the I-recorded ECC circuit (13) are input; 18) and the above RAM (
1G) and - the memory read signal inputted to the ECC circuit (13) and the bus transceiver (16), (9) is output from the timing circuit (18) and read out from the RAM (10).
) is the memory write signal input to

1- In the arithmetic processing unit configured as described above, the CPU
When writing data from (5) to RAM (to), the operation is similar to that of the conventional arithmetic processing device described above. However, C
The read signal (3) and write signal (4) output from the PU (5) are input to a timing circuit (18), and are output as a memory read signal (8) and a memory write signal (9). In this case, the read signal (3) and write signal (4) are the same as the memory read signal (8) and memory write signal (9).

When the CPU (5) reads data from the RAM (10),
The CPU (5) specifies a read address to the RAM (10) via the address bus (1) [shown in (1) in FIG. 2]. The CPU (5) also outputs a read signal (3) [shown in (3) in FIG. 2] to the timing circuit (18).

The timing circuit (18) outputs the same signal as the memory read signal (8) in response to the read signal (3). From the RAM (10) by the memory read signal (8),
Data is output onto a second bi-directional data bus (6) and check bits are output onto a bi-directional check bit path (7). The above memory read signal (8) is the ECC circuit (13)
, the second bidirectional data bus (6) from the RAM (13) and the bidirectional check bit bus (7)
This second bidirectional data bus (
6) and the bidirectional check bit bus (7), the data signal of the bidirectional data bus of upper storage 2 is output as is to the first bidirectional data bus (2), and the CPU ( 5) can read data. Next, a case will be described in which when the CPU (5) reads data from the RAM (10), there is error data in the data in the RAM (10) due to an external factor. First, RAIll (1G)
When there is an error in the signals of the second bidirectional data bus (6) and bidirectional check bit bus (7), which are read data, and the signals are input to the ECC circuit (13), an error occurs in the ECC circuit (13). If a correctable error occurs [as shown in (6) and (7) in Figure 2], the ECC circuit (13)
Then, error correction is performed and error corrected 1E data is output to the first bidirectional data bus (2), and a signal is output to the error correction pulse signal output (11) [shown in (11) in FIG. 2]. ]
This signal is connected to the data register (17) and the timing circuit (
18). The bus transceiver (16) is in a state of outputting data to the output data bus (14) when the memory read signal (8) is being output. The data register (17) is the data of the first bidirectional data bus (2> obtained from the output state of the bus transceiver (16).Error correction data is input here.
Error correction pulse signal output from C circuit (11) (]
The data register (17) stores error correction data in response to the signal from I1, and the timing circuit (18) stops the memory read signal (8) in response to the error correction pulse signal output (11) (as shown in Fig. 2). (8)) As a result, the bus transceiver (1B) connects the output data bus (
I4) to output data to the 2-input data bus (
15), and the ECC circuit (13) also changes from the error correction state to the check bit generation state. This operation causes the data register (17
) The error correction data stored in the output data bus (1
5), outputs a signal to the first bidirectional data bus (2), and inputs the signal to the CPU (5) and the ECC circuit (I3). Also, at this time, since the ECC circuit (13) is in the check bit generation state, error correction data is output to the second data bus (6), and check bit data corresponding to the error correction data is transmitted in both directions. Output to check bit bus (7). The timing circuit (18) inputs the signal of the error correction pulse signal output (11), and outputs the memory write signal (9) after a certain period of time, as shown in (9) in FIG. lJ? AM (10) is
With the read address specified, after reading the error data, the error corrected iE data is transferred to the second bidirectional data bus (6) and the corresponding check pit is transferred to the bidirectional check bit bus (7) for each error. The signal that is not present is written again by the memory retrieval signal (9).

However, if there is an error in the RAM (to) that cannot be corrected by the ECC circuit (13), the error detection pulse signal (12) is output as in the conventional technology, and the second bidirectional data bus (6 ) is output as is to the first bidirectional data bus (2), and the CPU (5) reads out the error data.

〔Effect of the invention〕

As described above, according to the present invention, the CPU corrects the soft errors occurring in the RAM during the period of reading data from the RAM, and writes normal data and normal bits to the IIILAM again. This prevents malfunctions caused by the inability to correct errors caused by accumulation of error bits.
In addition, since it is configured to correct errors and rewrite to RAM during the CPU read period, it does not affect soft errors in the arithmetic processing unit, and the processing time remains the same as before. The effect of obtaining highly reliable products) (Yes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an arithmetic processing device according to an embodiment of the present invention, FIG. 2 is a timing diagram illustrating the timing of the embodiment, and FIG. 3 is a block diagram showing a conventional arithmetic processing device. In the figure, (1) is the address bus, (2) is the first
bidirectional data bus, (3) is read signal, (4) is write signal, (5) is CPU, (6) is second bidirectional data bus, (7) is bidirectional check bit path, (8
) is a memory read signal, (9) is a memory write signal,
(10) is RAM, (11) is error correction pulse signal output, (12) is error detection pulse signal output, (13) is ECC circuit, (14) is output data bus (I5), (16) is input data bus ) is a bus transceiver (17)
is a data register, and (1g) is a timing circuit.

Claims (1)

[Claims] C in which a plurality of address signals are combined to form an address bus, a plurality of bidirectional data signals are combined to form a first bidirectional data bus, and a read signal and a write signal are output.
PU (Central Processing Unit)
and a second bidirectional data bus which connects the address bus and combines a plurality of new bidirectional data signals,
In addition, a bidirectional check bit bus consisting of a plurality of bidirectional check bit signals is connected, and a RAM (RandomAcce
ssMemory) and a data bus connected to the CPU, a second bidirectional data bus connected to the RAM, and a bidirectional check bit bus connected to the RAM. Connect and also connect the above RA
An ECC circuit that inputs the memory read signal that is input to M, and outputs an error correction pulse signal that outputs an error correction signal and an error detection pulse signal that outputs an error detection signal, and the above CPU and the above ECC circuit. The first connected
a bidirectional data bus connected thereto, and an output data bus and an input data bus separated from the bidirectional first data bus connected to the bus transceiver to which the memory read signal is input, and a bus transceiver connected to the bus transceiver. connecting the output data bus and input data bus, and inputting the error correction pulse output signal outputted from the ECC circuit to a data register, and inputting the read signal and write signal outputted from the E CPU; Also input the error correction pulse output signal output from the ECC circuit,
An arithmetic processing device further comprising a timing circuit that outputs a memory read signal to the RAM, the ECC circuit, and the bus transceiver, and outputs a memory write signal to the RAM.