JPH02159651A - Monitoring system for data memory - Google Patents

Abstract

PURPOSE:To detect double read-out, etc., as an error by constituting the system so that with respect to 8-bit parallel input data, not only a vertical direction parity check but also a horizontal direction parity check can be executed by utilizing a free bit. CONSTITUTION:When 8-bit parallel data is inputted to a data memory 1, a vertical direction parity Pr1 of a first row is generated, and in the same way, vertical direction parities Pr2-Pr4 of a second row - a fourth row are generated. In addition, a horizontal direction parity Pa5 of a first line is generated, and in the same way, horizontal direction parities Pb5-Ph5 of a second line - an eighth line are generated. After passing through the data memory 1, vertical direction parities Pr2', Pr4', Pr1' and Pr3' are generated, and horizontal direction parities Pa5'-Ph5' are generated. In such a way, since double read can be detected, data memory monitoring can be executed more exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a monitoring method for a data memory in which data is sequentially written and randomly read, and more particularly to a method for monitoring normal write/read operations of a data memory.

(Prior art) Conventionally, methods for monitoring this type of data memory include:
Previously, only vertical monitoring of so-called input data was performed, in which a 1-bit parity bit was added to 8-bit parallel input.

FIG. 2 is an explanatory diagram in which only vertical parity check is performed on input of 8-bit parallel data according to the prior art. In Figure 2, 1 is the data memory, 2 is the input data in 8-bit parallel configuration, 4 is the vertical parity for the input data, 5 is the output data in 8-bit parallel format, and F is the vertical parity for the output data. be.

(Problem to be Solved by the Invention) In the conventional data memory monitoring method described above, if an abnormality occurs due to random reading and the data is read twice, the error cannot be detected using the so-called vertical parity of the input data. There are drawbacks.

An object of the present invention is to add vertical parity bits to input 98-bit parallel data, and to add horizontal parity bits to one frame by using empty bits in one frame, especially in order to solve the above-mentioned drawbacks. remove the
The object of the present invention is to provide a data memory monitoring method configured to detect horizontal parity errors as well.

(Means for Equally Determining Problems) The data memory monitoring system according to the present invention is constituted by a parity check means and a data memory.

The parity check means is for performing a horizontal parity check on empty bits of the frame in addition to a vertical parity check on the 8-bit parallel input.

Data memory is like a tortoise and a tortoise in which data is written sequentially and read out randomly.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. III is an explanatory diagram showing a data memory monitoring method according to the present invention. FIG. 1 is an explanatory diagram showing the arrangement of input/output of 8-bit parallel data, vertical parity for monitoring them, and horizontal parity.

In FIG. 1, 1 is a data memory, 2 is input data in an 8-bit parallel configuration, 3 is horizontal parity for input data, 4 is vertical harness for input data, and S
is the output data in 8-bit parallel format, 6 is the horizontal parity for the output data, and F is the vertical harness for the output data.

First, when 8-bit parallel data is input to the data memory 1, the vertical parity pr1 of the first column is generated,
Similarly, the vertical parity P r of the second to fourth columns
le P rl * P r4 is generated. In addition to this, the horizontal parity P''I of the first row is generated, and in the same way, the horizontal parity PbB t P of the second to eighth rows is generated.
J IP d@e P 'Sg IP 15 eP
g@IP h6 is generated.

After passing through the data memory 1, the vertical parity Pry of the first column (the second column before passing through the data memory) is generated, and in the same way, the vertical parity P r4 of the second to fourth columns is generated.
*Prl*Pr6 is generated. In addition, the horizontal parity pa, / in the first row is generated, and in the same way, the horizontal parity Pb@' + in the second to @8th rows is generated.
Pe@'ePd@ +Pl! 1B'*Pfg' *P
g@'rPh; is generated.

Therefore, prl and P rmouthP rj and P rj e
P rl and Pr1. A vertical parity check can be performed on each match of pr, and pr4, and Pal and P
ag'e...

Lateral parity checking means can be implemented with PIlla and Ph. Moreover, since double radius distortion can also be detected, more accurate data memory monitoring can be performed.

(Effects of the Invention) As explained above, the present invention not only performs a vertical parity check on 8-bit parallel input data;
By also performing the horizontal parity check using empty bits, it is possible to detect undetected data being read twice as an error.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating an example of a data memory monitoring method according to the present invention. FIG. 2 is an explanatory diagram showing an example of a data memory monitoring method according to the prior art. 1... Shima data memory 2.8-e-data 3, FJ&*@horizontal parity 4.70-working vertical parity

Claims (1)

[Claims] A parity check means for performing a horizontal parity check on empty bits of the frame in addition to a vertical parity check for 8-bit parallel input, and a data memory for sequentially writing and randomly reading data. A data memory monitoring method comprising: