JPH02156787A - Orthogonal multiplex transmission system and signal generator used for transmitter thereof and signal reproducing device used for receiver thereof - Google Patents

Abstract

PURPOSE:To reduce disturbance of a multiplex signal onto a video signal of a television receiver by applying spectrum suppression processing to a multiplex signal subject to digital coding, applying modulation so as to invert the phase of an adjacent data and applying amplitude modulation to an orthogonal carrier in the relation of orthogonal phase with a video carrier. CONSTITUTION:A multiplex digital signal is fed to an input terminal 111, a digital signal processing circuit 112 corrects an error caused during the transmission, a digital modulation circuit 113 applies FM, PE digital modulation and a tri-state value conversion circuit 114 converts the binary digital signal into a tri-state digital signal. Moreover, a processing circuit 115 processed the data in the unit of one horizontal scanning period for plural number of times, the data is inverted in the adjacent horizontal scanning period to apply transmission in opposite phase. Then the carrier for video is modulated in the orthogonal relation between the video signal and digitally coded signal. Thus, the disturbance onto the existing television receiver is reduced in the case of multiplexing the multiplex signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex transmission system &C*, which is a multiplex transmission signal regeneration system that receives transmission No. 1 in which other information is multiplexed on the current television signal. Regarding equipment.

[Conventional technology]

Conventionally, a method for multiplexing other information onto a television signal is to change an orthogonal carrier wave having an orthogonal phase relationship with the image carrier with other information, as described in Japanese Patent Laid-Open No. 65-56694. An orthogonal modulation method is known that combines and transmits the video signal modulated by the video signal, and in this conventional example, the aspect ratio of the TV screen (the ratio of the width to the height of the screen) is used as other information. It contains a lot of information for the wide area when it is set to .

In addition, the current television receiver using this orthogonal modulation method is 1! ! As a means to reduce the interference caused by multiplexed signals to the aircraft, a method is used to multiplex the residual whistle sideband using a Nyquist filter, which has a frequency characteristic opposite to that of the video intermediate frequency amplification attack of the aircraft. is shown in °C.

[A problem to be invented or solved]

The above conventional technology is based on the current TV receiver 1 using orthogonal modulation method.
! Interference due to multiplexed signals when the detection method has a comprehensive configuration or multi-signal interference when the carrier regeneration type quasi-synchronous detection is used.
Interference caused by low frequency components of the signal @ No consideration was given especially to the interference caused to the color subcarrier of current television receivers, and the towed television broadcasting system due to multiplexed signals is not possible! There was a problem with hue change interference in Shin's reproduced image.

Furthermore, no consideration was given to interference from video signals when reproducing multiplexed signals that have been multiplexed and transmitted.

An object of the present invention is to provide a multiplex transmission system that further reduces the number of U''# signals transmitted to 18 desktop television receivers when multiplexing multiplexed signals using an orthogonal modulation system for video transmission in current television broadcasting systems. The main object of the present invention is to provide an effective fd signal generation device.A further object of the present invention is to provide an orthogonal modulation method that reduces interference with current television broadcasting, and which is multiplexed and transmitted on video carrier waves of current television broadcasting. It is an object of the present invention to provide a multi-transmission signal reproducing device which is effective for stably reproducing a multiplexed signal with reduced interference from a video signal.

[Means to solve the problem]

In order to achieve the above object, in the present invention, a digitally encoded multi-KIM signal, which is different from a video signal, is subjected to spectrum suppression processing to suppress its low frequency components.
Alternatively, use a combination of the + method of performing kI & lI so that the data is reversed or reversed phase like the pE code, and the method of shaking the 2ia digital signal to 5111 digital No. 48 so as to suppress the low frequency component, and further suppress processing. #jlLg! 1
Review the results in horizontal scanning period units of the video signal, and 1
Multiplex multiplexing of correlation processing that reverses to an inverse phase relationship at the same timing in four adjacent horizontal scanning periods! In the No. 1 issue, the above-mentioned Hozo Rengo Kai and 1 Father Seiso's En 9kVc 11iL Matakata Maki were tuned, and the multiplex was transmitted by combining with Joshoguchi Rokubo Fei Sotai Mei Hen - Nao. The transmission system is used as a transmission method, and the force generator includes a phase shifter that obtains a carrier m of quadrature from the carrier wave generation 11111 path that transmits the video signal, and a digital signal such as FM or PE code that reduces the spectrum near the video carrier wave. A modulation circuit, a three-value switching circuit that converts the 2ill digital 4 code into an S-digital code, and the video signal (by engineering).
The digitally encoded multi-X mark is 1J! Correlation processing that is reconsidered in units of horizontal fixed period of bonds and reversed to negative correlation at the same timing of horizontal fixed f period after 114 withdrawals?
A T5 processing circuit, a modulation circuit that modulates the pitch width of the output of the phase shifter with this output, and a synthesis circuit that synthesizes the output of the shivering chest circuit and the pitch width modulation of the shallow flute side pitch shifter. did.

Further, the above purpose is to transmit a multiplexed signal which is multiplexed by transmitting a carrier wave that is amplitude-modulated and is combined with the amplitude-modulated carrier wave by using a multiplexed signal other than No. In the signal detected by the multiplex transmission method that is multiplexed in a quadrature phase relationship by the carrier regeneration circuit and synchronous detection circuit of the demodulating receiver, pm@ or PE
A digital rear leg circuit that modulates the transmitted multiplex signal so that it has adjacent takes or opposite phases like a code, and then converts it into an s value and demodulates the transmitted multiplex 'r8 code. This is accomplished using circuits.

In addition, in the case of using the carrier & regeneration type transverse i& (also referred to as pseudo synchronous detection) for the transverse wave of the vibrated carrier wave, the selection of the carrier intermittent/number selection circuit that creates the carrier modified Nyu circuit is required. The response frequency band of the PLL that uses the same AI3 detection is within the suppressed band of the spectrum near the carrier wave. By making the band narrower, 4 results can be achieved.

In addition, a plurality of delay circuits are provided to delay the multi-M1g signals that are repeatedly transmitted multiple times in a certain period, and an arithmetic circuit is provided to add and subtract the outputs of the plurality of delay circuits. By providing this, it is coupled.

[Effect]

The residual side band amplitude has a video side band in the image carrier which is in tune with the amplitude of the residual side band, and the band CI) S is
Adding @ to B) and adjusting the carrier wave by waiting for the orthogonal relationship between the video signal and the multi-channel signal reduces the influence of the multi-channel signal on the reproduced video signal.Here, By making the V4 degree of the multi-signal signal lower than the video signal, there is an effect of reducing the influence of the Ta-1!! No. on the video signal reproduced by the Bao-M machine.Also, the Ta-N-No. Since the orthogonally modulated video signal is not demodulated, the influence of interference from the video signal to the multiplex signal is reduced.

Furthermore, if the horizontal axillary modulation of the amplitude modulation of the receiver is of the transport persuasion type* (also referred to as jILC pseudo-Oka period horizontal axillary), the transport recirculation frequency selection circuit of the carrier sputum circumference selection circuit that constitutes the carrier wave regeneration circuit Because there is interference such as one source multiplexing (i!) in the band, the reproduced carrier wave has phase jitter V, which causes phase fluctuations in the Ayuka Yokokai output, causing image disturbances such as changes in the hue of the one source.Digital/R94 Since the circuit and the conversion to 511 (b) suppress the spectral components in the vicinity of the frequency of the transmission multiplexed signal, the interference signal is reduced from the transmission range of the transport system JttJ technique number selection area of the iron transmission direct circuit system a trace selection circuit. to reduce the hue change caused by the phase f: #dJ caused by orthogonal multiplexing qI.

The same goes for the vibration-modulation detection of the PLLIWIM detection method, which reduces interference due to orthogonal multiplexing within the PLL frequency response temporal band, and eliminates hue changes due to phase fluctuations caused by the multiplex JrM signal. reduce

In addition, since the data is transmitted in reverse phase, the TV channel depression caused by the phase oscillation of the orthogonal component &C (II) caused by the multiplexing of the It can reduce the hue change on the screen of the receiver.

More f. Multi*(I!-q is reconsidered in units of horizontal scanning periods of the video signal, and transmitting the same -multi' The hue change on the screen of the TV Jimitsu receiver using the envelope N@resenpa method, which is caused by the phase fluctuation of the carrier signal, is reduced to a low tc.

In addition, since the desk FM audio (PI number) has the same frequency, frequency, and modulation code, they do not affect each other and are both types.

The Okashi 151T wave circuit and the carrier UJL Nyu regeneration circuit regenerate the multiplexed signal, and then the multiplexed signal can be regenerated by the 511it demodulation circuit and digital demodulation circuit using two comparators. Since the response band of the carrier wave regeneration circuit is narrowed so that the spectrum near the carrier wave of the old number to be transmitted is within the suppressed band, it is possible to stably reproduce the multiplexed and transmitted multiplexed ideas.

In addition, in the case of ffi transmission tIL Nyu type detection, by narrowing the selection band of ★ transmission I & Shusaka type, PLLiWIJa
In the case of m-waves (handling the response frequency band of the engineering PLL), the amplitude oscillations from the orthogonal multi-JM signal that is multiplexed and transmitted by the plate-transmitted wave whose amplitude is R-legged and the plate-transmitted wave with orthogonal phase relationship. −
Interference with the carrier wave?iii! Because he is admired, he is able to suppress the phase fluctuations of Kakugomei, which were narrowed in width due to the phase vibration caused by the modulation tsukugogo.

:! ! Since the No. 48- signal delayed by the delay circuit is processed by Noboru Toguchi etc. in the arithmetic circuit, the same signal (G signal is added by the delay rc, and when repeated twice, the signal amplitude increases by 2. Due to randomness, only the J7 ratio increases, so the signal-to-axis ratio of the received signal can be revised. Also, when transmitting signals, the signal-to-axis ratio of the received signal can be changed at intervals of a certain period of time. Since the arithmetic circuit subtracts the delay of , it is also possible to cancel out and eliminate disturbances that occur in short-term intervals.

When transmitting multiple signals by making the video signal carrier wave orthogonal to the video signal, it is possible to transmit the same multiplexed signal in multiple even-numbered horizontal scanning periods, such as two horizontal scanning periods, in reverse order in adjacent horizontal scanning periods. In the case of phase transmission, the multiplexed signals with a time difference of one horizontal scanning period delay are the same and have opposite phases, so the delay circuit delays the time by a multiple of one horizontal scanning period, and the arithmetic circuit transmits [water contact half scanning]. The signal transmitted in the period is #C″g. As a result, the multi'X signal becomes 20 times more precise, and a leakage or ghost from the Hozuka signal is eliminated.
Regarding An, the correlation for each horizontal scanning period of video No. 1 (
On the television screen, it is offset by vertical correlation).

〔Example〕

Examples of the present invention will be described below with reference to the drawings. .

Fig. 1 shows 10 parts of a television training signal transmission device according to an embodiment of the present invention. A digitally encoded signal will be explained as an example of a signal to be multiplexed and transmitted.

101 is an audio signal, 102 is an FM modulator, 10
6 is an audio signal carrier generator, 104 is a video converter, 105 is a matrix circuit, 106 is a Terutomo I B processing circuit, 107 is a chromatic signal processing circuit, 108 is an addition circuit, and 109 is a bastard image. 110 is a video signal carrier IML generator, 111 is an input electronic for digital signals, 112 is a digital signal processing circuit, 115 is a digital shaking leg circuit, 114 is a SIL&L conversion circuit, 115 is a processing circuit,
116 is a low-pass filter, 117 is a sieve filter, 118 is a digitally encoded tP signal input hook, 119 is an equalizer, 120 & Noriyoshi Kotoguchi, 1214 is a transmission VSB for the Zan-Trade side's Kaitei Amplitude Pumpkin. Filter, 122 is a filter,
12b is an antenna.

The audio signal from the audio signal input terminal 101 converts the audio f1i incoming wave from the audio P signal carrier wave generator 103 into the FM converter 1.
At 02, FMi tone is applied. A matrix 105 divides the KGB three primary color signals inputted into the color filter 104 into a color signal and a color signal, respectively.
6 and the value processed by the color difference processing circuit 107, adder 1
Add at 08. The carrier wave generator 110 modulates the transmission wave from the carrier wave generator 110 using a temporary signal, and the transmission VSB filter 121 limits the band to the television broadcast band. The audio modulated waves are added and transmitted from the antenna 125.

The above is the same as conventional terrestrial television broadcasting. Add the following to transmit high-quality audio to the above signals.

Add multiple digital signals to input electronic 1114C,
The digital signal processing circuit 112 adds a code for detecting and correcting errors that occur during transmission, and performs interleaving 1 processing as described below. The processed digital code is subjected to digital modulation such as FM or PR in a digital modulation circuit 115, and then converted to +1,0 in a 5 ill conversion circuit 114.
+1.0 from the 21 channel digital signal. The processing circuit 115 repeats the data multiple times in units of one horizontal scanning period, and in the adjacent horizontal scanning period, the data can be inverted and transmitted in reverse phase. Perform processing. A detailed explanation will be given in the next section. after that,
Unnecessary high-frequency components are removed via a low-pass filter 116 that takes into account the transmission rate of the output of the processing circuit 115.

Using this digitally encoded signal, the video signal carrier wave whose phase has been shifted by 90 degrees via the phase shifter 117 is modulated by the digitally encoded signal modulator 118, and the video signal 91! Signal I
Equalizer 1 with characteristics inverse to Nyquist filter of F
The frequency characteristics are corrected in step 19, and added to the carrier wave modulated by the video signal in adder 120.

As a result, the video carrier wave is modulated in an orthogonal relationship with the video signal and the digitally encoded signal.

The modulated spectral skin is shown in Figure 2.

In Figure 2, 2 old is the spectrum of the video signal after the VSB filter, 202 is the spectrum of the FM modulated audio signal, 2
05 indicates the spectrum of the digitally encoded signal.

204K will be explained later.

Here, since the video signal spectrum 201 and the spectrum 205 of the digitally encoded signal are orthogonal to each other, they are shown in two stages in FIG. Not considered.

In Figure 2, -0.75MHz for the video carrier.
The following spectrum is attenuated by a VSB filter with residual sideband amplitude modulation. 4, 2
There is a frequency spectrum modulated by the video signal 4B up to MHz, and a spectrum where the audio carrier wave is FM modulated around 4.5 MHz.

±0 with respect to the video carrier wave, and both side bands are transmitted for 75 MHz, so it can be thought of as a general silkworm @ modulation CD5B). A signal within ±0.75 MH2 orthogonal to the carrier wave having both sidebands is converted into digital code 1 and O.
When modulated by the widths A and -A with K equivalent, the spectrum of the carrier wave becomes cotωc t thAzinωct (11) when the image carrier wave amplitude is 1, where ωC is the angular frequency of the carrier wave.

Expanding equation (1), we get It is.

Let us now consider interference from a digitally encoded signal to a received video signal. The video signal detection circuit is cosω
For those that are synchronously detected with at, only the coefficient of capωat (i.e., only the video signal) regardless of the value button of A.
is played and does not cause any interference.

Further, in the case where the video signal detection circuit performs envelope detection, interference can be reduced by lowering the value of A below 1.

For example, if A is 0.1, E=i=1 out of 11. oos
Therefore, the ratio to 1 is 0.005 (') 'R (approximately -
aodB), but the S/N ratio of the video signal is
If it is B or higher, there is no problem in practical use.

On the other hand, interference with a digitally encoded signal from a video signal can be eliminated by demodulating only the components orthogonal to the carrier wave using a synchronous detection circuit. Signal level to noise ratio C or less SN
Considering the SN ratio of the video signal is 40
If tiB is at a practical level, the bandwidth is approximately 4 times that of the transmission band @1 mix of the digitally encoded signal, so the S/N ratio of the digitally encoded signal is 46 ct.
However, if the power level A is set to 0.1, the transmission SN ratio will be about 26 dE. Furthermore, when considering the relationship between the SN ratio of a digital signal and the pit error rate using a general binary signal, the relationship is 10-' when the SN ratio is 17.4 dB. When the SN ratio of the video signal is 4 octB, the transmission SN ratio of the digitally encoded signal is 26 dE, which is a practically sufficient value for the transmission of digital signals.

Next, consider the spectrum 203 of the digitally encoded signal and the digital chest transformation circuit 113.5-shank transformation circuit 114.

Spectrum of digitally encoded signal 2o3 & engineering 2
As shown in the figure, it is assumed that the spectrum near the Kffi transmission frequency is suppressed. This problem can be caused by suppressing the low frequency components of the baseband digital code before being modulated by the modulator 118, and the digital conversion circuit 113
This effect can be achieved by applying digital modulation that does not have a DC component such as , and further suppressing low-frequency components by converting the 21-channel digital signal into 5 values in the 5-value conversion circuit 114. There is. However, by using FM and PE, the transmission capacity is halved.

Here, the effect when frequency components near the carrier wave are reduced will be explained.

204 in FIG. 2 represents the carrier frequency selection band of the carrier frequency selection circuit that constitutes the carrier wave recovery circuit in the case of carrier wave recovery fine detection, or the frequency response band of the PLL that constitutes the carrier wave recovery circuit in the case of PLL synchronous detection. . band 2
If signals other than the 04 and 1c carrier frequency components are included, they interfere with carrier wave reproduction and cause deterioration of video detection characteristics. Since the spectrum 203 of the digitally encoded signal becomes this interference component, it is desirable that more spectral components within the response band 204 be suppressed.

In this way, the spectrum 2 of the digitally encoded signal
By selecting the carrier frequency selection band or the PLL frequency response band within the band in which the spectrum near the carrier frequency e of 0.05 is suppressed, interference from orthogonally multiplexed digitally encoded signals can be reduced.

In addition, we will discuss in detail the interference caused to the video transmission waves of current television broadcasts using monkeys.

FIG. 3 shows F゛M performed in the digital modulation circuit 115,
and an example of digital modulation of PE. FM・(Frg
qtLgrbcy Modwlat*on) makes bit 111 correspond to inversion, and bit)I-11 corresponds to no inversion, but also inverts the boundary between bits. pECPnaz* Encoding
) The bit 116 corresponds to a reversal in one direction, and the bit a-1@f corresponds to a reversal in the opposite direction. Once done, the boundaries between bits are also reversed if necessary.

The characteristics of FM and PE are that since each bit has one or more inversions, it is easy to perform cell logic, and that they do not include DC portions. Also, pE is 5 as shown in Figure 5.
niα. The data string of , al, α, . . . is aOhα. ,
A data string is formed in which adjacent data are arranged with opposite polarities, such as C1, C1, C1, α, . . . .

The fourth factor is an example of the 5-value conversion circuit 114 that has a low frequency component suppression effect.

401 is binary digital data input, 402, 405
404 is an inverter, 405 and 406 are AND circuits, 407 and 408 are adders, 409 is a 5-value digital data output, 410 is a clock input terminal, and 411 and 412 are D-7 amplifiers. The operation of Figure 4 will be explained using the timing chart of Figure 3. In FIG. 5, (α) is the 211 digital data waveform, (Al beam No. 16, (C1 is the output of the D-7 lip flop 411, (d) is the output of the D-7 lip flop 412, and (-) is the AND Circuit 405 output, (7'l
is the AND circuit 406 output, 1 is the inverter 407 output, (Al is 5 (it digital data waveform (adder 40
8 outputs), (&) is the digital/l/signal processing circuit 112
The output digital data, (1) is its waveform.

The output data of the digital signal processing circuit 112 (Al is represented by waveform .

The 2-speed digital data shown in Fig. 5 (α) is D-7-
The flip-flop C2 block 412 further delays the delay by 7, which is half of one data length, and as a result, the output of the D-flip-flop 412 is delayed by 2
ii The signal is delayed by T, which is one data length, than the digital data (see Figure A5 μm).

An AND circuit 405 generates a binary digital data (C1 and D
- Flip-flop 412 output (AND with the inversion of dl is performed and the rising edge of binary digital data (α) is detected as shown in figure (C).Similarly, KAND [g circuit 4
At 06, the inversion of the 2-digit digital data and the output from the D-flip-flop 412 are ANDed, and the sum of the 92-digit direct digital data (α (falling edge σ) of The waveform shown in Figure 97 is obtained. Adding the waveform of (#1-) and the waveform of diagram ψj using the adder 40f5 results in the 5 digital data shown in Figure A1. Figures (α) and μ) Comparing the data, the 5111L digital data shows B A (+1) at the rising edge of the 2Asahi digital data, and LoW (-1) at the falling edge.
) is generated with a pulse width of 1 data length T, and in other cases it is understood that the potential (b) is intermediate between 77 rill and Low. By converting the 2-value digital data into 3-value digital data in this way, it is possible to suppress the low-frequency components of the baseband digital signal, and remove unnecessary high-frequency components from this with the LpF116 to convert them into digitally encoded audio signals. A spectrum 205 of the digitally encoded audio gj signal in which the spectrum near the carrier frequency is suppressed is obtained by modulating the signal with the modulator 118.

The fourth teeth in FIGS. 1 and 5 have the effect of reducing frequency components near the video carrier wave.

Next, a specific example of the processing circuit 115 of A1- is shown in FIG. Further, FIG. 7 shows an explanation of the operation of FIG. 6 and an example of a transmission data string of the present invention. 601 is an input terminal, 602 is a time axis compression circuit, J605 is a timing generation circuit, 604 is an inverter, and 605 is a delay circuit.

606 is a changeover switch, 607 is an output terminal, 7014 is a data string of the input terminal 601, and 702 is a time axis kingship circuit 6.
02 output data string, 705 is the output data string of the delay circuit 6Ω5 which has passed through the inverter 604 and the delay circuit 605, 70
4 is an example of a transmission data string of the present invention, and 705 is a timing waveform.

Here, the signal input to the input terminal 601 is a 5-value signal, and FIG. 1072 shown in FIG. ).

For example, if a 5-value signal is +1.0. The operation of the inverter 604 represented by -1 is assumed to convert +1 to -1, -1 to +1, and 10 to 0. Furthermore, the data strings shown in FIGS. 7 and 8 are also ternary signals.

A data string 701 applied to an input terminal 601 is compressed in a time axis by a time axis compression circuit 602 according to the timing of a timing generation circuit 605, and is converted into intermittent data shown in a data string 702. This intermittent data is transferred to the inverter 604.
and a delay circuit 605 inverts the data, and the delay time τ
In other words, in the example of the m7 diagram, if the delay is delayed by 5 data, the result will be as shown in the data string 705. This data string 705
and the data string 702 are added using the changeover switch 606, resulting in a data string 704. This data string r04 is obtained by delaying and inserting the same data that has been inverted during the dataless period of the data string 702. FIG. 8 shows an example of a transmission pattern of the present invention. It is assumed that the delay time τ is the same as the horizontal scanning period of the video, and the timing waveform 705 is synchronized with the horizontal synchronization signal of the television receiver.
This is a simulated version of the data transmission timing that matches the screen. In FIG. 8, the bond shows the horizontal scanning direction and the vertical scanning direction.

In the first horizontal scanning period, the time series data is from α to α, and in the second horizontal scanning period, it is data from cLI to a, and in the first and second horizontal quantitative periods, ν・τ The same data will be in reverse phase.

Also, consider here the video color subcarrier of current television broadcasting. Figure 9 shows the spectrum of color subcarriers on the video carrier. (α) indicates the case where there is no multiplexing on the orthogonal components of the video carrier; (Al indicates the case where there is multiplexing on the orthogonal components; ωI indicates the phase rotation in the color subcarrier; ωI and ωS
' indicates that the phase of the color line carrier wave is shifted by π due to the horizontal scanning period. l w JP indicates the change process of the color subcarrier vector, and l-7 and l'~
S' indicates that the phase of the color subcarrier is shifted by π. Further, A and -A indicate multiplexed signals into orthogonal components, and indicate a case where A and -A become adjacent horizontal scanning periods at a certain point in time. In current television broadcasting, due to the relationship between the frequency of the color subcarrier and the horizontal scanning frequency, the color printing carrier waves are l, m, FL, 0-., I and l', rd, n' in adjacent horizontal scanning periods.

The phase is shifted by π as shown by O'...J/.

When multiplexing into orthogonal components is performed as shown in Figure 9 (bl),
If the television video signal detection method is envelope detection, S and l will cause phase fluctuations in the video carrier wave.
During this period, an explosive amplitude of the color subcarrier appears, causing a phase shift φ between the maximum amplitude phase l in the case of no orthogonal component. The phase variation of the color subcarrier appears as a hue change on the reproduced video screen. With this phase fluctuation, in the video signal detection method or the synchronous detection method, only the cotωct direction component of the rotation is detected, so even if there are many A's, the maximum amplitude phase of the color subcarrier is l,
No phase variation occurs. In the case of envelope detection, depending on the sign of the 11L signal, CT and: 2 (indicated by A and -A in Figure 9)K
When the orthogonal components are multiplied, the phase direction (phase lead or lag) of the maximum amplitude of the color subcarrier is determined, and the amount of phase vibration is determined by the absolute values of A and -A.

When the phases of multiplexed signals are A and -A in adjacent horizontal scanning periods, as shown in IbI in Fig. 9, the phase fluctuation directions of ω and ω,′ become opposite directions, and the amount of phase vibration becomes the same. - The hue change of the screen in adjacent horizontal scanning periods is reversed by the signal, and it is possible to feel the hue change due to the frequency characteristics of the chromaticity sensitivity of human vision (integral effect of the eye). That is, α in Figure 8.

Since the multiplexed signal is in reverse phase like A and -A between the horizontal scanning period in which the same data is input in opposite phase, such as ~α and ζ~aha bx~bs and C~n, Difficulty perceiving hue change. However, in horizontal scanning periods where the same data is not in reverse phase, such as ζ~'; In a receiver that employs a ``<C-shaped filter'' (correlation) to separate luminance signals and color signals, phase vibrations of color subcarriers can be canceled out using a circuit. Figure 10 (α)
2 shows a configuration diagram of a comb filter for extracting color signals for membrane-level tile level signal color number separation, and [Al shows a waveform diagram for explaining the operation.

1001 is an input terminal, 1002 is a delay circuit, 1005 is a nasal reducer, 1004 is an output terminal, 1005 to 1008 are 1
This is the waveform of the color subcarrier. 1005 & If there is no multiplication, 1006 is the summary 9 diagram (right side of bl, 100 ha x Figure 9 1)
．． 6), 1008 is the inverse of 1007. The color subcarrier in the case of no multiplexing is shown in FIG. 9 (a fluent mosquito large waveform 1005 at time l corresponding to C1. Here, when the multiplexed signal of A is added, the maximum amplitude is between I and l. The waveform 1006 appears.

Also, in the next adjacent horizontal scanning period, the multiplexed signal of -A is added ω
The maximum aim phase of the color subcarrier of I' appears between I and 9', resulting in a waveform 1007. Delay episode W! Waveform 1006 and waveform 100 delayed by one horizontal scanning period after passing through 11002
7 is added to Akishinki 1005K. The inversion of waveform 10070 is shown as waveform 1008, but from waveform 1006 to waveform 10
Subtracting 07 means adding waveform 1006 K waveform 1008, and further increasing the amplitude by 172 results in waveform 1.
It becomes 005. This waveform 1005 is obtained from the output terminal 10 port 4.

It shows that the color subcarrier obtained by this comb filter does not undergo phase fluctuation even if the video signal detection method is envelope*detection and multiplexed signals are added. In this case as well, α! shown in FIG. Since there is no phase fluctuation only when processing horizontal scanning periods in which the upper and lower data are in opposite phases in adjacent horizontal scanning periods, such as ~α and α1~i,
A horizontal scanning period that does not undergo phase fluctuation appears every horizontal scanning period.

As shown above, in addition to the m1 diagram, the Ichimiura example of the present invention shown in FIGS. There are young fruits that can reduce disturbance without causing a change in hue.

Note that in FIG. 6, the time axis compression circuit 602 is used because the °C input data is continuous data; however, if the input data is intermittent discontinuous data (this may not be necessary).

Next, the interference caused by mono-orthogonal multiplexing to the phase of the video color subcarrier of current television broadcasting will be explained using a formula.

Acozat is the orthogonally multiplexed gKg, cotωct is the multiplexed video carrier wave, Bcolbt is the low frequency video signal of the television signal having both side bands, and Bcolbt is the video signal to be multiplexed.
If the color subcarrier of polarization is 5cos bt, adder 1
20 output c (tl is CItI= (1+Bcosbt +5cozst)
eosωct Ten Acozat ziTLωct
It is shown as 31. Here, αt and bt
This is to omit the complexity of calculations due to the level difference between the upper and lower sidebands due to the construction, equalizer 122, and Nyquist filter of the 1m TV receiver. By sending Ctt+ and passing it through a QIVSB filter, cog(z-ωc
) The first transmission C tI excluding the component of t is +(Ac
ozat --coast ) zinωct
(Represented by 41.The Nyquist filter output c, 1t1 of the television receiver 1! which receives this signal is converted into Σ along with the video carrier wave and nearby sideband waves, and the carrier wave is converted to an intermediate frequency by ωitK.

'J=-y C1+Bc01bt+5OO1,tt)"+
(Acosat -f; cots t )" ) cos
(No. 0 is -θ) (51).

However, . This C"x (from tl, comprehensive detection output Rn (
tlk@Rn(tl=,, E(1+5")+B"co
s”bt +2Bcopbt12BScozbt *
cos z t +2Scozz t-2ASaoza
t * z * n z t +7Icoz”a t)
(It becomes 71, and when the square root is approximately expanded, it becomes +BScozbtacozzt+5cozst.

Here, if the term #t related to the color subcarrier is extracted from Rn(t), the received color afM transmission wave Rdt) is.

-Acosαtz*nzt) ・cot　(z　t+φ](9B however becomes.

From equation (10), it can be seen that the polarity of the multiplexed signal corresponds to the phase shift of the interference received, and the phase shift of the interference is reversed due to abhorrence.

A conceivable method of utilizing the above-mentioned explanation and the visual effect is to transmit adjacent data with polarities as opposite as possible. In other words, if the direction of phase fluctuation between the data of class 111 is opposite, the hue change of the screen will be opposite between the data that are in instant contact with the same signal, and the frequency characteristic of the chromaticity sensitivity of human vision (the integral effect), it is possible to make the hue change less perceivable. To realize this method, in the digital modulation circuit 115 in FIG.
This can be achieved by modulating the M or pE diet.

As mentioned above, according to the embodiment of the first factor, codes such as FM and PR are used and multiplexed in reverse phase between 1llllll minute data, which has the effect of reducing interference to the hue of existing television receivers. In addition, since the carrier frequency selection band of the carrier wave regeneration circuit or the response frequency band of the PLL of the television entertainment machine is within the band where the spectrum of the orthogonal multi-M signal is suppressed, it is possible to stably detect the damaged Kaimata multi-signal. There are some effects that can be done. Further, according to the one-line embodiment, since multiplexed signals of the same signal with opposite phases are transmitted in adjacent horizontal scanning periods, there is an effect that interference to the video 1 #2 signal can be reduced.

Next, another specific example of the processing circuit 115 shown in FIG. 1 is shown in FIG. Further, FIG. 12 is a diagram for reading an operation such as an example of a transmission data string of the present invention, and FIG. 16 is an example of a pseudo pattern of transmission data of the present invention. 11o1 is an input terminal, 110
2 is an inverter, 1105 is a delay circuit, 1104 is a timing generation circuit, 1105 is a changeover switch, 110
6 is an output terminal, 1201 and 1206 are timing waveforms within the timing generation circuit 1104, 1202 is an input data string, 1205 is an output data string of the delay circuit 1105,
1204 is an output timing waveform of the timing generation circuit 1104, and 1205 is an example of an uninvented transmission data string.

Here, the signal input to the input terminal 1101 is a 51 direct signal, and the block diagram shown in FIG. 11 is a tri-state digital circuit similar to FIG.

The data examples shown in FIGS. 12 and 13- are also 5-line signals.

Data string 1202 applied to input terminal 1101 is passed through inverter 1102 and delayed by time in delay circuit 1105 to obtain data string 1205. Note that the timing waveform 1201 is inverted every time τ. The timing waveform 1204 is inverted during the data period in the data string, and when it is on the upper side in the figure, the changeover switch 1105 touches the (A) axis, and when it is on the lower side, it touches the K (1:1) 1411. A data string 1205 is obtained at an output terminal 1106 by a changeover switch 1105 controlled by this timing waveform 1204.

The 151st diagram is a schematic representation of the data string 1205, using the timing waveform 1206 as a horizontal synchronizing signal, and matching it to a television screen. horizontal scanning direction vertically
t indicates the scanning direction. @15 As shown by the circle frame in the figure, in adjacent horizontal scanning periods, the top and bottom of each data are inverted. Inverting the data in adjacent horizontal scanning periods indicates that the multiplexed signals to the orthogonal components of the video carrier wave have an opposite phase relationship, and the effect of reducing the interference with the hue change of the video due to the multiplexed signal is shown in Figure 19. ,
This is the same as the one-shot in Figure 10.

In addition to the above %m11WK, according to the embodiments shown in FIGS. 11 to 13, since the multiplexed signals in adjacent horizontal scanning periods are of opposite phase, there is an effect of reducing disturbances caused by changes in the hue of the image. . Also, in all horizontal scanning periods, 1
Each theta has 14 modulus periods and an inverse phase circle, and the cancellation of hue changes becomes a mesh-like pattern as shown by the nine frames in Figure 15, so the disturbance to hue changes becomes glaze (or visual chromaticity). Because of the low sensitivity frequency K, there is a young fruit that can reduce the disturbance to the hue change of the image even more than in the case of gg6-8.

In the above actual product example, the transmission data string is one water scanning period [
The case of stitch number data is shown in the example of 7 data, but in the case of even number data, 6 data are used as shown in Figures 1i1414 to 16. FIG. 14 shows the 21st processing time v! Still another example of 6115 is shown. @ Figure 15 is a diagram for explaining operations such as an example of a transmission data string, and Figure 16 is an example of a simulated pattern of transmission data of the present invention. 1104 is a timing generation circuit, 1
401 is a timing input terminal, 1402 is a timing generator, 1501 1504, 1507 is a timing waveform in the timing generation circuit 1104, 1502 is an input data string of the input terminal 1101, 1505 is a delay circuit 11
05 output data string, 1505 is timing generation circuit 1
104 is the timing waveform of the output, 1506 is an example of a transmission data string of the present invention, and 1405 is an exclusive OR C (hereinafter abbreviated as EOR). In addition, the same symbols as in FIG. 11 indicate the same functions.

Here, the data strings shown in FIGS. 15 and 16 are sm signals.

The difference from FIG. 11 is that an exclusive OR 1405 is provided in the timing generation circuit 11o4, and the timing waveform 15
01 and 1504, a timing waveform 1505 is obtained at the output of the timing generation circuit 1104, and the changeover switch 11
It is to be controlled by City 1 in 05'. E OR14i is
By reversing the control timing of the changeover switch 11050 every horizontal scanning period, a transmission data string 1506 is obtained, and the transmission data TV screen 17 shown schematically in FIG. 16 is obtained.
This becomes a pattern on the screen.

In the actual 211m example as well, as in FIGS. 11 to 15, there is an effect of reducing the damage caused by the change in hue of the image due to multiple signals.

Next, the 51 direct conversion circuit 114 and the processing circuit 115χ shown in FIG.
Regular 21 box digital cable (7” T L, Cl
d O5, etc.)) are shown in Fig. 17 and Fig. 1.
Figure B.

It is shown in FIGS. 19 and 20.

Figure 17 is the same as the example of 51111f in Figure 4: the example of the chivalry circuit and the example in Figure 6 made with the tri-state fist digital circuit.
It shows the function. 1701 is a 215L digital data input, 1702 is an edge detection circuit;
A is a rising edge detection circuit, 1702B is a falling edge detection circuit, 1705 is a time axis compression circuit, 1704 is a delay circuit, 1705 is a changeover switch, 1706 is an inverter, 1707 is an adder circuit, and 1708 is a timing generation circuit. A and B of 1703 to 1704 indicate processing of the outputs of the rising edge detection circuit 1702A and the falling edge detection circuit 1702B, respectively, and have the same functions. The selector switch 1705 widens both the rising edge and falling edge signals.

B only means that the functions are the same.

The operation shown in FIG. 17 will be explained using the fifth factor and the timing chart shown in FIG. Ratio 5 diagram (α) 2 il! When a digital data waveform is input from a binary digital data input 1701, a rising edge is detected w! 11702A
.

From falling edge detection times % 1702#K, edges are detected as +t1 and Vl in FIG. 5, respectively.

As you will see, the output of the AND circuit 405 and the AND circuit 406 in the example of the 3 flit circuit shown in FIG.
Outputs a rising edge and a falling edge, respectively. When the edge detection circuit 1702 A, , B output is divided into data lengths T, each data string nest 7 is created.
You can think of it as a trap. Now, for the sake of explanation, the number of the data string of the system that processes the output of the rising edge detection circuits 1702 and 4 has an overflow A1 falling edge detection time @170
Assign the thread character B to the symbol of the data string of the thread that processes the output of 2B. The data strings yo1, 4, and B are time-axis compressed by the time-axis compression circuits 1705A and 1705B according to the timing of the timing generation circuit 1708, respectively, to form a data string 7.
Data strings 702 A and 702 B are obtained at the timing shown in 02. Changeover switch 17o5,4.

When B is closed toward (A), the output of the selector switch 1705B rises and the edge side signal 702
A, or the signal 702B on the bottom wedge side is selected as the output of the changeover switch 1705A. Changeover switch 1.70
The 5A output is inverted by inverter 1706 and added to adder circuit 1.
At step 707, the signal is added to the output of the changeover switch 1705B, and a 5-channel signal is obtained as the output of the adder circuit 1707. This operation will be explained using the time chart of FIG. FIG. 5 (The illusion is that the output of the rising edge circuit 1702A is converted to the time axis compression circuit 170.
Waveform compressed at 5A, Vl is falling edge circuit 170
The waveform obtained by compressing the 2B output with the time axis compression circuit 1705B, the inverted No. 16 of Hano, (AI is the 511L (I No. 1, (i Mesaki e) obtained by adding (-I and the 10 waveforms) This is an s-value signal obtained by adding the inverted signal, υ) beam) and ljl waveform. However, here, T indicates the length of one data after compression. When the selector switch 1705 is closed to (a), If so, the waveform of tel is output to the changeover switch 1705B, or the waveform of V) is output to the changeover switch 1705A, and the output of the inverter 1706 becomes the waveform of (AI).

Therefore, the output of the adder circuit 1707 is 3-value g! as shown in ≠). 1, and a data string 702 is output. Next, when the changeover switch 1705 is closed toward (+:i), the changeover switch 1705B outputs a waveform of V), the changeover switch 1705A outputs a 1g3 waveform, and the inverter 1706 ffl force becomes (1). The waveform will be Therefore, the output of the control circuit W6t7o7 becomes a waveform of υ) (a 5-value signal that is inverted with the AI waveform centered at the midpoint potential. However, if the selector switch 1705 is closed to 10,000 °C in (a), the delay circuit 1704, the signal is delayed by a delay time τt, that is, in the example of FIG.

Therefore, the output of the adder circuit 1707 becomes as shown in FIG. 7 704. This data string 704 is the same as the circuit output of FIG.

According to the embodiment shown in FIG. m17, it is possible to process quinary multiplication using a binary digital element.

@Figure 18 also shows an example of the fourth three-value conversion circuit and a tri-state
This shows the same function as the example shown in Figure 6, which is a nest created using digital signals.

1801 is a time axis compression circuit, 1802 is an edge detection circuit, and 1802A is a rising edge detection circuit;
B is a falling edge detection circuit. An example of m18 diagram is
Binary digital data is compressed on the time axis, and C edge detection is performed on the compressed take. I wanted to C
It becomes the pulse width of 1 data length interval after edge detection & processing in 1802 and compression. The example shown in Fig. m18 has the advantage that only one time-base clamping circuit is required.

Figure 19 is the same as the example of the 51Fji conversion circuit in Figure 4 and the example in Figure 11 made with a tri-state digital circuit.
Show function. 1901 is a timing generation circuit. Data column 1202 in Figure 12 for the operation structure of the 19th cause
Rising edge detection circuit 1702, 4 outputs, respectively.
Corresponding to the output of the falling edge detection circuit 1702B, the delay time τ of the delay/delay circuit 1704 is the time shown in FIG. ltl
l. Close to the (a) side when the level is low. A changeover switch 1705 controlled by this timing waveform 1204 causes the data string 1205 to become a sia signal to the output terminal 1.
709 obtained. The example shown in FIG. 19 has the advantage that a 5-channel signal can be obtained using 21@digital elements.

FIG. 20 shows the same function as the example of the 51@conversion circuit shown in FIG. 4 and the example shown in FIG. 14 made of a tri-state ψ digital circuit. 2001 k timing input terminal, 200
2 is a timing generator, and 2005 is an EOR.

The difference with Fig. 19 is that E O is in the timing generation circuit unit 1.
Setting R2005 is timing waveform straw 15 ugly 1501 and 1
504, the timing waveform 1505 is applied to the output of the timing generation circuit 1901, and the selector switch 1705 is set to ? It is to control ttlJ. The example shown in Figure 20 has the advantage that a five-value signal can be obtained using a binary digital element.

As you can see from the above explanation, the same-multiple 3 [signal is 2 &
Interference can be reduced by using a transmission format, but on the other hand, if the transmission band of multiple signals is constant, the transmission valley will decrease by T-1. It is also possible to change the numbers by using a partial response method, etc., which actively uses OU to compress the transmission band. Note that the partial response method is described in pages 157 to 142 of the Ohmsha edition of the digital in@ method published in September 1980, so the details will be omitted.

Further, in FIGS. 8, 15, and 16, the modulation method of a single signal is shown in a simulated manner in correspondence with a screen of a television video signal. In these cases, the multiplexed signal was explained as a synchronized signal in which a certain number of signals enter in the horizontal scanning period, but if the transmission speed of the multiplexed signal and the horizontal scanning period are not synchronized, the busyness is different from the horizontal scanning period of the multiplexed signal. If the horizontal scanning period of the video signal is approximately the same, a similar effect of reducing interference to video No. 46 can be obtained. Further, it is also possible to absorb this by setting the maximum data time in the horizontal scanning period or by increasing or decreasing the number of data in a certain pair of horizontal scanning periods.

FIG. 21 shows an embodiment of the receiver of the present invention that receives the signals transmitted in the above embodiments.

2101 is an antenna, 2102 is a high frequency N-width circuit, 21
03 is a frequency conversion circuit, 2104 is a reproduction I for the receiver
F y 4 # J, at 2105'! intermediate frequency amplification circuit, 21o6 is a video signal detection circuit, 2107 is video 1#!
Signal amplification circuit, 2108, color difference signal demodulation circuit, 21o9
is a primary color signal demodulation circuit, 2110 is a cathode ray tube, 2111
2112 is an audio intermediate frequency amplification circuit, 2112 is an audio FM detection circuit, 2115 is a voice signal output Itako, 2114 is a band pass filter, 2115 is a synchronous transverse wave circuit, 2116 is a carrier wave regeneration circuit, 2117 is a delay circuit, 211B is a subtracter ,2
119 is a 5 yearning separate circuit, 2120 is a code -wjR separate circuit,
2121 beam Q-tsuku regeneration circuit, 2122 switch, 2
125 is a time axis expansion circuit, 2124 is a timing recovery circuit, 2125 is a 211&& conversion circuit, 2126 is a digital demodulation circuit, 2127 is a gain digital signal processing circuit, 21
28 is the demodulated output signal of the digitally encoded and transmitted signal.

A television signal inputted from an antenna 2101 is amplified by a high frequency amplification circuit 2102, frequency-converted to an intermediate frequency for demodulation by a )ttJ wave number conversion circuit 2103, and passed through a IF filter 2104 for reception to an intermediate frequency. It is amplified by a frequency amplification circuit 2105. Tuning is performed by varying the local oscillation frequency of the frequency conversion circuit 2105. The video signal band from the signal amplified by the intermediate frequency amplification circuit 2105 is detected by the video signal detection circuit 2106, and the video signal amplification circuit 2107 detects the video signal band.
The gM1 circuit 2109 recovers the primary color signal from the luminance signal output from the output luminance signal and the chrominance signal output from the color difference signal demodulation circuit 2108.
So, t<,V.

Obtain the three primary colors of B and print on 7゛lauy'#2110.

On the other hand, the audio signal band is amplified by an audio intermediate frequency amplification circuit 2111, and transverse wave demodulated by an audio FM detection circuit 2112 to obtain an audio signal at an audio signal output terminal 2115. The above is the same as the conventional TV receiver.

In addition to the above, in order to demodulate the digitally encoded audio signal, the frequency conversion circuit 2105 selects and amplifies the digitally encoded audio signal band that has been multiplexed and transmitted by the bandpass filter 2114. At 2115, a carrier recovery circuit 2116
Using a signal synchronized with the carrier wave reproduced in , transverse wave demodulation is performed on a signal modulated with a component orthogonal to the amplitude modulation component of the carrier wave.

The demodulated waveform and -i! A subtracter 2118 subtracts the demodulated waveform which has passed through the A delayer 2117 and is delayed by one horizontal period.

By subtracting, the transmitted data is doubled and the white noise is only increased by a factor of 17. Furthermore, interference from images that are highly correlated in each horizontal period, such as image ghosts, can be canceled out and removed. The signal obtained by the subtracter 2118 is increased by +1. ．． 0. -1 is identified into five states. This three-bit digital eye code is converted into a digital code at a point with a low error rate (the so-called maximum aperture of the eye pattern) using a separate circuit 2120 and a readout circuit 2121.

Only the necessary data from the digitally encoded signal is selected and extracted by the switch 2122 and the timing recovery circuit 2124, and the original data transmission rate is restored by the time axis expansion circuit 2125. After that, the 51m digital signal is converted into a +1, 0 binary digital signal by a binary conversion circuit @ 2125, modulated by pE, FM, etc. by a digital demodulation circuit 2126, and processed by a digital signal processing circuit 2127 during transmission. Errors are detected and corrected using an error construction correction code. A digital signal after error detection and correction is obtained at an output terminal 2128.

Note that interference removal from the video signal is performed in the following process. If data X is sent at a certain timing in a certain horizontal scanning period, the same data X is sent at a certain timing in the next horizontal scanning period with a delay of one horizontal period.
The inverted X data is sent. Receiver delay device 21
27 and the subtracter 2118, the X received during one horizontal scanning period and the X received during the next horizontal scanning period are subtracted at the same timing, so that X-CX)=2X, and the signal of 2 borrows is superior. During this transmission, the image
Assuming that the signal receives interference from G, the video signal has a high correlation with the horizontal scanning period in the image O1! (Images such as vertical stripes)
In this case, G will interfere with both the X timing and the X timing. By the subtracter 2118, CX+G)-CX+G)=2X, and the interference from the video is canceled out. However, if the correlation between the horizontal scanning periods of the video signal is small, the canceling effect will be reduced.

The receiving side pressure deviation explained above is caused by the carrier wave regeneration circuit 2116
Since the carrier wave 8 wave number selection band and the &LPLL response frequency band are within the band where the spectrum of the orthogonal multiplexed signal is suppressed, stable Tlc orthogonal multiplex signal can be transmitted, and furthermore, interference from the video can be reduced.

FIG. 22 shows a specific example of the 51 direct identification circuit 2119 and the code identification circuit 2120 in FIG. The same reference numerals as in FIG. 21 indicate the same functions, 2101 is the 51-direction digital detector, 2102 is the titg cut capacitor, and 2103 is the DC operating point OV (
GND ) useless resistance, 2104 &! Amplifier, 2
105, 2106 are comparators, 2107,
2108 is a transfer voltage source, 2109 e211 (N error), 21114 machining door tgi path, and 2112 is a 51 direct attached output forceps.

In Diagram 25, (al is 811! digital data, (bI & ecomparator 2205 output, s+i ecomparator 2206 output, ktjtX, ayri, N number,
ia+ is the latch 22o9 force, or the latch 2210 output %-) I work 5111 (addition circuit 2211 output). The 51st direct digital data inputted from the input A terminal 2201 is connected to the capacitor 2202 at t! 1LvIL will be cut. Since the 5-wax digital data does not include low-range acid content, it becomes the operating point or UV due to the resistor 2205, and the amplifier 2204 surpasses the shaping of the term 1st order n25th factor (C). The ω force of the amplifier 2204 is determined by the comparator 2205.
, 2204S respectively reference voltage source 2207°22
It is compared with the voltages r1 and r4 generated at 08 using the polarity shown in the 22nd factor. The voltage 0 generated by the reference voltage source 2207 and the voltage 4 generated by the reference voltage source 2208 are adjusted to voltage values such that the number of code errors is minimized, as shown in the 25th line 1G+. Comparator 2205,
The outputs of 2206 are shown in Figure 23 (bl, (C)).
The comparator 2205 identifies +1 of the 3-value digital data, the comparator 2206 identifies -1 of the 5-value digital data, and the comparator 220
5゜2206 The output is regenerated by the latches 2209 and 2210 in the Ω-tock regeneration circuit 2121, and latched at the +d+ timing in Fig. 25 using the a-tock signal, becoming a digital signal synchronized with the clock signal.
The outputs shown in FIG. 23 (el, (7°)) are obtained respectively.However, the output of the latch 2210 is in opposite phase.Adding these two latch outputs in the adder circuit 2211 is the same as that of No. 51. Encoded and superior.

According to Figure 22, the circuit configuration is quantitative, and 511
2501 in Figure 25 (α) in 1L digital data,
Even if unfavorable noise such as 2502 is mixed in, as long as it is not present at the rising edge of the clock signal, it will not have a large effect on the demodulated binary digital code and will have the effect of not deteriorating the bit error rate characteristics. .

FIG. 24 shows a five-value identification circuit 2119 and a code identification circuit 21.
This is another example of a circuit with a power of 200 min. Figure 21.

Items with the same symbols as in FIG. 22 indicate the same functions, and 2401
is a sample reference hold circuit (hereinafter abbreviated as S/E circuit),
2402 is a check signal, and 2403 is an inverter. The 24th blood will be explained using the operation explanatory diagram of FIG. 25.

Figure 25 (C1 is 5-value digital data, (b) is a clock signal, (C1 is S/H circuit 2401 output, μ)
is comparator 2205 output, (C) is comparator 2
206 output.

Ul is the output of the inverter 2405, and K) is the 311IL code and is the output of the adder circuit 2211. S/H circuit 2
401 is a clock regeneration circuit 2121 which samples at the rising edge of the beat signal 2402 and holds the value until the next sample as shown in FIG.
The clock signal 2402 reproduced by is a signal with one data length T as one period, and the rising edge of the clock is located at a point where the bit error rate is low (the so-called maximum opening of the unpatterned pattern). S/H circuit 2401 output is second
5 11! is shown in Figure 5 + CI and input at input terminal 2201. L digital data read a check signal 240
The digital code of the s value synchronized with 2 is identified. Below 5
The value digital code is input to the comparators 2205 and 2206, and the 5-value digital code is identified as +10j-1 in the same way as the operation explained in the 22nd factor, and the comparator 2206
The output of the inverter 24o5 is inverted, and the output and the output of the comparator 22o5 are connected to the Toguchi Makoto circuit 2211.
The 511m code shown in the 25th factor 1 is obtained at the output terminal 2211&C. By using the circuit shown in FIG. 24, even if a noise like that shown in FIG. This has the effect of not deteriorating the bit error rate characteristics that affect digital codes.

The 26th factor is the 5-value identification circuit 2119 and the code identification circuit 2.
It is another circuit power with 120 degrees of caution. The number with the same sign as the 24th factor indicates the direction, and 26o1 is S
/ HtgJ road, 26o2 is a wind comparator.

2605 and 2604 are adders, and 26o5 is an intermediate level detection signal.

The basic operation of gl & 26 is the same as that of 24.

Parts that operate differently from those in FIG. 24 will be explained using FIG. 27.

In FIG. 27, (C1 is 5-value digital data, (b
) beam Ωtsk signal, (C1 is S/If circuit 2401
The output, tdl, is the window comparator output (intermediate level detection signal 2605). Now antenna 2101
No. 18 received by the input terminal 2201 is distorted by the spatial transmission path or other causes, and as a result, the 5-digit digital data input to the input terminal 2201 has a pulse of 1 izlh level with respect to the intermediate level, as shown in aR277 (α). Consider a case where the pulse is higher than the low level pulse.

At this time, is the 3-level digital data a DC component? : If the signal becomes a normal signal and the capacitor 2202 cuts DC'' and the resistor 2205 determines the operating point, the intermediate level as shown in the 27th cell (α) will not become OV.

This signal is transmitted using the S/H circuit 24o1 as shown in FIG.
If you sample at the rising edge of 24oz and hold that value until the other sample point, you will get the waveform shown in Figure 27 (CI), which is a signal with an offset of ΔV at the intermediate level.The qI signal in Figure 27 to+ are input to the comparators 2205 and 2206, and the window comparators L/-2602 and S
/11 circuit 26o1 input. Wind Convergence It 2602 Detect the intermediate level part from the signal of tC+ in Fig. 27 and set the H level to 27 during that period.
Output as shown in figure tdl. Note that the intermediate level detection signal 2605 can also be generated from the outputs of the comparators 2205 and 2206. S/E circuit 2601
receives the output of this window comparator 2602, the output of the window comparator 2602 is 1iilk
The signal is sampled during the period of , and the period of low is held.

By operating in this way, the S/E circuit 26o1 becomes 5
It is also possible to extract the intermediate level offset ΔV of the 1st shift digital data. Here, the output V8 of the reference voltage source 2207 and the output of the reference voltage source 22o8 are 0 VCGND)
Because it is set based on the standard, it is 51! If there is an offset of Δr at the intermediate level of the digital data, the error will be that much. Therefore, the error component ΔV is calculated using the adders 2605 and 2604 [Respectively, the reference voltage source 22
o7 Output L'□, -#, *Voltage source 2208 By calculating output 4 and 71Ill, a breakthrough reference voltage can be given to comparators 2205 and 2206. As described above, according to the circuit configuration shown in Figure 26, it is possible to cancel the influence of unbalance between high and low pulse heights on the intermediate level of 5-value digital data, and to convert 3-value digital data using the optimal reference voltage. Three-value identification of signals can be performed. Note that the error voltage cancellation circuit shown in FIG. 26 can also be used as a five-value discrimination circuit for the twenty-second factor. Also, if you want to take the output polarity of the latch 2210 in FIG. 22 from the positive phase output, you can reverse the comparison polarity of the comparator 2206 (and if you do the same,
The inverter 2406 in Figure 26 can also be omitted.

Next, the delay circuit 2117% subtracter 211 shown in FIG.
B. The detailed operations of the switch 2122, time axis expansion circuit 2125, and timing regeneration circuit 2124 will be explained.

The motion of the rear legs when the transmission data string 704 is received by the 28th prisoner is shown. 2801 is a timing waveform for synchronizing the horizontal scanning period; 2802 is a transmitted and received data string; 2805 is a data string output from the delay circuit 2117;
804 is a data string of the output of the subtracter 2118, 2aos
! timing waveform obtained from the timing waveform 2801, 2806 is a data string of the output of the switch 2122, 28
07 is an output data string of the time axis expansion circuit 2123.

The received data string 2802 becomes a data string 2803 by the delay circuit 2117. The data string 2802 is subtracted from the data string 2806 by a subtracter 2118, and the five-value Seibetsu circuit 21
19, sign'@identification circuit 2120, rip-a-tsuku reproduction circuit 21
21 over data string 2804. Timing waveform 2
A data string 2806 is obtained by controlling the switch 2122 so that the upper side of the switch 805 is in contact with the switch 2122 . In addition, in the data string 2806 and the data string 2807, 2'@ is omitted such as 2α and α1. The data string 2806 becomes the data string 07 by the time axis expansion circuit 2123, and the transmission g! ! It becomes the original data string 701 on the side.

In addition, data strings 2802 to 2804, 2806, 0
7 is the s value, switch 2122, time axis expansion circuit 2
125 and the like are constructed of tri-state Φ digital circuits (the unnecessary data portion of the data string 2804 has five values).

Figure 29 shows the demodulation operation when receiving the transmission data string 1205 in Figure 12. 2901 is a timing waveform for horizontal scanning period synchronization % 2902 is a transmitted and received data string 2903 is a delay circuit 2117
The output data string, 2904 is a subtracter, 2118
2905 is the timing waveform, 2
906 is the output data string of the switch 2122, 2907
is the data string of the output of time axis expansion W62125.

The received data string 2902 becomes a data string 2903 by the delay circuit 2117. When the data string 2902 is subtracted by the subtracter 2118 from the data string 2905, the data string 2
904 is obtained.

When the switch 2119 is activated on the upper side of the timing waveform 2905, a data string 2906 is obtained. The data string 2906 becomes a data string 2907 by the time axis expansion circuit 2125K, and returns to the original data string 1202 on the sending @ side shown in FIG.

Note that in data string 2906 and data string 2907, 2 no 1
etc., the display of double numbers has been omitted.

FIG. 30 shows the demodulation operation when receiving the transmission data string 1506 in FIG. 15. 5001 is a timing waveform for synchronizing the horizontal scanning period, and 5002 is a timing waveform that is transmitted.
'C whistle data string, 3005 is delay circuit 21170
is a force data string, 5004 is a data string of the output of the subtracter 2118, 5005 is a timing waveform, 5006 is a timing waveform that is inverted every horizontal scanning period, 5007
is the timing waveform obtained from the timing waveform 5005 and the timing waveform 3006, and 5008 is the switch 212
A data string holding a value of 2, 3009 is a timing waveform, and 3010 is an output data string of time axis expansion @2125. The received IN l, the data string 3002 is the late arrival l62
117 becomes a data string 3003. data string 500
When data string 3002 is subtracted from 3 by g calculator 2118, data string 5004 is superior. Timing waveform 3
005 and the timing waveform 50 (16Y exclusive-rational arrangement (EC in Figure 14) Same operation as R1405) The switch 2122 is made conductive at the upper side of the obtained timing waveform 3007, and the interruption period of the switch 2122 is the conduction period. 1
Data data 13500B is superior if the box is held. This is a digital circuit that is latched on the upper side of the timing waveform 50 lower. This data string 30
By latching 08 at the falling edge of the timing waveform 6009, the data string 50101't? is output from the time axis expansion circuit 2125. 4). This data string 5
010 is the original data string 1502 on the sending side shown in FIG.
matches. Note that data string 3008 and data string 3
In 010, double indications such as 211 are omitted.

As can be seen from the above explanation, interference can be reduced by transmitting the same multi-N code twice in opposite phases.

FIG. 31 shows a specific example of the 21st factor digital demodulation circuit 2126 when receiving the 1B signal FM tuned by the digital 16 modulation circuit 115 of FIG. The same reference numerals as in FIG. 21 indicate the same functions, 51o1 is a synchronous detection circuit output, 5102 is a window comparator, 3105 is a latch, 5104 is a digital data output, 5105 is a subtracter, and 3106 is an M extension circuit. The operation of factor A51 will be explained using FIG. The timing chart for the 32nd prisoner is shown as 51 cases of endorsement, and the 51st cause is shown as 70 points and 7tl. Further, 5210 and 5211 are comparator levels of the window comparator 3102. Data 5208 on the transmitting side undergoes FM modulation and becomes an FM signal 3201, which is output from the synchronous detection output 3101. signal 5201
is delayed by the delay circuit 6106. 1g No. 3202
The subtracter 5105 calculates 7JR from the signal 5201.

This operation inverts the signal 5202 (signal 52o5) to 1
! This is equivalent to adding the number 3201 to the number 3201. Subtractor 510
The output of 5 also becomes a 5-value signal as shown in the engineering signal 5204, which is converted to a comparator level by the window comparator 3102. Voltage between 5210 and 5211,
That is, the midpoint potential is detected and a signal 5205 is obtained. The signal 3205 is latched by the latch 3105 using the clock 3206 regenerated by the a clock regeneration circuit 2121.
An output signal 5207 without whiskers is obtained. Output signal 5207
It is 3209 expressed as digital data, but it can be seen that the data 520B IIC before including JF5 is equal. The digital rear leg circuit in Fig. A31 has a signal 520
4, the midpoint “potential is 1-1 of data 5208 before transmission”
This takes advantage of the fact that it corresponds to 1. Although the signals 5201 to 5204 are shown as rectangular waves in FIG. 52 for simplicity, they are actually signals that are limited by the band f#lj and have no harmonic components. According to this embodiment, the demodulated waveform delayed by one data length (half data length from the data before transmission), which is the minimum data inversion period, through the delay device 3106? : Since subtraction is performed by the subtractor 5105, the interference from the video with a high correlation can be canceled out and removed by the low frequency component, which has the effect of reducing the interference from the video.

FIG. 55 shows the PE in the digital i-key circuit 113 of FIG.
FIG. 21 is a specific example of the digital demodulation circuit 2126 when receiving a modulated signal. Figure 21.

The same reference numerals as in FIG. 61 indicate the same functions, and 33o1 is Combaret/, and 5502 is Eratch. The operation shown in FIG. 33 will be explained again using FIG. 34. FIG. 54 shows the timing chart of FIG. 53, and FIG. 35 shows its part υr. 15ato is the comparator level of the comparator 53o1. Data 34o8 before transmission is PE
It undergoes modulation and becomes a PR signal 34o1, which is obtained from the synchronous detection output 3101. The 1M number 34o1 receives a delay in the -M extension path 5106 and becomes a signal 54o2, which is sent to the subtracter 6.
1o5 is subtracted from the signal 34Ω1. This operation causes the signal 5402' to have an anti-$1i1=Lte (! No. 5aO5)
This is equivalent to calculating signal 5401 Vc71D. The output of the subtracter 3105 is a ternary signal as shown in the signal 3404, which is converted to a comparator level 5410 by a comparator p5501.

A signal 5405 is obtained by identifying the midpoint potential. Clock 5406 which is regenerated from signal 3405 by reproducing circuit 2121
Using &C, as shown in FIG. Output signal 3
It can be seen that 5409, which represents 407 in digital data, is equal to data 5408 before transmission. ! The digital return W4 circuit shown in FIG. 55 utilizes the fact that every other data signal 5404 is equal to data 5408 before transmission. Note that in FIG. 34, signals 34 to 5404 are shown as rectangular waves for simplicity, but in reality they are band-limited and are signals without harmonic components. This example has the effect of reducing interference from the video, similar to Figure M61.

FIG. 35 also shows i21 digital 'u' when receiving a PE modulated signal in the first worst digital modulation circuit 115.
This is a specific example of the i-key circuit 2126. The 21st factor, the same reference numerals as in FIG. S1 indicate the same functions, 3501 is a window comparator, 5502 is a latch, and 5503 is a T-flip 712 knob. The 36th prisoner shows the timing chart of the g551iW, and its location is shown in the 55th cause. Further, 5611 and 5612 are comparator levels of the window comparator 3501. The process until the signal 3604 is obtained is the same as in the diagram 5s. pE in Figure 55
The decoding circuit is based on the fact that the midpoint potential of the signal 3604 is the data change point of the data 5609 before transmission 1g, and the voltage between the comparator levels 5611 and 5612, that is, the midpoint potential, is determined by the window comparator 55o1. The potential is detected and a signal 5605 is obtained. signal 3
605 is latched by a latch 5502 using a clock 5606 regenerated by a reproducing circuit 2121 to obtain a signal 5607 without whiskers. This g! When the T-flip-flop 5503 is operated at the falling edge of No. 1 5607, an output qig 5605 is obtained. The digital data representation of the output signal 5608 is 5610.
Something strange can be seen in the data 5609 before transmission. In addition! ! In Figure 56, signals 5601 to 560 are used for the quantity rate.
4 is shown as a square wave, but it is actually band-limited,
The signal is free of harmonic components. This example has the effect of reducing interference from images, similar to the case shown in FIG.

Next, 51f! In the case of demodulating L-polarized code, a circuit for demodulating using a normal 2111 digital circuit without using a tri-state digital circuit will be explained with reference to Fig. 37. Figure 57 shows the three-value identification circuit 2119 code @ Seibetsu circuit standard, switch 2122, time axis expansion circuit 2123
FIG. 3 is a block diagram of a case where the circuit is constructed using a 2111 daisimel circuit. The same symbols as in FIG. 21 indicate the same functions, and 2
119Ak is a negative pulse identification circuit, 2119B is a negative pulse identification circuit, 212 DA is a positive pulse detection No. 16 code Makoto circuit, 2120B is a negative pulse detection signal code Takabetsu circuit, 2122A is for a positive pulse detection signal switch.

2122B is a switch for negative pulse detection gA, 212
5A is a time axis expansion circuit for positive pulse detection signal, 2125
B is a time axis expansion circuit for negative pulse side ratio signals, 3701 is a 6111 digital signal input terminal, and 5702 is a 2D digital signal output terminal. The 57th has two identical circuits, one for processing on the positive pulse side and the other for processing on the negative pulse side. Those with the code 1/CA handle the processing on the positive pulse side, and the ones with B handle the processing on the negative pulse side. conduct. The output of the subtracter 2118 is inputted from the 5-level digital signal input terminal 5701, and from the signal, the +1 part of the 51-channel digitel signal is identified by the positive pulse identification circuit 119A, the -1 part is identified by the negative pulse identification circuit 2119B, Each outputs an identification signal. Hereinafter, each identification signal is transmitted to the code identification circuit 212OA,
2120 B, and further encoded in FIGS. 28 to 30
The switch 2122A performs the same process as the operation explained above.
, 2122B time axis expansion circuit 32124A,
2125B on the positive side and negative side, respectively, and the positive pulse construction signal of the time axis expansion circuit 212SA output and the negative pulse detection signal of the time axis expansion circuit 2125B output are 2
It is input to the group conversion circuit 2125 and a 21-digit digital signal is obtained from the output terminal 5702. To return the signal converted to 61#L in Figure 4 to a binary value, the rising edge of the 2nd half data corresponds to +1 and the falling edge corresponds to -1 (0)
So, 24K conversion lol! 12125 Using VCR5-7 lip flop, time axis expansion circuit 212 for set input.
It is preferable to input the positive pulse configuration signal of the SA output and the negative pulse detection signal of the output of the time axis expansion circuit 2125B to the reset input. The case of FIG. 37 has the feature that it can be constructed using a normal binary digital circuit.

An example of a circuit having the configuration shown in FIG. 37 is shown in FIG. FIG. 58 is constructed using the 22nd circuit.

The same reference numerals as in FIGS. 21 and 22 indicate the same functions.

5801 is an MS-7 lip 70 tube, and 58o2 is a two-channel digital signal output terminal. FIG. 58 shows an example of a circuit for receiving the transmission data string 1205 in FIG.

The explanation of the Mouse 58 diagram will be given using the 59 factors. In the diagram, (α) is the three-value digital data, (b) is the output of the comparator 2205, [C1 is the output of the comparator 2206, (d+ is the Ωtsk signal, and (-) is the ratte 2209
Output, σ°) is latch 2210 Output, (90 min 21
1m digital data (R5-flip-flop 680
1 output). Comparators 2205, 220
The operation until output No. 6 is obtained is the same as that shown in FIG. 22. The output of the comparators 2205 and 2206 is the latch 22
09, 2210, a-track regeneration circuit 2121
It is latched at the timing μ in Fig. 39 using the clock No. 1 regenerated in , and becomes a digital signal synchronized with the Ω clock signal. Here, the clock re-main circuit 2121
The clock signal kLl in FIG. 59 reproduced by the clock signal (kLl) shown in FIG. (See Futsu's 2904).In other words, latch 2209
, 2210 are the code identification circuit 2120, the switch 2122, and the time axis expansion circuit 2125, respectively.
The output of the latch 2209 is the 39th
(c), the output of the latch 221o is shown in FIG. It is as if the positive pulse and negative pulse of the L digital signal were detected.

Now, if the 51st section digital data is modulated as shown in the 39th prisoner (C1), then the 21st variable circuit 2
125 consists of MS-7 lip 7o tube. That is, since +1 of 5-value digital data means a rising edge of 2-value digital data, and -1 of 3-value digital data means a falling edge of binary digital data, the output of latch 2209, which is rising information, is sent to R5-7 lip-flop 3801. By inputting the latch 2210 output, which is falling information, to the set terminal S of R5-7 and the reset terminal R of the lip 5801,
R5 - Flip-flop 5801 5th from output terminal
9INC! The binary digital data shown in Il can be demodulated.

As shown in FIG. 58, n has a simple circuit configuration and has the effect of being able to receive 51 direct digital numbers without using a tri-state digital circuit.

FIG. 40 is also an example of the wandering circuit shown in FIG. 57, and is constructed using the circuit shown in FIG. 24. Figure 24.

The same reference numerals as in FIG. 68 indicate the same rudders. FIG. 40 is also an example of a circuit for transmitting data listed at 1205 in FIG. 12 and receiving. Figure 41 is an explanation of the operation of Figure 40.
Figure (αJ is 5-value digital data, Cblk equation 1a'9j, tC+ is S/11 circuit 2401 output,
μm (Ecosovarator 2205 output, ig+ is comparator 2206 output, V) is 2 im digital data C
B5-7 Rig Hub 6801 output). 40th
The difference in operation from FIG. 24 in this figure is that the frequency of the SlH link signal (A) in FIG. 41 has been doubled, and the reason for this is the same as that explained in connection with FIG. 58.

Hereinafter, a 21m digital signal can be obtained at the output terminal 5802 by the same operation as in FIG. According to Figure 40 of the theory, it was a slow episode lol! With I-switching, it is possible to receive a 51 direct digital code without using a tri-state digital circuit. Similarly, it is also possible to utilize the circuit shown in FIG.

1iI442 is also an example of the circuit having the configuration shown in FIG. 37, and is an example of the circuit when receiving the transmission data list 1205 in FIG. 12.

22, 38, and 40 indicate the same functions, 4201, 4202 are gates, 4205
is a gate control circuit. FIG. 43 is a timing diagram for the glare in FIG. 42, where (α) is 31 [digital data% (bl is the output of comparator 2205,
l is the comparator 2206 output, Td+ is the gate control signal, (-) is the gate 4201 output, V) is the goo)
4202 output, υ) is binary digital data CB5-7
2801 output). Comparator 2
The operation until the outputs of 205 and 2206 are obtained is Atsushi 2.
It is the same as Figure 2.

Comparator 2205, 2206 output is gate 420
1.

4202 K are each input and gated.

The gate signal is generated by the gate control circuit 4205 using the clock obtained from the clock regeneration circuit 2121, and is input to the comparator 22 as shown in FIG. 45 (d+).
Of the normal data rise of 05°2206,
The critical data (second data column)
2904g in Figure 9).

In other words, it is gated in eight periods, which is twice the length of one data being transmitted. As a result, the outputs of comparators 2205 and 2206 are 4201 and 4202 respectively.
Figure 5 (11, gated as (7+, R5-
7 lip 7 Q Tsubu 5801 &C sent, 2 ill
Demodulate digital data. Note that the output terminal 3802
It is preferable that the digital data obtained from the above is further identified by the symbol '@' before being input to the next stage digital signal processing circuit 2127. According to the example in Fig. 42, even if unnecessary noise such as 4501 and 4502 in Fig. 45 (α) is mixed into the 5-year digital data, it will be a mess) ff
If it is not during the gate ON period of gate No. 1, the demodulated binary digital code will not have any shadows and will have the effect of not deteriorating the code error military status.In addition, in the gate control circuit 42o5, By providing multiple pulse intervals with different pulse intervals and monitoring the bit error rate, etc., it is possible to determine which pulse interval to select and optimize the bit error rate.Also, gate pulse timing It is also possible to change the bit error rate by monitoring the bit error rate, etc., so that the bit error rate is in the best state.

In addition, Fig. 38, Fig. 40, and Fig. 42 are 15 in Fig. 15.
06 can also be received. That is, the 68th u
The rise of the clock signal in the I man diagram and m42
The Bsh part of the gate signal shown in the figure is placed at the necessary data of 5004 in Fig. 50 (2m # 2ft a 2j'
s2!1t #2! After processing the latch, S/E, and gate, transmit both inputs or outputs of the R5-7 lip flop 38010 set and reset. By using a clock signal having a cycle twice as long as one data length, it is possible to latch at the pass point, as shown in 3010 in Figure 50.

FIG. 44 shows another example of the circuit having the configuration shown in FIG. 37.

Items with the same numbers as in Figure 22 indicate the same rudders, 4401
.

4402 is a memory circuit, 4403 is a memory control circuit, 4
404 is a digital signal processing circuit. Similarly to FIG. 42, the example of the 44th factor is also an example that has the ability to eliminate noise when unnecessary noise is mixed into the 3irJL digital data. The clock regeneration circuit 2121 regenerates clock No. 16 by n times the data transmission period, and using this, the memory control circuit 4405
05 and 2206 outputs are divided into clocks and stored in memory circuits 4401 and 4402 as digital data. Then, the digital signal processing circuit 4404 selects a set indicating the Hth part of the 5-value digital data, which is close to the normal data sample point, and removes unnecessary noise mixed into the 5-value digital data. Thereafter, it is converted into binary digital data by the R5-7 lip flop 5801.

The example shown in FIG. 44 has the effect of removing unnecessary noise mixed into the digital data 31 by applying extensive digital processing. It is also possible to select the most 1M sample point with the best bit error rate by selecting the normal data sample points with reference to the bit error rate. In addition, comparators 2205 and 220
6 outputs are input to the memory control circuit 4405 and the digital signal processing circuit 4404, and when the set pulse exceeds the above plurality of reset pulses, and when the reset pulse exceeds the above plurality of set pulses, the normal According to the circuit shown in Figure 0m44, which allows you to select the data sample point, the transmission data string is 704 in Figure 7, 1 in m12-.
205° Any of 1506 in FIG. 15 can be received.

FIG. 45 is a block diagram of a television signal transmission device as an embodiment of the present invention. The difference is that the processing order of the digital modulation circuit 115 and the three-value conversion circuit 114 is reversed.

FIG. 46 shows the modulation waveform of FIG. 45. (α) is the output data of the digital signal processing circuit 112, (b) is the output of the three-value conversion circuit 114, (C3 is the output data of the digital modulation circuit 11
This is the output of 3 and is the case when pE is applied. (11 is W1
3111 when processed by the five-value conversion circuit 114 adjusted by the digital modulation circuit 113 in the embodiment shown in FIG.
This is the output of the conversion circuit 114. [From dl and (#), it can be seen that there is an effect IC left. Digital modulation circuit 1
13, of the data converted into 51 by the 31μ conversion circuit 114, +1-1 is subjected to °C processing, and 0 is output as 0 without any processing.

47, 48, 49, and 50 show that the embodiment shown in FIG. 45 is realized by an ordinary binary digital circuit. The same reference numerals as in FIGS. 18, 19, and 20 indicate the same functions, and 4701A and 4701B are digital conversion circuits. ! Figure 47, Figure 48 1m4
The movements shown in Figures 9 and 50 are shown in Figure 17, respectively.

It is almost the same as Figure 18, Figure 19, and Figure @20,
The images in Figures 8, 15, and 16 are the (turns), respectively.

Figure 51 shows an embodiment of the receiver of the present invention which receives the signal transmitted in the embodiment of Figure 45. The same symbols as in FIG. 21 indicate the same functions. W! ;The parts that differ from Figure 21 are digital, and the demodulation circuit 2126 is the time axis expansion circuit 2123.
Manslaughter & C connection. First, after demodulating in the digital demodulation circuit 2126, the 2-box conversion circuit 2125
The 5-value signal is converted into a 2-value signal.

The 52nd factor implements the embodiment of FIG. 51 using an ordinary binary digital circuit. The same symbols as in FIG. 37 indicate the same functions, and 2126A and 2126B are digital demodulation circuits. The operation shown in Figure 52 is almost the same as that of its younger brother, Figure 37.

As mentioned above, according to the embodiments from Figure 45 to Figure 52, the first
Similarly to FIGS. 21 and 21, there is an effect of reducing interference from images.

FIG. 55 shows another embodiment of the receiver of the present invention for receiving the signal transmitted in the embodiment of FIG. 1Js. The same symbols as in Figure 21 indicate the same functions, and 5501 is Oi7. true circuit,
5302 is a delay circuit.

Consider the case where pE is applied in the digital modulation circuit 113 in Figure 45.

Figure 54 shows the screen pattern of the transmission signal. The operation of demodulating this transmission screen pattern will be explained using the timing chart of FIG. 55. 5501 is a transmitted and received data string, 5502 is a data string output from the delay circuit 5302, 550t is a data string output from the subtracter 5501, 5504 is a data string output from the delay circuit 2116,
5505 is a data string of the output of the subtracter 2115, 550
6 is the output waveform of the a-c reproducing circuit 2121 that is input to the code identification circuit 2120, and 5507 is the code identification excitation waveform w1.
2120 output data string, 5508 is the switch 212
2K is the output tying waveform of the timing regeneration circuit 2124 that is input, 5509 is the data string of the output of the switch 2122, and 5510 is the output data string of the time axis expansion circuit 2125.

The data string 5501 is delayed by one data length τ from the delay circuit 5502K to become a data string 5502, and a subtracter 5301 subtracts the data strings 5501 and 5502 to obtain a data string 5505. Next, the data string 5505 is delayed by the horizontal scanning period τ1 by the delay circuit 2116 to obtain the data string 5504.
505 and 5504 are subtracted to obtain a data string 5505. Here, the coefficients 2α1, 4α1, etc. in FIG. 55 indicate the magnification of the amplitude relative to the town. Also, data column 5505
Furthermore, in the data string 5507, meaningless data that does not have data information is shown with a rose.

The data string 5505 is input to the code identification circuit 2120,
A data string 5507 is obtained by latching at the rising edge of the timing waveform 5506. Data string 5507 is switch 2
At step 122, the data string 55o9 is transmitted only during the Highk portion of the timing waveform 5508, and the time axis is expanded by the time axis expansion circuit 2124K to obtain output data 5510.

The 56th factor shows another transmission screen pattern of FIG. 45. The operation of demodulating this transmission screen pattern will be explained using the timing chart of FIG. 57. 57o1 is the transmitted and received data string, 5702 is the data string output from the delay circuit 5502, 5703 is the data string output from the subtracter 55o1, 5704 is the data string output from the delay circuit 2116, and 5705 is the output from the subtracter 2115. data string, 570
6 is the output timing waveform of the a-c reproducing circuit 2121 that is input to the code identification circuit 2120, and 5707 is a data string output from the code identification circuit 2120.

The operation until the data string 5705, which is the output of the subtracter 2115, is obtained is the same as in the 55th case. 21. .

Coefficients such as 4g indicate amplitude multipliers relative to c, and meaningless data without data information are indicated by a rose. Data string 5705 is code identification circuit 2
120 and is latched at the rising edge of the timing waveform 5706 to obtain the data string 57o7. In this case, the code identification circuit 2120 is, in a broad sense, the switch 212
2. It also has the function of a time axis expansion circuit 2125, and the data string 5707 is input to the digital g signal processing circuit 2127.

Fig. 58 shows another transmission screen pattern of Fig. 45. The operation of demodulating this transmission screen pattern will be explained using the timing chart shown in Fig. 59. 59o1 is the transmitted and received data string, 59o2 is the data string of the output of the delay circuit 5502, 5903 is the data string of the output of the subtracter 5501, 5904 is the data string of the output of the delay circuit 2116, 5905 is the output of the subtracter 2115 data string, 59
06 is the output waveform of the clock recovery circuit 2121 that is input to the code identification circuit 212o, and 59o7 is the code identification circuit 21
20, 5.908 is a timing waveform that is inverted every horizontal scanning period, 59o9 is a timing waveform, and 591o is the output of the timing recovery circuit 2124 that is input to the switch 2122 obtained from the timing waveform 59o8 and the timing waveform 5909. 5911 is a data string holding the output value of the switch 2122, 5912 is the output timing waveform of the timing reproduction circuit 2124 input to the time axis expansion circuit 2125, and 5915 is the output data of the time axis expansion circuit 2125. It is a column.

The operation until the data string 59o5, which is the output of the m calculator 2115, is obtained is the same as in the case of FIG.
Coefficients such as # indicate amplitude multipliers relative to -8, and meaningless data without data information are indicated by rose marks. Data string 59o5 is code separation circuit 21
20 and is latched at the rising edge of timing waveform 5906 to obtain data string 5907. Data column 59
07 is input to the switch 2122, and the switch 2122 is made conductive at the upper side of the timing waveform 591o obtained by exclusively burying the timing waveform 5908 and the timing waveform 59o9. By holding , a data string 5911 is obtained. This can be implemented with a digital circuit that is latched on the upper side of timing waveform 5910. By latching this data string 5911 at the rising edge of the timing waveform 5912, a data string 5913 is obtained at the output of the time axis expansion circuit 2126.

As mentioned above, in the example of UkeqI Iso shown in Figures 53 to 59, by performing the subtraction process twice, the data quadruples, but the white noise only doubles. , it has the effect of being able to perform repetitions with a good signal-to-noise ratio. Furthermore, it has the effect of not only canceling and removing interference from images that have a high 1iIl correlation with low frequency components, but also canceling and removing interference from images that have a high correlation in each horizontal period, such as image ghosts. .

Note that interference removal from video No. 91 is performed in the following process. When data X is subjected to PE modulation, it becomes two data strings xx. This is connected to the delay circuit 550 of the receiver.
2 and the subtractor 5301 subtracts the received X of 1 data and the received X of the next data at the same timing, so that X - (X ) = 2X (11), and a signal twice as large is obtained. If G interference occurs from the video signal during this transmission, for images where the video signal is low frequency and there is a lot of correlation between adjacent data, even if the X tiling is
Even at this timing, G's interference will occur. By subtractor 5301, (X+G)-CX0G)=2X
(12), and the interference from the video is canceled out.

Also, at this time, since the white noise is a random signal, 41-
It just doubles.

FIG. 60 shows a block diagram of a television broadcast polarization transmission apparatus as another embodiment of the present invention. The same code as Brown 1st prisoner indicates the same function.

In FIG. 60, the five-value conversion circuit 114 is omitted from the first version, and the rest of the operation is the same as in FIG. 1.

FIG. 61 shows an embodiment of a conventional receiver for receiving the signal transmitted in the embodiment of FIG. 60. The same symbols as in Fig. 21 indicate the same functions.
125 is omitted, and the rest is the same operation as in FIG. 21.

The embodiment shown in Figures 60 and 61 has the effect of reducing interference from images with a simple circuit configuration.

〔Effect of the invention〕

According to the present invention, the spectrum near the carrier wave frequency of the video signal can be suppressed from the spectrum of a signal such as a digitally encoded audio signal that is modulated in a relationship orthogonal to the amplitude-varied carrier wave. If the modulated carrier detection circuit is carrier regeneration type detection, the carrier frequency selection band of the carrier frequency selection circuit is used, and if the PLL synchronous detection circuit is used, the orthogonal multi-point digital encoded signal is applied to the frequency response band of the PLL. This has the effect of reducing interference from signals such as audio QI signals, and reducing zero-finger changes due to phase fluctuations caused by multi-cross signals. In addition, the video carrier wave has an orthogonal relationship with the video signal, and the same multiplexed signal in adjacent horizontal scanning periods of the video signal can be multiplexed and transmitted as an opposite phase with a phase relationship. However, the envelope detection method also has the effect of reducing interference from multiplexed signals to the MA.

In addition, according to the invention, the video carrier wave has an orthogonal relationship with the video signal, and since adjacent data can be multiplexed as opposite-phase data that has a phase relationship, the video detection method used in the television broadcaster Yumerei is the envelope detection method. Even so, it has the effect of reducing interference from multiplexed signals to video signals.

Further, according to the present invention, it is possible to suppress the spectrum in the vicinity of the carrier wave frequency of the *a signal from the spectrum of a signal such as a digitally encoded audio signal that is orthogonal to the amplitude modulated carrier wave. Therefore, the transverse wave circuit of the amplitude modulated carrier wave is applied to the carrier wave in the case of double detection to the carrier frequency selection band of the carrier frequency selection circuit, and in the case of a PLL synchronous detection circuit to the frequency response band of the PLL. There is a young fruit that can reduce the hue change caused by the phase fluctuation caused by the orthogonal multi-X signal due to interference from signals such as the voice fg signal.

Furthermore, reducing the spectrum near the carrier is −T
Since the audio band of Vif11411 can also be reduced, there is a benefit in that it can also reduce the interference given to the TVf7!1 decoupling A4 circuit of the intercarrier system.

Further, according to the present invention, a carrier wave having a quadrature phase relationship with a carrier wave modulated by a single corner is combined with a signal that is modulo multiplexed by reducing the spectrum near the carrier wave, and a carrier wave that is amplitude modulated. Synchronous detection is performed from the system transmission signal using a signal synchronized with the carrier wave in the multiplexed number 1, and demodulation can be performed using a 5i identification circuit or a digital demodulation circuit, so it is possible to reproduce signals other than the amplitude modulated signal that is different from the amplitude modulation. effective.

Furthermore, the response band of the carrier wave regeneration circuit is
Since the signal can be generated in a suppressed band near the carrier wave in the spectrum of , stable KfJa transmission can be regenerated and orthogonally multiplexed signals can be stably demodulated. Further, according to the present invention, since the signal transmitted in the reverse phase of the Oka-ta 11L (I! signal) can be subtracted and reproduced, interference from the video signal such as video ghost can be reduced.

Further, according to the present invention, the response band of the parallel transmission wave regeneration circuit can be set within the suppressed band near the carrier wave of the spectrum of the orthogonal multiplexed signal Xa, so that the carrier wave can be stably regenerated and the orthogonally multiplexed 1M signal can be stabilized. There is an effect that can be demodulated. In addition, since the signal multiplexed into orthogonal components can be demodulated or inverted-add demodulated for each piece of data, which is the minimum data inversion period, F
M-? P Inverted change for each Vc1 data like E
It has the potential to demodulate multiplexed signals, and it also has the effect of canceling out and removing interference from images with a lot of 14-tangent correlation using low-frequency components.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a delivery machine as a practical example of the present invention, Figure 82 is a spectrum diagram for explaining the present invention, Figure 5 is an explanatory diagram of the operation of the main parts of the present invention, and Figure 4 is a Raw of the present invention 4! Figure 5 is a timing diagram explaining the operation of Figure 4. Figure 6 is a timing diagram explaining the operation of the IL61N. Fig. 8 is a mock diagram of the screen pattern of the transmission signal in the present invention, Fig. 9 is a vector diagram for explaining the present invention, and Fig. 10 is a main circuit of the present invention and its explanation. Waveform diagram, Figure 11 is a block diagram explaining the J & part of the present invention, Figure 12 is a timing diagram explaining the operation of Figure 11, m15 is a screen pattern diagram of the transmission signal of Figure 11, fil! Figure 14 is a 1012 diagram explaining the construction cost part of the present invention, Figure @15 is a timing diagram explaining the operation of Figure @14,! ! 16 is a screen pattern diagram of the transmission signal in FIG. 14, the 17th factor is a block diagram explaining the 41st part of the present invention, the 18th figure is a block diagram explaining the 41st part of the present invention, and the 19th part is a block diagram explaining the 41st part of the present invention. 7a explaining the construction cost part of the present invention
Figure 20 is a diagram 7a explaining the main parts of the present invention, Figure 21 is a diagram 7a of a receiver as an embodiment of the invention, and Figure 22 is a diagram illustrating the construction cost in an embodiment of the invention. 1a and 23- are timing diagrams for explaining the operation of FIG. Timing diagram for,! ! Fig. 26 is a block diagram of another example of the main parts in the embodiment of the present invention, Fig. 27
The figure is a timing diagram for explaining the operation of Figure 26.
Figure 29 is an explanatory diagram of one operation of the main part in the embodiment of the present invention, Figure 29 is an explanatory diagram of another operation of the main part in the embodiment of the invention, and Figure @50 is an explanatory diagram of the operation of the main part in the embodiment of the invention. 31 is a block diagram of the construction cost part of the present invention, Figure 52 is a timing diagram for explaining the 31st part, and Figure 53 is a block diagram of the 4N part of the present invention. Fig. 54 is a timing diagram for explanation of I-53-, Fig. 35
The figure is the 70th figure of the construction cost part of the present invention, and the 56th figure is the 55th figure of the theory.
37 is a block diagram of another 42 part in the embodiment of the present invention, and Figure 58 is a block diagram of a specific example of other main parts in the embodiment of the present invention. Figure 59 is a timing diagram for explaining the operation of Figure 38. Figure 40 is a block diagram of another specific example of other main parts in the embodiment of the present invention. A timing diagram, FIG. 42 is a block diagram of another specific example of other main parts in the embodiment of the present invention, and FIG.
Fig. 52 is a timing diagram for explaining the operation, Fig. 44 is a 10-trick diagram of other specific examples of other main points in the embodiment of the present invention, and Fig. 45 is a transmission diagram as another embodiment of the present invention. Figure 46 is a waveform diagram for explaining the present invention, Figure 47 is a block diagram for explaining the main parts of the present invention,
@Figure 48 is a block diagram explaining the main parts of the present invention,
Figure 49 is a block diagram explaining the main parts of the present invention, Figure 50 is a diagram 1012 explaining the main parts of the invention, and Figure 5
Figure 1 is a block diagram of another embodiment of the present invention, and Figure 52 is a block diagram of the main parts of the present invention.g55
The figure shows a receiving device 1012 as another embodiment of the present invention.
Fig. 54 is a screen pattern diagram of the transmission signal of the present invention, Fig. 55 is a timing diagram explaining the operation when receiving the transmission signal of Fig. 54, and Fig. 56 is a screen pattern diagram of the transmission signal of the present invention. Screen pattern diagram, ii! 57 is a timing diagram explaining the operation when receiving the transmission signal of FIG. 56, and FIG.
59 is a timing diagram explaining the operation when receiving the transmission signal of FIG. 58, and FIG. 60 is another embodiment of the present invention. The block diagram of the transmitter shown in Figure 61 is a block diagram of the transmitter as another embodiment of the present invention. 1012 diagram of the I device. 115...Digital modulation circuit 114...5 constant conversion circuit 115...Processing circuit 2
117...Delay device 2118...Subtractor 2
119...Five value identification circuit 2120...Code identification circuit 2121...Rikku reproducing circuit 2122...Switch 2125...Time axis expansion circuit 2124...Tie-digital reproduction circuit 2125... 211 Friend exchange circuit 2126...Digital hind leg circuit 42 Figure 44 Figure 5 (j) Figure 5 (j) Figure 5 (mark) A Figure Punishment 1'5 Figure 〒14 1405 - 47 people 7 Nomushi 7 or (EO Shakun porridge old Yuen porridge 1○ Figure 42 Figure 2j Figure (I)) Blank 24 Figure 425 Figure (fang) (d) 426 Figure 27 Figure 51 Figure FM's i! JiJro S valley's arrow diagram 〒52 Figure FMrL No.1 solid 7 timing chart diagram no, s! 1 Engineering Drawing Closed Figure 34 PEIL Exit Route Timing Signaya F Diagram I = 1 3G10 4'55 Figure Ta 4 Min 7 Chart! River 51 Ii 156 Diagram ￥553 Diagram <, f N Chu Shun Zuko 41 Diagram Sanskrit 44 Diagram (cL) 61〇-〒43 Diagram Door 46 Diagram! Illustration 5 of the imitation of the mountain face Ha Tarn of the 54th figure of the spear 3

Claims (1)

[Claims] 1. In a transmission method in which a carrier wave is modulated in vestigial sideband amplitude with a video signal and transmitted, a digitally encoded multiplexed signal different from the video signal is transmitted as a low-frequency component of the multiplexed signal. A multilevel digital signal is generated that suppresses the low-frequency components of the multiplexed signal, and the multiplexed signal subjected to the suppression processing is repeated in units of horizontal scanning periods of the video signal, and adjacent Amplitude modulates an orthogonal carrier wave that has a quadrature phase relationship with the video carrier wave using a multiplexed signal that undergoes correlation processing to invert to an antiphase relationship at the same timing in the horizontal scanning period, and synthesizes it with the residual sideband amplitude modulated wave. An orthogonal multiplex transmission system that is characterized by transmitting 2. The rising edge of the binary signal data digitally encoded as the multilevel digital signal is a pulse with a high level relative to the intermediate level, the falling edge is a pulse with a low level relative to the intermediate level, and other periods 2. The orthogonal multiplex transmission system according to claim 1, wherein: is a ternary digital signal having an intermediate level. 5. The orthogonal multiplex transmission system according to claim 1, wherein an FM code is used as the digital modulation. 4. The orthogonal multiplex transmission system according to claim 1, wherein a PE code is used as the digital modulation. 5. A signal generation device having an amplitude modulation circuit that amplitude modulates a carrier wave with a video signal with a residual sideband, a phase shifter that obtains a quadrature-phase carrier wave from a carrier wave generation circuit that transmits the video signal, and the residual sideband a digital modulation circuit that digitally modulates a digitally encoded multiplex signal different from the video signal, which is amplitude modulated, so that the low frequency components are suppressed; and a digital modulation circuit that digitally modulates the output of the digital modulation circuit so that the low frequency components are suppressed. A multi-value conversion circuit that converts into a multi-value digital signal, and a correlation process that repeats the output of the multi-value conversion circuit in units of horizontal scanning periods of a video signal and inverts it to an inverted phase relationship at the same timing in adjacent horizontal scanning periods. A modulation circuit that amplitude modulates the output of the phase shifter using the output of the modulation circuit, and a synthesis circuit that synthesizes the output of the modulation circuit and the residual sideband amplitude modulated wave. A signal generator used in an orthogonal multiplex transmission system transmitter. 6. In a signal generation device having an amplitude modulation circuit that amplitude modulates a carrier wave with a video signal with a vestigial sideband, a phase shifter that obtains a quadrature-phase carrier wave from a carrier wave generation circuit that transmits the video signal; a multi-value conversion circuit that converts a digitally encoded multiplex signal different from the video signal that is amplitude-band modulated into a multi-value digital signal in which low-frequency components are suppressed; a digital modulation circuit that performs digital modulation so as to suppress A processing circuit, a modulation circuit that amplitude modulates the output of the phase shifter using the output, and a synthesis circuit that synthesizes the output of the modulation circuit and the residual sideband amplitude modulated wave. A signal generator used in an orthogonal multiplex transmission system transmitter. 7. The signal generating device used in a transmitting device using an orthogonal multiplex transmission system according to claim 5 or 6, wherein the digital modulation circuit is an FM modulation circuit. 8. The signal generating device used in a transmitting device using an orthogonal multiplex transmission system according to claim 5 or 6, wherein the digital modulation circuit is a PE modulation circuit. 9. The multi-value conversion circuit includes a delay circuit that delays an input signal of the multi-value conversion circuit, a first inversion circuit that inverts the multiplexed signal, and a second inversion circuit that inverts the output of the delay circuit. , a first AND circuit that ANDs the multiplexed signal and the output of the second inversion circuit, and a second AND circuit that ANDs the output of the delay circuit and the output of the first inversion circuit. Consisting of an AND circuit, a third inversion circuit that inverts the output of the second AND circuit, and an adder circuit that adds the output of the first AND circuit and the output of the third inversion circuit. 7. A signal generator for use in an orthogonal multiplex transmission system transmitter according to claim 5 or 6. 10. A signal generation device having an amplitude modulation circuit that amplitude modulates a carrier wave with a video signal with a residual sideband, a phase shifter that obtains a quadrature-phase carrier wave from a carrier wave generation circuit that transmits the video signal, and the residual sideband a digital modulation circuit that digitally modulates a digitally coded multiplex signal different from the video signal that is amplitude modulated in such a way that low frequency components are suppressed; A multi-value conversion circuit that converts into a value digital signal, and a correlation process that repeats the output of the multi-value conversion circuit in units of horizontal scanning periods of the video signal and inverts it to an inverse phase relationship at the same timing in adjacent horizontal scanning periods. An orthogonal multiplex transmission system comprising a processing circuit, a modulation circuit that amplitude modulates the output of the phase shifter using the output, and a synthesis circuit that combines the output of the modulation circuit and the residual sideband amplitude modulated wave. A receiving device that receives an orthogonal multiplex transmission signal transmitted from a signal generating device used in a transmitting device includes a selection circuit that selects the output band of the modulation circuit from the received orthogonal multiplex transmission signal, and a selection circuit that selects the output band of the modulation circuit from the received orthogonal multiplex transmission signal, and a carrier regeneration circuit that regenerates a carrier wave; a synchronous detection circuit that synchronously detects the output of the selection circuit with the regenerated carrier wave from the carrier regeneration circuit; and at least one delay that delays the detected output from the synchronous detection circuit for a certain period of time. a circuit, an arithmetic circuit that performs arithmetic processing such as subtraction on the output of the delay circuit, a code identification circuit that identifies the sign of the output of the arithmetic circuit, and an extraction that extracts a signal of a required period from the output of the code identification circuit. a binary conversion circuit that performs inverse conversion of the multi-value conversion circuit on the output of the extraction circuit, and a digital demodulation circuit that performs inverse conversion of the digital modulation circuit on the output of the binary conversion circuit. A signal reproducing device used in a receiving device characterized by: 11. A signal generator having an amplitude modulation circuit that amplitude modulates a carrier wave with a video signal with a residual sideband, a phase shifter that obtains a quadrature-phase carrier wave from a carrier wave generation circuit that transmits the video signal, and the residual sideband a multi-value conversion circuit that converts a digitally encoded multiplex signal different from the video signal that is amplitude-band modulated into a multi-value digital signal in which low-frequency components are suppressed; a digital modulation circuit that performs digital modulation so as to suppress An orthogonal multiplex transmission system comprising a processing circuit, a modulation circuit that amplitude modulates the output of the phase shifter using the output, and a synthesis circuit that combines the output of the modulation circuit and the residual sideband amplitude modulated wave. A receiving device that receives an orthogonal multiplex transmission signal transmitted from a signal generating device used in a transmitting device includes a selection circuit that selects the output band of the modulation circuit from the received orthogonal multiplex transmission signal, and a selection circuit that selects the output band of the modulation circuit from the received orthogonal multiplex transmission signal, and a carrier regeneration circuit that regenerates a carrier wave; a synchronous detection circuit that synchronously detects the output of the selection circuit with the regenerated carrier wave from the carrier regeneration circuit; and at least one delay that delays the detected output from the synchronous detection circuit for a certain period of time. a circuit, an arithmetic circuit that performs arithmetic processing such as subtraction on the output of the delay circuit, a code identification circuit that identifies the sign of the output of the arithmetic circuit, and an extraction that extracts a signal of a required period from the output of the code identification circuit. a digital demodulation circuit that performs inverse conversion of the digital modulation circuit on the output of the extraction circuit; and a binary conversion circuit that performs inverse conversion of the multi-value conversion circuit on the output of the digital gain circuit. A signal reproducing device used in a receiving device characterized by: 12. A signal generation device having an amplitude modulation circuit that amplitude modulates a carrier wave with a video signal with a residual sideband, a phase shifter that obtains a carrier wave of quadrature phase from a carrier wave generation circuit that transmits the video signal, and the residual sideband a multi-value conversion circuit that converts a digitally encoded multiplex signal different from the video signal that is amplitude-band modulated into a multi-value digital signal with suppressed low-frequency components; and a multi-value conversion circuit that PE encodes the output of the multi-value conversion circuit. a processing circuit that performs correlation processing that repeats the output of the PE encoding circuit in units of horizontal scanning periods of a video signal and inverts it to an inverted phase relationship at the same timing in adjacent horizontal scanning periods; A signal used in a transmitter of an orthogonal multiplex transmission system, which is provided with a modulation circuit that amplitude modulates the output of the phase shifter and a synthesis circuit that synthesizes the output of this modulation circuit and the residual sideband amplitude modulated wave. In a receiving device that receives an orthogonal multiplex transmission signal transmitted from a generator, a selection circuit that selects an output band of the modulation circuit from the received orthogonal multiplex transmission signal, and a carrier wave that reproduces the carrier wave from the output of the selection circuit. a regeneration circuit; a synchronous detection circuit that synchronously detects the output of the selection circuit with a regenerated carrier wave from the carrier regeneration circuit;
a first delay circuit that delays data that has become a PE code in the encoding circuit by one data length; a first arithmetic circuit that performs arithmetic processing such as subtraction on the output of the first delay circuit; a second delay circuit that delays the output of the arithmetic circuit for a certain period of time; a second arithmetic circuit that performs arithmetic processing such as subtraction on the output of the second delay circuit; and a sign of the output of the second arithmetic circuit. A code identification circuit for identifying the code identification circuit, an extraction circuit for extracting a signal of a necessary period from the output of the code identification circuit, and a binary conversion circuit for performing inverse conversion of the multi-value conversion circuit on the output of the extraction circuit. A signal reproducing device for use in a receiving device, characterized in that: