JPH0215352A - Dummy fault substitution diagnosis system - Google Patents

Abstract

PURPOSE:To diagnose a channel control device under the same condition as that of real data transfer by providing a diagnosis device between a channel control device and an I/O control device. CONSTITUTION:The diagnosis device 17 is provided to a bus 22 connecting the channel control device 18 to the I/O control device 21. The device 17 allows transfer data 23 outputted from the device 21 to practically generate a fault at the time of diagnosis and outputs transfer data 24 to which a fault is added to the device 18. The device 17 diagnosis the device 18 by monitoring a response signal 25 outputted from the device 18 in accordance with output operation. Thereby, the device 18 can be diagnosed under the same condition as that of practical data transfer.

Description

[Detailed Description of the Invention] [Summary] Regarding a diagnostic method for a channel control device in a data processing system that transfers data between a device and an input/output control device via a channel control device, this paper describes In a data processing system that transfers data between a device and an input/output control device via a channel control device, the above-mentioned channel control device and It is provided between the buses connecting the manipulating saw control device, and is connected to the input/output side at the time of diagnosis. f
The channel control is performed by taking the transfer data output from the f1l device, adding one pseudo failure to the data, outputting it to the channel control device, and monitoring the response signal from the channel control device in response to the output operation. The apparatus is configured to include a diagnostic device for diagnosing the device.

[Industrial application field]

The present invention relates to a method for diagnosing a channel control device in a data processing system that transfers data between a storage device and an input/output control device via a channel control device.

[Conventional technology]

-i system configuration when data is transferred between input/output devices such as external auxiliary storage devices, printers, terminal devices, or trunk circuits and main storage devices in data processing systems such as computer systems and electronic exchange systems. As a possible example, the one shown in FIG. 4 can be considered.

In the figure, a central control unit (CC1 and below) 2 and a main memory (MM, below) 3 are connected to a channel control unit (CHC, below) 1 via a memory bus 5. On the other hand, is there a plurality of input/output sides (n units) to which each input/output device (not shown) is connected? llI device 4 (#1) ~ 4
(#n) is connected to CHC] via the common bus 6.

Data transfer between MM3 and l0C4 is performed under the control of CHC1. That is, first, CC2
is C)-f Transfer start address on MMJ to C1, number of bytes transferred from there, and address of l0C4 (#1 to #
n), etc. Based on this, CHC1 transmits each of the above data to the corresponding l0C4 and activates it. After this, CHC1 occupies the memory bus 5 based on the transfer request from l0C4, and l0C4
MM3 is accessed according to the transfer addresses input sequentially from It is necessary to diagnose the operation of each device. Among these diagnostic methods, there is one shown in FIG. 5 as a conventional example particularly for diagnosing CHCl.

In the figure, during normal data transfer, the control section 9 turns on the buffer 14 and the AND gate 11,
Buffer 16 and AND gate 12 are turned off. As a result, the data output from l0C4 to the common bus 6 is transferred to the buffer 13, the AND gate 11, and the OR gate 10.
is input to the data section 8 via the control section 9.
is output to the memory bus 5 under the control of MM3 (Fig. 4).
will be forwarded to. Conversely, data input from MM3 to data section 8 via memory bus 5 is output from buffer 14 to common bus 6 and transferred to 10C4.

On the other hand, when diagnosing CHCl, the control section 9 turns on the buffer 16 and the AND gate 12, and turns off the buffer 14 and the AND gate 11, contrary to the above.

As a result, the diagnostic device 7 configured in CHCl can output test data, etc. from the common bus 6' to the data section 8 via the buffer 15, AND gate 12, and OR gate 10, and conversely, can output test data, etc. from the data section 8. is buffer 1
6 to the diagnostic device 7 via the common bus 6'.

As described above, at the time of diagnosis, the common bus 6 to which the l0C4 is connected is disconnected from the CHC1 and switched to the common bus 56, thereby connecting the CHC1 to the diagnostic device 7 for diagnosis.

[Problem to be solved by the invention]

However, in the case of the conventional example shown in FIG. The common bus 6 used during data transfer is also disconnected. Therefore, in the past, it has not been possible to perform diagnosis in accordance with actual data transfer, and there has been a problem in that diagnosis including the common bus 6 and the like cannot be performed.

An object of the present invention is to realize diagnosis using data etc. during actual data transfer.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention. The channel control device 18 is connected to a storage device 20 (for example, a main storage device) via a bus 26 and, if necessary, to a central control device 19.
is connected to the input/output side t7 via another bus 22.
1 device (for example, a disk-based device) 21 is connected. The channel control device 18 controls data transfer between the storage device 20 and the input/output control device 21. The data transfer method in this case is, for example, a DMA (direct memory access) transfer method.

Further, a diagnostic device 17 is provided between the lotus 22 connecting the channel control device 18 and the input/output control device 21. The same device 1
Is 7 on the input/output side during diagnosis? The transfer data 23 output from the 1TL device 21 to the bus 22 is taken in, a false fault is added to the data, and the data is output to the channel control device 18 as transfer data 24 with the fault added. Then, by monitoring the response signal 25 from the channel control device 18 in response to the output operation, the channel control device 1
Perform the diagnosis in step 8. Note that the diagnostic device 17 may be built into the channel control device 18.

[For production]

In the above means, first, during normal transfer, the transfer data transferred between the channel control device 18 and the input/output control device 21 passes through the diagnostic device 17 as is.

On the other hand, during diagnosis, as described above, a fault is caused in the transfer data 23 actually output from the input/output control device 21, and the fault is output to the channel device 18 as transfer data 24 with the fault added.

Therefore, it is possible to diagnose the channel control device J8 under the same conditions as during actual data transfer.

Here, if the channel control device 18 is able to detect a fault in the transfer data 24 to which the fault has been added, the response signal 25 that should normally be output is no longer output, so the diagnostic device 17, for example, outputs the response signal 25 for a certain period of time. If it is not detected within the j period, it can be recognized that the channel control device 18 has successfully detected the pseudo fault j. In such a case, the diagnostic device 17 interrupts the data transfer by outputting an interrupt request signal to the channel control device 18, for example, and returns control to the central control device I9. It is possible to read out 17 diagnostic states.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

First, the overall configuration of the data processing system, which is the premise of this embodiment, is the same as that shown in FIG. 4, which has already been explained, so its explanation will be omitted.

Next, the configuration of the channel control device (CHC1 and below) 1 in FIG. 4 according to this embodiment is shown in FIG.

In the figure, during normal data transfer, the bus switching unit 29 inserted between the common buses 6 is connected to the diagnostic device (P
ro, the same applies hereafter) 26, and the main memory (
MM (same below) 3 and input/output device (IOC5 and below)
4 (see Figure 4) via the memory bus 5 and common bus 6.
Data transfer is performed using the transfer method. At this time, the memory bus 5 and the common bus 6 are connected to each other by the data section 27 controlled by the control section 28.

On the other hand, the PI 026 includes a control section 30, a data buffer register (DBR, hereinafter the same) 31, a device status register (DSR, hereinafter the same) 31, buffers 33 and 34, and the like.

At the time of diagnosis, the transfer data 35 outputted from the l0C4 to the common bus 6 is inputted from the bus switching section 29 to the DBR 31 via the buffer 34. After the contents are controlled by the control section 30 as described later, the buffer 33, which is also controlled by the control section 30, is again outputted to the common bus 6 as faulty transfer data 36 via the bus switching section 29. , is sent to the data section 27.

On the other hand, a response signal 37 output from the data section 27 to the common bus 6 is set in the DBR 31 from the bus switching section 29 via the buffer 34.

Next, the contents of the DSR 32 are controlled by the control section 30, and as described later, the contents of the DSR 32 are controlled by the buffer 33 and the bus switching section 29.
, the common bus 6, the data 27 and the memory bus 5 to the CC 2 (see FIG. 4).

In the above configuration, the bus switching section 29 is connected to the control section 2.
8 and 30.

The operation of the above embodiment will be explained using the operation flowchart shown in FIG. The invention according to this embodiment is an invention relating to a diagnostic operation when data is transferred from one of the l0C4s in FIG. 4 to the MM3. In the following explanation, the explanation will be centered on FIG. 2, and CC2, M M3,
Regarding l0C4, refer to FIG. 4.

First, a diagnostic command is sent from CC2 to CHC1 via memory bus 5 (see FIG. 3 81, below)
.

After this diagnostic command is received by the data section 27, it is recognized by the control section 28.
controls the control unit 30 in the PIO 26, thereby bringing the P I 026 into service, that is, into an operational state (S2).

After the above operation, CC2 sends an IO start command to cFrct in the same way as a normal data transfer operation, and causes it to be input to the data section 27 (S3).

Next, since the control unit 28 recognizes this command, the control unit 28 accelerates the MM3 from the data unit 27 via the memory bus 5, and in this 4. 3 data related to the data transfer being performed, ie, the transfer start address, the number of bytes transferred from the transfer start address, and the start command, will be sold. Then, these data are sent from the common bus 6 to the bus switching section 29 and further to the l0C4 via the common bus 6 (S4). Note that the startup command at this time indicates an instruction to transfer data from 10C4 to MM3.

According to the v1 work described above, 10C4 is activated and sends a transfer request signal indicating that it wants to start DMA transfer to CHCl (S5).

However, in this case, the control unit 28 controls the lotus switching unit 29 in advance to change the common bus 6 on the l0C4 side to P4O1.
Connected to 0. Therefore, the transfer request signal outputted to the CHC1 does not go to the bus switching unit 2.
9 to the PI026, and the transfer is accepted by the control unit 30 (S6).

After that, from the input/output device (10) not shown in particular,
Transfer data 35 output to common bus 6 via C4
is transferred from the bus switching unit 29 to the DBR 3 via the buffer 34.
1 (S7).

In this way, each time the transfer data 35 is loaded into the DBR 31, the control unit 30 intentionally inverts, for example, only one bit of the transfer data 25 of, for example, 16 bits, sets a pseudo fault, and detects the fault. Transfer data 36
(S8).

Subsequently, the control unit 30 sends a transfer request to the control unit 28 (S9).

When the transfer request is accepted, the buffer 33 and the bus switching unit 29 are controlled, and the faulty transfer data 36 set in the DBR 31 is transferred to the data via the buffer 33, the bus switching unit 29, and the common bus 6. 27 (S10).

The control unit 28 checks the parity bit and returns a response signal 37 if the transferred data is correct, but if the faulty transferred data 36 is received, a data error is detected. Therefore, the response signal 37 is not returned (Sll).

On the other hand, the controller 30 determines whether the response signal 37 is returned within a certain period of time after outputting the faulty transfer data 36 from the DBR 31, that is, the common bus timeout has occurred (S12 ).

Then, even though the response signal 37 is not returned and a common path timeout occurs as described above, the control section 30 determines that the control section 28 has correctly detected the above fault, and the control section 30 sends information on the occurrence of the fault to the DSR 32. At the same time, an interrupt request is outputted to the control section 28 through means not shown in order to interrupt the DMA transfer (S13).

When the control unit 28 accepts this interrupt request,
The current DMA transfer is interrupted and the D in PI026 is
The information set in the SR32 is read from the buffer 33 to the data section 27 via the bus switching section 29 and the common bus 6, and at the same time, the 10 addresses of pr026 are also sold (S14).

After that, the control unit 28 sends an interwoven source signal from the data unit 27 to the CC 2 via the memory bus 5 to notify that an interrupt has occurred (S15). The contents of the DSR 32 and the 10 addresses of P2026 read into the data section 27 are stored, for example, in the system area of the MM3.

With the above operation, CC2 is controlled by MM3 under software control.
By detecting each of the above information stored in the system area of , CHCl determines whether or not the original image failure due to the parity bit inversion has been detected, and ends the diagnostic operation (816.517).

As shown in the above embodiment, l0C4 outputs the transfer data 35 in exactly the same way as the normal data transfer operation, and PI02
6 adds a fault to it and transfers data with fault 2
6 and is output to the data section 27. Therefore, it is possible to perform diagnosis under the same conditions as during actual data transfer. Further, when the response signal 37 is not returned within a certain period of time, the PI 026 can interrupt the DMA transfer by interrupting the control unit 28.
This makes it easy to output the diagnostic state to the CC2.

〔Effect of the invention〕

According to the present invention, it is possible to diagnose a channel control device under the same conditions as during actual data transfer.

Here, if the channel control device is able to detect a fault in the transferred data to which the above fault has been added, the response signal that should normally be output can be prevented from being output, so that the diagnostic device can detect the response signal within a certain period of time. If not, it can be recognized that the channel control device has successfully detected the pseudo failure.

In such a case, the diagnostic device interrupts the data transfer by, for example, outputting an interrupt request signal to the channel control device, and returns control to the central control device, thereby changing the diagnostic state of the diagnostic device. can be easily read out.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the present invention; Figure 2 is a configuration diagram of an embodiment of the present invention; Figure 3 is an operational flowchart of the embodiment of the present invention; Figure 4 is the entire data processing system. The configuration diagram, FIG. 5, is a configuration diagram of a conventional example. DESCRIPTION OF SYMBOLS 17... Diagnosis device, 18... Channel control device, 20... Storage device, 21... Input/output control device, - Nomas, - Transfer data, - Transfer data added with a fault, response signal.

Claims (1)

[Scope of Claims] A data processing system that transfers data between a storage device (20) and an input/output control device (21) via a channel control device (18), comprising: Input/output control device (
21) is provided between the bus (22) that connects the input/output control device (21), and takes in the transfer data (23) output from the input/output control device (21) at the time of diagnosis, adds a pseudo fault to the data, and connects the channel. It is characterized by having a diagnostic device that diagnoses the channel control device (18) by outputting it to the control device (18) and monitoring a response signal (25) from the channel control device (18) in response to the output operation. An alternative diagnostic method for pseudo failures.