JPH02151775A - Automatic trigger apparatus - Google Patents

Abstract

PURPOSE:To obtain a correct trigger signal always at the same point of an analog input signal even if a level of the analog input signal fluctuates by a method wherein a trigger level is set based on a peak value of a digital signal and converted into an analog signal, and this is compared with the analog input signal. CONSTITUTION:With AND output data of increase flag output data of a decrease/increase determination circuit and decrease flag output data latched by FF15 changed from decrease to increase from an AND gate 14, it is output to FF11 as a minimal flag. A digital signal Dn-1 latched by FF group 8 at this time is latched with FF11 as minimum. On the other hand, when AND output data of decrease flag output data of the increase/decrease determination circuit and increase output data latched by FF12 is changed from increase to decrease from an AND gate 14, it is output to FF10 as a maximal flag. A signal Dn-1 latched by the FF group 8 at this time is latched with FF10 as maximum.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an improvement in an automatic trigger device that can always obtain a trigger signal at the same point in time of an analog input signal, regardless of level fluctuations in the analog input signal. .

<Prior Art> When setting a measurement start point with a waveform measuring device such as an oscilloscope, it is necessary to obtain a trigonometric signal synchronized with an analog input signal. Therefore, some devices are configured to set a desired trigger level using, for example, a potentiometer, and generate a trigger pulse when the analog input signal exceeds this trigger level.

However, in such a circuit, a trigger signal is not generated when the amplitude of the analog input signal becomes less than a set trigger level, which is not preferable when a trigger signal is always required.

Therefore, in order to solve such drawbacks, the trigger level is electronically controlled according to the amplitude of the analog input signal, as disclosed in Japanese Patent Publication No. 60-18013, and the amplitude of the analog input signal is controlled electronically. A circuit has been proposed in which a tri-force signal can always be obtained regardless of the condition.

<Problems to be Solved by the Invention> However, the circuit disclosed in this publication is basically composed of an analog circuit, and is subject to the effects of voltage drops in diodes, delays in RC circuits, etc. from,
It is difficult to obtain a tri-force signal with an analog input signal below a certain value or near a peak value.

In order to solve these disadvantages, various complicated circuits are required, which is disadvantageous in simplifying and downsizing the entire circuit.

The present invention has focused on such points, and its purpose is to provide the same level of control even when the level of the analog input signal fluctuates.
An object of the present invention is to provide an automatic trigger device that can always obtain an accurate trigger signal at the same point in time of an analog input signal.

Means for Solving the Problems> The automatic trigger device of the present invention includes an A/I converter that converts an analog input signal into a digital signal, and a peak value that is calculated from the digital signal output from the A/D converter. A peak detection circuit for detecting a peak, a trigger level setting circuit for setting a trigger level based on the peak value detected by this peak detection circuit, and a D for converting trigger level data set by this trigger level setting circuit into an analog signal. The present invention is characterized in that it includes: a /A converter; and a trigger pulse generation circuit that compares the trigger level signal output from the D/A converter with the analog input signal and generates a trigger pulse.

Effects> Since the automatic trigger device of the present invention basically performs digital processing, various inconveniences caused by conventional analog circuit configurations can be solved.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, 1 is an A/D converter that converts an analog input signal Ain into a digital signal, and the digital signal output from this A/D converter 1 is sent to a peak detection circuit 2 that detects the peak value. It has been entered. 3 is a trigger level setting circuit that sets a trigger level based on the peak data PD detected by the peak detection circuit 2; A D/A converter 4 converts trigger level data TD set by the trigger level setting circuit 3 into an analog signal AT, and its output signal AT is input to the trigger pulse generating circuit 5. The trigger pulse generation time 1p65 compares the trigger level signal AT output from the D/A converter 4 with the analog input signal A jrL and generates a trigger pulse 'rP.
occurs. 6 is a timing control circuit that controls the operation timing of each part, outputs a control signal S1 that controls the conversion timing to the A/D converter 1, and outputs a control signal S1 to the peak detection circuit 2 for operating the circuit. Output S2,
A timing signal S3 for reading the peak data PD output from the peak detection circuit 2 is output to the trigger level setting circuit 3.

The operation of the peak detection circuit 2, which is the main part of the device configured as described above, will be explained.

In the present invention, the point at which the digital signal output from the A/D converter 1 changes from increasing to decreasing is defined as a local maximum value, and the point at which the digital signal outputted from the A/D converter 1 changes from decreasing to increasing is defined as a local minimum value.

Comparing the current digital signal D1 and the digital signal Dπ-1 one sample before, DTL>DTL-1→Qu=1 (increase) Dvr<Du-
+→Qu=O (decrease) Du:DTL-1″Qu=Qu-+ (1) where Ql is a flag indicating increase or decrease.

Then, compare Ql and Ql-1, QTL −+ = 1, Qu =O...I)it
-1-+Local maximum value Qπ-+ =O, Qπ=1...Dπ-
1→Minimum value...(2).

However, as shown in Figure 2, the actual analog input signal is rich in noise such as analog noise superimposed on the analog input signal itself and quantization noise due to digitization. Extreme values that should not be detected may be detected as local maximum values or local minimum values. That is, in FIG. 2, when comparing the second data D2 and the third data D3, D 2 < 1) 3
If we compare the third data D3 and the fourth data D4, >D4, so the third data D3
is determined to be the maximum value, and furthermore, the fourth data D4 and 5
When the fourth data D5 is compared, D4<D, so the fourth data Dd is determined to be the minimum value. However, the third data D:I is not the true maximum value that should be detected, and the fourth data D4 is not the true minimum value that should be detected.

This kind of inconvenience occurs because if the level difference between the current data and the data one sample ago does not exceed a certain threshold T, it is determined that the current data has not changed and the next data is compared. It can be improved. That is, 0π>Dπ-1zu→Qul (increase) D1→DTL+1. Dπ-1→DTL DTL<Dπ-, -T→Q1=O (decrease) D1″D T
L +I + DTL -1″D1D 1-, -T≦
01 ≦0 π −1+T→Q 7L=oT1−
.

Dπ→DTL + j + Dπ-1→D1-1...
(3).

The case where FIG. 2 is processed based on this equation (3) will be explained. Since the difference between the first data D and the second data D2 is within the threshold T, the difference between the first data D1 and the third data D
Compare 3. Similarly, since the difference between the third data D3 and the fourth data D4 is within the threshold -], the third data D
Compare the 3rd and 5th data D5, and the 5th data D5
Since the difference between the data D and the sixth data D6 is within the threshold value -T, the fifth data D and the seventh data D7 are compared.

As a result, the fifth data D5 is determined to be the maximum value. Note that such a threshold value 'r is, for example, A
When using an 8-bit output as the /D converter 1, the lower two bits may be set.

FIG. 3 is a block diagram showing a specific example of the beak detection circuit 2 that operates in this manner. Output data D of the A/D converter 1 is latched into the first D-type flip-flop group 7 as current data D1 in accordance with a clock signal φ synchronized with the A/D conversion operation.

The current data Dπ latched by the first D-type flip-flop group 7 is input to the second D-type flip-flop group 8 which latches the data Dπ-1 of one sample before, and one of the increase/decrease discrimination circuits 9 is input. being input to the input terminal. The pig Du-1 of the previous sample latched by the second D-type flip-flop group 8 is input to the other input terminal of the increase/decrease discrimination circuit 9, and the D-type flip-flop 10 which latches the maximum value data and the minimum It is input to a D-type flip-flop 11 that latches value data. The increase flag output data of the increase/decrease discrimination circuit 9 is input to the D-type flip-flop 12, as well as to one input terminal of the OR gate 13 and one input terminal of the AND gate 14, and the decrease flag output data is input to the D-type flip-flop 12. 15, the other input terminal of the OR gate 13, and one input terminal of the AND gate 16. The output data of the D-type flip-flop 12 is input to the other input terminal of the AND gate 16, and the output data of the D-type flip-flop 15 is input to the other input terminal of the AND gate 14. The output data of the OR gate 13 is input to the clock terminal of the second D-type flip-flop group 8, and the output data of the AND gate 14 is input to the clock terminal of the D-type flip-flop 11 and one input terminal of the OR gate 17. The output data of the AND gate 16 is input to the tally terminal of the D-type flip-flop 10 and the other input terminal of the OR gate 17. input to the terminal.

In such a configuration, when the AND gate 14 outputs the increase flag output data of the increase/decrease determination circuit 3 and the decrease flag output data latched in the D-type flip-flop 15, the minimum flag changes from decrease to increase. The digital signal Dπ-1 is output to the D-type flip-flop 11 as a minimum value and is latched in the second D-type flip-flop group 8 at that time. On the other hand, and gate 1
6, the logical product output data of the decrease flag output data of the increase/decrease discrimination circuit 3 and the increase flag output data latched in the D-type flip-flop 12 changes from increase to decrease, and is output to the D-type flip-flop 10 as a maximum flag. At that point, the second D-type flip-flop group 8
The digital signal D1-1 latched in the D-type flip-flop 10 is latched as a maximum value.

Note that the digital signal Dπ-1 latched in the second D-type flip-flop group 8 is updated only when an increase or decrease change occurs, and the increase flag output data and decrease flag output data are the local maximum value and the local minimum value. Updated only if a value is found.

In the above embodiment, when detecting a peak value, a threshold value 'r is provided in order to remove the influence of noise having a sufficiently faster cycle than the repetition cycle of the analog input signal. It is sufficient to change the trigger level according to fluctuations in the amplitude or DC level, which have a sufficiently slow period compared to the repetition period of the signal, and to always apply a stable trigger force at the same point in time of the analog input signal. In order to remove the influence of noise, instead of providing a threshold value T, the update period 'rR of the trigger level of the analog input signal is further divided into sub-intervals t, as shown in Figure 4, and each of these sub-intervals The average value in the update period of the peak value at tj may be used. Specifically, the peak detection circuit 2 may be used in the trigger level setting circuit 3 in FIG.
N pieces of output data are sampled at an appropriate interval 1 (
A new trigger level may be calculated and set using the average of these N pieces of sampling data as the peak value of section T'R.

<Effects of the Invention> As explained above, according to the present invention, even when the level of an analog input signal fluctuates, with a relatively simple configuration,
It is possible to realize an automatic trigger device that can always obtain an accurate trigger signal at the same point in time of an analog input signal, and it has a great practical effect as an automatic trigger circuit for various waveform measuring devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing a specific example of the peak detection circuit in FIG. FIG. 4 is an explanatory diagram of the operation of another embodiment of the present invention. 1... A/D converter, 2... Peak detection circuit, 3.
...Trigger level setting circuit, 4...D/A converter, 5
...Figure 1 Figure 2

Claims (1)

[Claims] An A/D converter that converts an analog input signal into a digital signal, a peak detection circuit that detects a peak value from a digital signal output from the A/D converter, and the peak detection circuit. a trigger level setting circuit that sets a trigger level based on the detected peak value; a D/A converter that converts the trigger level data set by this trigger level setting circuit into an analog signal; and this D/A converter. An automatic trigger device comprising: a trigger pulse generation circuit that generates a trigger pulse by comparing a trigger level signal output from the analog input signal with the analog input signal.