JPH02149108A - Gate voltage control circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by decreasing the drain current of a FET by detecting a high frequency signal inputted to the FET, and controlling a voltage to be applied on the gate of the FET based on a detecting signal by a gate voltage controller. CONSTITUTION:A gate voltage control circuit is constituted in such a way that part of the high frequency signal is taken out by connecting a directional coupler 7 to the gate of the FET 1, and a detector 8 and the gate voltage controller 9 are connected to the output line of the high frequency signal, and the output of the gate voltage controller 9 is outputted to the gate of the FET 1. Therefore, the power level of the high frequency signal can be monitored by detecting part of the high frequency signal inputted to a high frequency signal input port 2 by the detector 8. And by controlling a detected voltage at the gate voltage controller 9, the drain current to be applied from a drain bias port 6 can be controlled. In such a way, it is possible to reduce the power consumption by decreasing or decreasing to zero the drain current of the FET.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a gate voltage control circuit for controlling the drain current of a field effect transistor (FET), and particularly to a gate voltage control circuit that reduces power consumption during non-operation. Regarding circuits.

[Conventional technology]

Conventionally, a circuit using a fixed bias has been used as a gate voltage control circuit using an FET.

FIG. 2 shows an example, in which a high frequency signal input port 2 is connected to the gate of the FETI via a DC cut capacitor 3, and a high frequency signal output port 4 is connected to the drain via a DC cut capacitor 5. A drain bias port 6 is also connected. As a gate voltage control circuit, a gate voltage bias port 11 is connected to the gate of the FETI via a variable resistor 10, and the gate bias voltage applied to the bias port 11 is adjusted by the variable resistor 10 to control the FETI. Applied to the gate.

[Problem to be solved by the invention]

In the conventional gate voltage control circuit described above, the variable resistor 1
Since the gate bias voltage is uniquely set to 0, a certain constant drain current always flows even when no high frequency signal is input to the FETI. Therefore, when the FET 1 constitutes a high-power amplifier or the like, there is a problem that a large amount of drain current flows even when the FET 1 is not in operation, consuming a large amount of power.

In addition, when configuring an amplifier in multiple stages, consideration must be given to lower power consumption and the drive level of each stage.
In order to improve the variation in cross-modulation distortion characteristics of amplifiers, various types of FETs and hybrid ICs are required, and the high-frequency circuit section,
Another problem is that the circuit configuration of the DC bias circuit section becomes complicated.

SUMMARY OF THE INVENTION In order to solve these problems, it is an object of the present invention to provide a gate voltage control circuit that makes it possible to reduce the power consumption of FETs.

[Means to solve the problem]

The gate voltage control circuit of the present invention includes a directional coupler that takes out a part of the high frequency signal input to the FET, a detector that detects the high frequency signal taken out by the directional coupler, and a detector that detects the high frequency signal that is taken out by the directional coupler. and a gate voltage controller that controls the voltage applied to the gate of the FET based on the signal.

[Effect]

In the above-described configuration, when the FET is not in operation and no high-frequency signal is input, the gate voltage applied from the gate voltage controller to the FET is lower than the pinch-off voltage, and the drain current of the FET is reduced to zero, thereby reducing power consumption.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, a high frequency signal input port 2 is connected to the gate of the FETI via a DC cut capacitor 3, a high frequency signal output port 4 is connected to the drain via a DC cut capacitor 5, and a drain bias port 6 is connected to the gate of the FETI. Connected. Then, as a gate voltage control circuit, the FET
A directional coupler 7 is connected to the gate of I to extract a part of the input high frequency signal, a detector 8 and a gate voltage controller 9 are connected to the high frequency signal extraction line,
According to this configuration, which outputs the output of the gate voltage controller 9 to the gate of the FET 1, a part of the high frequency signal input to the high frequency signal input port 3 can be detected by the detector 8. The power level of the high frequency signal can be monitored. Then, by controlling this detected voltage in the gate voltage controller 9 and inputting this voltage to the FETI as a gate voltage, it is possible to control the gate bias and the drain current applied from the drain bias port 6. become.

Therefore, if the gate voltage controller 9 is set to suppress the drain current when the input level of the high-frequency signal is low and increase the drain current as the input level rises, the input power will be reduced when the input power is not in operation. Detector 8
If it is not detected, the gate voltage reaches the pinch-off voltage and no drain current flows, making it possible to reduce power consumption.

As a result, even when a high power amplifier is configured with FETs, power consumption during non-operation can be reduced. Furthermore, in order to obtain equivalent cross-modulation distortion characteristics, it is possible to simplify the circuit configurations of the high frequency circuit section and the DC bias circuit section.

〔Effect of the invention〕

As explained above, the present invention is configured to detect the high-frequency signal manually applied to the FET, and control the voltage applied to the gate of the FET based on this detected signal with the gate voltage controller. When the FET is not in operation and no signal is input, the gate voltage applied from the gate voltage controller to the FET is set below the pinch-off voltage, thereby reducing the drain current of the FET and reducing power consumption.

Further, it is possible to correct variations in the cross-modulation distortion characteristics of the FET, and also to realize temperature compensation for the cross-modulation distortion characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional gate voltage control circuit.

Claims (1)

[Claims] 1. In the gate voltage control circuit that controls the gate voltage applied to the gate of the FET, there is a directional coupler that takes out a part of the high frequency signal input to the FET, and a detection of the high frequency signal taken out by this directional coupler. What is claimed is: 1. A gate voltage control circuit comprising: a wave detector; and a gate voltage controller that controls a voltage applied to the gate of the FET based on a signal detected by the wave detector.