JPH02148760A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02148760A JPH02148760A JP30118988A JP30118988A JPH02148760A JP H02148760 A JPH02148760 A JP H02148760A JP 30118988 A JP30118988 A JP 30118988A JP 30118988 A JP30118988 A JP 30118988A JP H02148760 A JPH02148760 A JP H02148760A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- groove
- polycrystalline silicon
- silicon
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 7
- 238000001947 vapour-phase growth Methods 0.000 claims description 9
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- 229910000077 silane Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910001507 metal halide Inorganic materials 0.000 claims description 3
- 150000005309 metal halides Chemical class 0.000 claims description 3
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 claims description 3
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 3
- 239000005052 trichlorosilane Substances 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 21
- 239000004020 conductor Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- 239000007789 gas Substances 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関し、半導体基板に
形成されたトレンチ溝のみを電気伝導体により埋め込む
プロセスの、より改善された方法を提供することを目的
としたものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and an object of the present invention is to provide an improved method of filling only trenches formed in a semiconductor substrate with an electrical conductor. The purpose is to
従来の技術
従来の半導体装置の製造方法においては、トレンチ溝の
形成された半導体基板を酸化した後に、多結晶シリコン
を上記半導体基板上に気相成長法により全面に堆積した
後に、リン拡散によりリンを上記多結晶シリコン中に拡
散することで上記多結晶シリコンの比抵抗を下げた後、
また第２の多結晶シリコンを上記多結晶シリンコ上に気
相成長法により全面に堆積し、同様な手段によりリン拡
散を行ない、上記第２の多結晶シリコンの比抵抗を下げ
るという工程を繰り返すことで、上記トレンチ溝を多結
晶シリコンで埋め込んだ後、エッチバック法により上記
トレンチ溝以外の部分に堆積された上記多結晶シリコン
を除去することで、上記トレンチ溝部分のみにリン拡散
のされた多結晶シリコンが形成されるという技術が知ら
れている。BACKGROUND OF THE INVENTION In a conventional semiconductor device manufacturing method, a semiconductor substrate in which a trench has been formed is oxidized, polycrystalline silicon is deposited on the entire surface of the semiconductor substrate by vapor phase growth, and then phosphorus is removed by phosphorus diffusion. After lowering the resistivity of the polycrystalline silicon by diffusing it into the polycrystalline silicon,
Further, repeating the process of depositing a second polycrystalline silicon over the entire surface of the polycrystalline silicon by a vapor phase growth method, and performing phosphorus diffusion by the same means to lower the resistivity of the second polycrystalline silicon. After filling the trench groove with polycrystalline silicon, the polycrystalline silicon deposited in the area other than the trench groove is removed by an etch-back method, so that the polycrystalline silicon with phosphorus diffused only in the trench groove area is removed. Techniques are known in which crystalline silicon is formed.
発明が解決しようとする課題
しかしながら、トレンチ溝の幅が０．５μｍ程度になっ
た場合、リン拡散を行なった多結晶シリコンの比抵抗で
はトレンチ溝内部の抵抗が高くなり過ぎ、トレンチキャ
パシタの安定した動作が得られず、また、リン拡散を行
なう回数を増加すると工程が増加すると共に、リン拡散
の量が多くなるとリンを含んだ化合物の析出が発生し、
不良の原因となる。Problems to be Solved by the Invention However, when the width of the trench is about 0.5 μm, the resistivity inside the trench becomes too high with the specific resistance of polycrystalline silicon that has undergone phosphorus diffusion, making it difficult to stabilize the trench capacitor. In addition, increasing the number of times phosphorus diffusion is performed increases the number of steps, and increasing the amount of phosphorus diffusion causes precipitation of phosphorus-containing compounds.
This may cause defects.
また、多結晶シリコンを堆積した後エッチバックにより
トレンチ溝以外の多結晶シリコンを除去する必要があり
、工程数が多（なると共に、トレンチ溝の幅が微細化さ
れるに伴いエッチバックが難しくなり、歩留りも悪化す
るという問題を有していた。In addition, after depositing polycrystalline silicon, it is necessary to remove polycrystalline silicon other than the trench by etchback, which requires a large number of steps (and as the width of the trench becomes smaller, etchback becomes more difficult). However, there was a problem in that the yield also deteriorated.
本発明は、かかる点に鑑み、半導体基板に形成されたト
レンチ溝のみを電気伝導体により埋め込むプロセスのよ
り改善された方法を提供することを目的としたものであ
る。SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an improved method of filling only trenches formed in a semiconductor substrate with an electrical conductor.
課題を解決するための手段
トレンチ溝を有する半導体基板上に絶縁膜を形成し、多
結晶シリコンあるいはアモルファスシリコンを上記トレ
ンチ溝にのみ形成した後、気相成長法により金属ハロゲ
ン化物と上記多結晶シリコンあるいはアモルファスシリ
コン、水素、シラン、ジクロルシラン、トリクロルシラ
ン、シリコンクロライドのうち少な（とも１つとの反応
により選択的に上記トレンチ溝部分のみに金属を堆積し
、上記トレンチ部分のみを埋め込むことを特徴とする半
導体装置の製造方法である。Means for Solving the Problems After forming an insulating film on a semiconductor substrate having a trench, and forming polycrystalline silicon or amorphous silicon only in the trench, a metal halide and the polycrystalline silicon are deposited by vapor phase growth. Alternatively, metal is selectively deposited only in the trench groove portion by reaction with a small amount (one or more) of amorphous silicon, hydrogen, silane, dichlorosilane, trichlorosilane, and silicon chloride, thereby filling only the trench portion. This is a method for manufacturing a semiconductor device.
作用
本発明は、トレンチ溝に電気伝導体として気相成長法に
より金属ハロゲン化物を用い金属を堆積することにより
、比抵抗が従来の多結晶シリコンよりも充分に低いため
、０．５μｍ以下の幅を持ったトレンチ溝に対しても適
応することが可能であり、更に選択的にトレンチ溝にの
み金属が堆積されることにより、その後のエッチバック
の工程が必要ないため工程数が少なくなり、安定したプ
ロセスを提供することが可能となる。Function The present invention uses a metal halide to deposit metal as an electrical conductor in the trench groove by vapor phase growth, so that the resistivity is sufficiently lower than that of conventional polycrystalline silicon. It can also be applied to trench grooves with It becomes possible to provide a process that
実施例
（実施例１）
以下実施例により詳細に説明する。第１図（Ａ）〜（Ｃ
）は本発明による半導体装置の作成方法の第１の実施例
を工程順に示したものである。Example (Example 1) A detailed explanation will be given below using an example. Figure 1 (A)-(C
) shows the first embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps.
（Ａ）トレンチ溝１及び絶縁膜３を有する半導体基板２
上の全面に気相成長法により多結晶シリコン４を堆積す
る。この時、トレンチ溝１の幅は例えば０．５μｍとし
、深さは４．０μｍとする。また、絶縁膜３の厚さは例
えば１０ｎｍとし、多結晶シリコン４の厚さは１１００
ｎとする。(A) Semiconductor substrate 2 having trench groove 1 and insulating film 3
Polycrystalline silicon 4 is deposited on the entire surface by vapor phase growth. At this time, the width of the trench groove 1 is, for example, 0.5 μm and the depth is 4.0 μm. Further, the thickness of the insulating film 3 is, for example, 10 nm, and the thickness of the polycrystalline silicon 4 is 110 nm.
Let it be n.
（Ｂ）その後、エツチングガスを半導体基板２に対し垂
直に入射することにより、多結晶シリコン４の異方性エ
ツチングを行なうことでトレンチ溝１の側壁にのみ多結
晶シリコン４を残存させる。(B) Thereafter, etching gas is applied perpendicularly to the semiconductor substrate 2 to perform anisotropic etching of the polycrystalline silicon 4, thereby leaving the polycrystalline silicon 4 only on the side walls of the trench groove 1.
この時、絶縁膜３上に多結晶シリコンが残らない条件を
選ぶ。At this time, conditions are selected so that no polycrystalline silicon remains on the insulating film 3.
（Ｃ）その後、気相成長法により、例えば６フツ化タン
グステン、シラン及び水素を用いて、上記トレンチ１に
のみタングステン５を堆積させる。(C) Thereafter, tungsten 5 is deposited only in the trench 1 using, for example, tungsten hexafluoride, silane, and hydrogen by vapor phase growth.
この時例えば６フツ化タングステンのガス流量は１１０
５ＣＣ、シランのガス流量は５８ＣＣＭ、水素のガス流
量は１１００５ＣＣとし、０．１５ｔｏｒｒの真空中に
て行ない、反応温度は２５０℃とする。At this time, for example, the gas flow rate of tungsten hexafluoride is 110
5CC, the silane gas flow rate is 58CCM, the hydrogen gas flow rate is 11005CC, the reaction is carried out in a vacuum of 0.15 torr, and the reaction temperature is 250°C.
（実施例２）
第２図（Ａ）〜（Ｃ）は、本発明による半導体装置の製
造方法の第２の実施例を工程順に示したものである。(Example 2) FIGS. 2A to 2C show a second example of the method for manufacturing a semiconductor device according to the present invention in order of steps.
（Ａ）第１の実施例における（Ａ）の工程後、多結晶シ
リコン４上にレジストを均一に塗布する。(A) After the step (A) in the first embodiment, a resist is uniformly applied onto the polycrystalline silicon 4.
（Ｂ）その後、全面をエツチングすることで絶縁膜３上
のみの多結晶シリコン４を除去した後に、トレンチ溝１
内部に残留したレジスト６を除去することで、トレンチ
溝１のみに多結晶シリコン４を形成する。(B) Then, after removing the polycrystalline silicon 4 only on the insulating film 3 by etching the entire surface, the trench groove 1
By removing the resist 6 remaining inside, polycrystalline silicon 4 is formed only in trench groove 1.
（Ｃ）第１の実施０例における（Ｃ）の工程と同じ手法
にて、トレンチ溝１のみに選択的にタングステン５を堆
積させる。(C) Tungsten 5 is selectively deposited only in the trench 1 using the same method as in the step (C) in the first embodiment.
（実施例３）
第３図（Ａ）〜（Ｄ）は、本発明による半導体装置の製
造方法の第３の実施例を工程順に示したものである。(Example 3) FIGS. 3A to 3D show a third example of the method for manufacturing a semiconductor device according to the present invention in the order of steps.
（Ａ）絶縁膜７をマスクとして、ドライエツチングによ
り形成されたトレンチ溝１を有する半導体基板２上に絶
縁膜３を形成した後、全面に気相成長法により多結晶シ
リコン４を形成する。トレンチ溝１．絶縁膜３及び多結
晶シリコン４のサイズは第１の実施例の（Ａ）の工程と
同様とする。(A) Using the insulating film 7 as a mask, an insulating film 3 is formed on the semiconductor substrate 2 having the trenches 1 formed by dry etching, and then polycrystalline silicon 4 is formed on the entire surface by vapor phase growth. Trench groove 1. The sizes of the insulating film 3 and polycrystalline silicon 4 are the same as in the step (A) of the first embodiment.
（Ｂ）第１の実施例の（Ｂ）の工程と同様な手法によっ
て多結晶シリコン４をトレンチ溝１の側壁にのみ残存さ
せる。(B) The polycrystalline silicon 4 is left only on the side walls of the trench groove 1 by a method similar to the step (B) of the first embodiment.
（Ｃ）第２の実施例の（Ｃ）の工程と同様な手法によっ
て、トレンチ溝１にのみタングステン５を堆積させる。(C) Tungsten 5 is deposited only in the trench groove 1 by a method similar to the step (C) of the second embodiment.
（Ｄ）その後、全面をシリコン基板２が現われる迄、全
面エツチングし、平坦化を行なう。(D) Thereafter, the entire surface is etched and planarized until the silicon substrate 2 appears.
（実施例４〉
第４図（Ａ）〜（Ｃ）は、本発明による半導体装置の製
造方法の第４の実施例を工程順に示したものである。(Example 4) FIGS. 4A to 4C show a fourth example of the method for manufacturing a semiconductor device according to the present invention in the order of steps.
（Ａ）第３の実施例における（Ａ）の工程後、多結晶シ
リコン上にレジストを均一に塗布する。(A) After the step (A) in the third embodiment, a resist is uniformly applied onto the polycrystalline silicon.
（Ｂ）第２の実施例における（Ｂ）の工程と同様な手法
によって多結晶シリコン４をトレンチ溝１のみに形成す
る。(B) Polycrystalline silicon 4 is formed only in the trench groove 1 by a method similar to the step (B) in the second embodiment.
（、Ｃ）第１の実施例における（Ｃ）の工程と同様な手
法にて、トレンチ溝１のみに選択的にタングステン５を
堆積する。(,C) Tungsten 5 is selectively deposited only in the trench groove 1 using a method similar to the step (C) in the first embodiment.
（Ｄ）その後、実施例３の（Ｄ）の工程と同様な手法に
より、半導体基板２が現われる迄、全面エツチングし、
平坦化を行なう。(D) Thereafter, the entire surface is etched until the semiconductor substrate 2 appears by a method similar to the step (D) of Example 3,
Perform flattening.
以上のように本実施例によれば、電気伝導体としてタン
グステン５を用いてトレンチ溝を選択的に埋め込むこと
により、比抵抗が従来の多結晶シリコンよりも充分に低
いため、０．５μｍ以下の幅を持ったトレンチ溝にも適
応することが可能であり、更に、選択的にトレンチ溝１
のみにタングステンを堆積することにより、工程が簡略
化され、トレンチキャパシタとして有用である。As described above, according to this embodiment, by selectively filling the trench grooves with tungsten 5 as an electrical conductor, the resistivity is sufficiently lower than that of conventional polycrystalline silicon, so that It is possible to adapt to a trench groove with a width, and furthermore, it is possible to selectively cut the trench groove 1.
Depositing tungsten only on the substrate simplifies the process and is useful as a trench capacitor.
なお、実施例として、トレンチ溝１の幅を０．５μｍと
し、深さを４．０μｍとしたが、それ以下のあるいはそ
れ以上の幅あるいは深さのトレンチ溝でも良く、また、
絶縁膜３の厚さを１０ｎｍとし、多結晶シリコン４の厚
さを１１００ｎとしたが、それ以外の厚さでも良い。ま
た、６フツ化タングステンガス、シランガス及び水素ガ
スを用いてタングステン５を堆積する時に、６フツ化タ
ングステンガスの流量をＩＯ８ＣＣＭ、シランガスの流
量を５ＳＣＣＭ、水素ガスの流量を１１００３ＣＣとし
、Ｏ，１５ｔｏｒｒの真空中で反応温度を２５０℃とし
たが、選択的にトレンチ溝１のみにタングステンが堆積
される条件ならば、それ以上あるいはそれ以下でも良く
、また、水素ガスの代わりにアルゴンガスあるいはヘリ
ウムガスのような不活性ガスを用いても良く、また、シ
ランの代わりにジクロルシラン、トリクロルシラン、シ
リコンクロライド等を用いても良い。また、多結晶シリ
コンの代わりにアモルファスシリコンを用いても良いし
、あるいはタングステンが選択的に堆積されるための核
となるものでも良、い。また、タングステンの代わりに
モリブデンなどの高融点金属を用いても良い。In addition, as an example, the width of the trench groove 1 was set to 0.5 μm and the depth was set to 4.0 μm, but the trench groove may have a width or depth smaller than or greater than that.
Although the thickness of the insulating film 3 was 10 nm and the thickness of the polycrystalline silicon 4 was 1100 nm, other thicknesses may be used. In addition, when depositing tungsten 5 using tungsten hexafluoride gas, silane gas, and hydrogen gas, the flow rate of tungsten hexafluoride gas is IO8CCM, the flow rate of silane gas is 5SCCM, and the flow rate of hydrogen gas is 11003CC, and the Although the reaction temperature was set at 250°C in vacuum, the temperature may be higher or lower as long as tungsten is selectively deposited only in the trench groove 1. Also, argon gas or helium gas may be used instead of hydrogen gas. Alternatively, dichlorosilane, trichlorosilane, silicon chloride, etc. may be used instead of silane. Further, amorphous silicon may be used instead of polycrystalline silicon, or it may be used as a nucleus on which tungsten is selectively deposited. Further, a high melting point metal such as molybdenum may be used instead of tungsten.
発明の詳細
な説明したように、本発明によれば、電気伝導体として
金属を用いてトレンチ溝を埋め込むことにより、比抵抗
が従来の多結晶シリコンよりも充分低いため、０．５μ
ｍ以下の幅を持ったトレンチ溝であっても抵抗率がそれ
程高くならないため、トレンチキャパシタでの電気的な
遅延が起こらない。更に、気相成長法により選択的にト
レンチ溝のみに金属が堆積されるため、工程が簡略化さ
れ、その実用的効果は大きい。As described in detail, according to the present invention, by filling the trench with metal as an electrical conductor, the resistivity is sufficiently lower than that of conventional polycrystalline silicon, so that the resistivity is 0.5μ.
Even if the trench has a width of less than m, the resistivity does not become very high, so no electrical delay occurs in the trench capacitor. Furthermore, since metal is selectively deposited only in the trench grooves by vapor phase growth, the process is simplified and its practical effects are great.
第１図は実施例１にかかる半導体装置の製造工程断面図
、第２図は実施例２にかがる半導体装置の製造工程断面
図、第３図は実施例３にかかる半導体装置の製造工程断
面図、第４図は実施例４にかかる半導体装置の製造工程
断面図である。
１・・・・・・トレンチ溝、２・・・・・・半導体基板
、３・・・・・・絶縁膜、４・・・・・・多結晶シリコ
ン、５・・・・・・タングステン、６・・・・・・レジ
スト、７・・・・・・絶縁膜。
代理人の氏名 弁理士 粟野重孝 ほか１名図1 is a cross-sectional view of the manufacturing process of a semiconductor device according to Example 1, FIG. 2 is a cross-sectional view of the manufacturing process of a semiconductor device according to Example 2, and FIG. 3 is a cross-sectional view of the manufacturing process of a semiconductor device according to Example 3. 4 is a cross-sectional view of the manufacturing process of the semiconductor device according to the fourth embodiment. 1... Trench groove, 2... Semiconductor substrate, 3... Insulating film, 4... Polycrystalline silicon, 5... Tungsten, 6...Resist, 7...Insulating film. Name of agent: Patent attorney Shigetaka Awano and one other person
Claims (2)
絶縁膜が存在し、上記トレンチ溝内の絶縁膜にそっての
み多結晶シリコン、あるいはアモルファスシリコンが存
在し、上記トレンチ溝の残りの部分がすべて金属により
埋め込まれた構造を特徴とする半導体装置。(1) An insulating film exists in the trench of a semiconductor substrate having a trench, polycrystalline silicon or amorphous silicon exists only along the insulating film in the trench, and the remaining part of the trench is A semiconductor device characterized by a structure completely filled with metal.
基板において、上記トレンチにのみ多結晶シリコンある
いはアモルファスシリコンを形成した後、気相成長法に
より金属ハロゲン化物と上記多結晶シリコン、水素、シ
ラン、ジクロルシラン、トリクロルシラン、シリコンク
ロライドのうち少なくとも１つとの反応により選択的に
上記トレンチ溝部分のみに金属を堆積し、上記トレンチ
溝部分のみを埋め込むことを特徴とする半導体装置の製
造方法。(2) In a semiconductor substrate having a trench groove (separation groove) and an insulating film, polycrystalline silicon or amorphous silicon is formed only in the trench, and then metal halide and the polycrystalline silicon, hydrogen, and silane are formed by vapor phase growth. , dichlorosilane, trichlorosilane, and silicon chloride, selectively depositing metal only on the trench groove portion, and filling only the trench groove portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30118988A JPH02148760A (en) | 1988-11-29 | 1988-11-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30118988A JPH02148760A (en) | 1988-11-29 | 1988-11-29 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02148760A true JPH02148760A (en) | 1990-06-07 |
Family
ID=17893846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30118988A Pending JPH02148760A (en) | 1988-11-29 | 1988-11-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02148760A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196551A (en) * | 1992-09-04 | 1994-07-15 | Internatl Business Mach Corp <Ibm> | Flattening of recessed part surface of semiconductor structure |
| US5475257A (en) * | 1992-02-19 | 1995-12-12 | Nec Corporation | Semiconductor device having an improved low resistive contact |
| US5675173A (en) * | 1995-01-19 | 1997-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for isolating elements and a trench for applying a potential to a substrate |
| US6465888B2 (en) * | 2000-06-05 | 2002-10-15 | Chartered Semiconductor Manufacturing Ltd. | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene |
| JP2019145790A (en) * | 2018-02-15 | 2019-08-29 | パナソニックＩｐマネジメント株式会社 | Capacitance element and manufacturing method thereof |
-
1988
- 1988-11-29 JP JP30118988A patent/JPH02148760A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5475257A (en) * | 1992-02-19 | 1995-12-12 | Nec Corporation | Semiconductor device having an improved low resistive contact |
| JPH06196551A (en) * | 1992-09-04 | 1994-07-15 | Internatl Business Mach Corp <Ibm> | Flattening of recessed part surface of semiconductor structure |
| US5675173A (en) * | 1995-01-19 | 1997-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for isolating elements and a trench for applying a potential to a substrate |
| US6465888B2 (en) * | 2000-06-05 | 2002-10-15 | Chartered Semiconductor Manufacturing Ltd. | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene |
| JP2019145790A (en) * | 2018-02-15 | 2019-08-29 | パナソニックＩｐマネジメント株式会社 | Capacitance element and manufacturing method thereof |
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