JPH02148244A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute data transfer at a high speed by providing a means for rearranging an array of an internal data bus at every 1 byte. CONSTITUTION:When a bus converting circuit control signal 8 is 'low', a bus converting circuit 4 allocates data on a second internal lower data bus 6-2 and data on a second internal upper data bus 6-1 to the upper type of an internal register 10 and the lower byte of the internal register 10, respectively. On the other hand, when the bus converting circuit control signal 8 is 'high', the bus converting circuit 4 allocates the data on a second internal upper data bus 6-1 and data on a second internal lower data bus 6-2 to the upper byte of the internal register 10 and the lower byte of the internal register 10, respectively. In such a way, it is unnecessary to rearrange the data, and a substantial transfer speed is high.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microprocessors. More specifically, the present invention relates to a microprocessor capable of converting the arrangement of internal data buses.

BACKGROUND ART FIG. 4 shows a block diagram of an example of a conventional □ microprocessor. The microprocessor shown in FIG. 4 is a microprocessor with a 16-bit data bus, and includes a unit (hereinafter referred to as BCU) 3 that interfaces between the inside and outside of the microprocessor, and a unit (hereinafter referred to as BCU) that executes instructions. (hereinafter referred to as EXU) 2, an internal upper data bus 6-1 connected to the internal register 10-1 of the EXU 2, the BCU 3, and the microprocessor external data bus for exchanging data between the BCU 3 and the external data bus; It has an internal lower data bus 6-2.

The conventional microprocessor described above operates as follows. When EXU2 executes an instruction to write data to the outside, data in the upper byte of register 10-1 inside EXU2 is transferred to the internal upper data bus 6-1, and data in the lower byte of register 10-1 is transferred to the internal lower data bus 6-1. The data is outputted to the data bus 6-2 through the BCU 3 and written via the external data bus. In addition, when EXU 2 executes an instruction to read data from the outside, conversely, the data written to the internal upper data bus 6-1 via the external data bus is transferred to the upper byte of the internal register 10-1. The data written to the data bus 6-2 is read into the lower byte of the internal register 10-1 by the BCU 3.

Some of the conventional microprocessors mentioned above have different connections between internal registers and internal data buses. FIG. 5 shows two types of microprocessors with different connections between internal registers and internal data buses. The microprocessor A shown in FIG. 5 has an internal register 10-2.
Data 20 of internal upper data bus 6-1 is stored in the upper byte of
, data 21 of the internal lower data bus 6-2 is allocated to the lower byte of the internal register 10-2. On the other hand, microprocessor B in FIG.
Data 21 on the internal lower data bus 6-2 is allocated to the upper byte of the internal register 10-3, and data 20 on the internal upper data bus 6-1 is allocated to the lower byte of the internal register 10-3.

Problems to be Solved by the Invention As described above, some conventional microprocessors have different allocations of upper bytes and lower bytes in the connection between registers inside the microprocessor and internal data buses. This poses a problem when configuring a device in which multiple microprocessors are connected to a data bus. FIG. 6 shows an example of a device in which a plurality of microprocessors are connected to a data bus.

The device shown in FIG. 6 is a device in which a microprocessor 15.16 and a memory 17 shared by the microprocessor 15.16 are connected to a lower data bus 18 and an upper data bus 19. Microprocessor 15 has internal registers 10-2 as in the microprocessor of FIG.
The upper bytes of the internal data bus are allocated to each other, and the lower bytes are allocated to each other. Further, in the microprocessor 16, like the microprocessor B in FIG. 5, the upper byte of the internal register 10-3 is allocated to the internal lower data bus, and the lower byte of the internal register 10-3 is allocated to the internal upper data bus. .

In the device shown in FIG.
When writing the data "1234." held in the internal register to the memory 17, the microprocessor 15 transfers the data "12." of the upper byte of the internal register 10-2 to the upper data bus 19, and writes the data "12."
-2 lower byte data "34H'" is output to the lower data bus 18. As a result, "12n" is written on the upper byte side of the memory 17, and '34.' is written on the lower byte side. ''' is written.Next, when reading this data into the internal register 10-3 of the microprocessor 16, the memory 17
is '12.' on the upper data bus 19. ” to the lower data bus 18, but the microprocessor 1
The data "3412." is set in the internal register 10-3 of No. 6.

As described above, in the device having the configuration shown in FIG. 6, a problem arises in that the data in the upper and lower bytes of the internal register of the microprocessor 15.1G are reversed. Therefore, in the past, a conversion circuit was provided between the microprocessor 16 and the upper data bus 19 and lower data bus 18. In addition, if the microprocessor 16 has an instruction to change the upper byte and lower byte of the internal register 10-3, the data is transferred to the internal register 10-3.
-3, this instruction is executed and the data in the upper byte and lower byte of the internal register 10-3 are swapped. Therefore, the processing time required to transfer data from the microprocessor 15 to the microprocessor 16 becomes long.

An object of the present invention is to provide a microprocessor capable of high-speed data transfer that solves the problems of the prior art described above.

Means for Solving the Problems According to the present invention, in a microprocessor having an internal data bus divided into a plurality of parts, a human input signal from an external input terminal or a signal generated internally by the microprocessor executing an instruction is provided. provides a microprocessor characterized by comprising switching means for rearranging the arrangement of the divided internal data buses for each byte.

Operation The microprocessor of the present invention realizes rearranging the data bus arrangement inside the microprocessor in units of bytes. Therefore, when used in a device with multiple microprocessors connected via a data bus,
All the data buses inside the microprocessor can be arranged equally. Therefore, when data is transferred between microprocessors, there is no need to change the data arrangement, so the data transfer speed is high.

Hereinafter, the present invention will be explained in more detail with reference to Examples.
The following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 shows a block diagram of an example of a microprocessor of the present invention. The microprocessor 1-1 shown in FIG. 1 is equipped with a bus conversion circuit 4, as compared with the conventional microprocessor 1-3 shown in FIG.
It includes first internal data buses 5-1 and 5-2 that connect to the CU 3, and second internal data buses 6-1 and 6-2 that connect the external data bus and the bus conversion circuit 4. However, this is the most different point. That is, the microprocessor of this embodiment uses the internal register 10 of EXU2.
The first internal high-order data bus 5-1 is allocated to the high-order byte of the internal register 10 of the second internal high-order data bus 6-LEXU2 connected to the external high-order data bus. The first internal lower data bus 5-2 and the second internal lower data bus 6-2 connected to the external lower data bus are connected to the bus conversion circuit 4.
It is connected to the. Further, the bus conversion circuit 4 receives an external bus conversion circuit control signal 8 from the BCU 3 via R/W (
')-1'/write) signal 9 is input and controlled.

FIG. 2 shows a circuit diagram of the bus conversion circuit 4 described above. The bus conversion circuit of this embodiment has a first internal upper data bus 5-
Bidirectional buffer 12-L connected to the first and second internal upper data buses 6-1, both connected to the first internal lower data bus 5-2 and the second internal lower data bus 6-2. a bidirectional buffer 13-1 and a second internal upper data bus 5-2 connected to the bidirectional buffer 12-2, the first internal upper data bus 5-1, and the second internal lower data bus 6-2; It mainly consists of a bidirectional buffer 13-2 connected to the second internal upper data bus 6-1.

Bidirectional buffers 12-1 and 12-2 are selected by bus conversion circuit signal 8, and bidirectional buffers 13-1 and 1
3-2 is selected by the bus conversion circuit signal 8 which has passed through the inverter 11. The R/W signal 9 controls the direction of data flow. That is, when the R/W signal 9 is "low", the R/W signal is transferred from the first internal data bus to the second internal data bus.
When the W signal 9 is "high", data is transferred from the second internal data bus to the first internal data bus.

First, the hash conversion circuit control signal 8 is "low"', R/W
When the signal 9 is “high”, the bidirectional buffer 13-1
and 13-2 are selected, and thereby the first internal upper data bus 5-1 and the second internal lower data bus 6-2 are selected.
, a first internal lower data bus 5-2 and a second internal upper data bus 6-1 are connected. Further, data is transferred from the second internal data bus to the first internal data bus by the R/W signal 9. That is, data is sent from the second internal lower data bus 6-2 to the first internal upper data bus 5-1, and from the second internal higher data bus 6-1 to the first internal lower data bus 5-2. It is something that can be done.

Next, both the bus conversion circuit control signal 8 and the R/W signal 9 are “
If “high”, bidirectional buffers 12-1 and 12-2
is selected, and as a result, the first internal upper data bus 5
-1 and the second internal upper data bus 6-1 are connected to the first internal lower data bus 5-2 and the second internal lower data bus 6-1.
2 is connected. Also, the data is as in the above case,
Data is transferred from the second internal data bus to the first internal data bus.

That is, data is sent from the second internal lower data bus 6-1 to the first internal upper data bus 5-1, and from the second internal higher data bus 6-2 to the first internal lower data bus 5-2. It is something that can be done.

The bus conversion circuit 4 of this embodiment has two types of first and second bus conversion circuits depending on the state of the bus conversion circuit control signal 8 as described above.
This is used to switch the internal data bus connection pattern.

In the microprocessor of this embodiment, the above-mentioned bus conversion circuit 4 switches the pattern of allocation of the internal register 10 of the EXU 2 and the upper byte and lower byte of the internal data bus. Specifically, the bus conversion circuit control signal 8 is “
LOW”, the bus conversion circuit 4 transfers the data on the second internal lower data bus 6-2 to the upper byte of the internal register 10, and transfers the data on the second internal lower data bus 6-2 to the lower byte of the internal register 10. -1 is assigned.Also, when the bus conversion circuit control signal 8 is “high”, the bus conversion circuit 4
allocates the data on the second internal upper data bus 6-1 to the upper byte of the internal register 10, and the data on the second internal lower data bus 6-2 to the lower byte of the internal register 10-1. As a result, it is possible to realize the layout pattern for both microprocessor A and microprocessor B in FIG. 5, so there is no need to rearrange the data even when used in the device shown in FIG.
The actual transfer speed is fast.

Embodiment 2 A block diagram of a second embodiment of the microprocessor of the present invention is shown in FIG. Microprocessor 1- of this embodiment
2 is a microprocessor according to the first embodiment, in which a bus conversion circuit 4 is connected to a flip-flop (D-FF) 14 that is controlled by a signal group 7 internally generated by the EXU 2 and generates a bus conversion circuit control signal 8. This is different from 1-1.

That is, while the microprocessor 1-1 of the first embodiment controls the bus conversion circuit 4 using the bus conversion circuit control signal 8 inputted from the outside, the microprocessor 1-2 of the present embodiment controls the bus conversion circuit 4 using the bus conversion circuit control signal 8 inputted from the outside. The bus conversion circuit 4 is controlled by the bus conversion circuit control signal 8 generated by the Philips flop 14 using the internally generated signal group 7.

Specifically, the microprocessor 1-2 operates the flip-flop 14 by the signal group 7 internally generated when the EXU 2 executes a special instruction given from the outside, and performs bus conversion with a certain constant state. Circuit control signal 8
is generated, and the bus conversion circuit 4 is controlled by this signal. The subsequent operation is exactly the same as that in the first embodiment, so the explanation will be omitted.

The microprocessor of the present invention can change the arrangement of the internal data bus in units of bytes. Therefore, when data is transferred between a plurality of microprocessors, high-speed data transfer is possible by aligning the internal data buses of all the microprocessors in advance.

Effects of the Invention As detailed above, the microprocessor of the present invention has the ability to provide information regarding the internal data bus arrangement from outside the microprocessor and perform bus conversion within the microprocessor based on this information. have Therefore, it is possible to share devices such as memory with microprocessors having different internal data bus configurations without an external bus conversion circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the microprocessor sensor of the present invention, FIG. 2 is a circuit diagram of a bus conversion circuit of the microprocessor of FIG. 1, and FIG. 3 is a block diagram of an example of the microprocessor of the present invention. FIG. 4 is a block diagram of a conventional microprocessor sensor, and FIG. 5 shows byte data allocated to the internal disk of the conventional microprocessor sensor. FIG. 6 is a block diagram of a device having two microprocessors. [Main reference numbers] 1-1.1-2.1-3.15.16... Microprocessor, 2... Execution unit (EXU), 3... Bus control unit (BCU), 4... ...Bus conversion circuit, 5-1..First internal upper data bus, 5-2..First
internal lower data bus, 6-1... second internal upper data bus, 6-2... second internal lower data bus, 7...
・Internally generated signal group, 8...Bus conversion circuit control signal, 9. ・R/W (read/write) signal, 10.
・Internal register, 10-2...Internal register of microprocessor 15,
10-3: Internal register of microprocessor 16,
11... Inverter, 12-1.12-2.13-1.13-2... Bidirectional buffer, 14... Phillip 7' (D-FF
), 17...Memory, 18...Lower data bus, 19...Upper data bus,

Claims (1)

[Claims] In a microprocessor equipped with a plurality of divided internal data buses, the arrangement of the divided internal data buses is determined by an input signal from an external input terminal or a signal internally generated when the microprocessor executes an instruction. A microprocessor comprising switching means for rearranging each byte.