JPH02146849A - Ringer reception circuit - Google Patents

Abstract

PURPOSE:To realize a band pass characteristic with low distortion to a ringer and to decrease the reception distortion of the ringer by driving a pulse generating circuit depending on the rise and fall of a ringer detection circuit. CONSTITUTION:A ringer detection circuit 1 compares a ringer signal (a) with a DC threshold voltage and outputs '0' or '1' depending on the quantity. A pulse generator 2 is started by the rise of a signal (b) from the circuit 1 and outputs a signal (c) being a pulse T1 being a setting width. Moreover, a pulse generator 3 is started by the fall of a signal (b) and outputs a signal (d) being a pulse T2 being a setting width. A NAND circuit 4 obtains the NAND logic of the signals (c), (d) to output a signal (e). A pulse generator 5 is activated by the rise of the signal (e) and a signal (f) being a pulse T3 of a setting length is outputted. Thus, the ringer signal (a) is received without distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ringer receiving circuit, and more particularly to a ringer receiving circuit used in a subscriber line carrier connected to a telephone exchange to receive a subscriber's calling signal on a low frequency. Regarding a receiving circuit.

[Conventional technology]

Conventionally, this type of ringer receiving circuit has been configured to start the pulse generator using only the rising edge or falling edge of the ringer signal (hereinafter referred to as ringer) detected by the ringer detection circuit.

[Problem to be solved by the invention]

The conventional ringer receiver circuit described above is configured to activate the pulse generator only once per ringer period using only the rising edge or the falling edge of the signal converted to a logic level by the ringer detection circuit. Therefore, the ringer input in bursts may start in the middle of the cycle, or
Alternatively, if the cycle ends in the middle of the cycle, ringer reception near the maximum cycle cannot be recognized, resulting in increased ringer reception distortion.

[Means to solve the problem]

The ringer receiving circuit of the present invention includes a ringer detection circuit that compares a ringing signal with a preset threshold voltage and outputs a binary signal, and a ringer detection circuit that is activated at the rising and falling edges of the binary signal to generate the ringing signal. first and second pulse generators that output first and second signals having a pulse width shorter than the shortest period of the pulse generator;
AND circuit and a third circuit that outputs a signal with a pulse width of a preset time using the output from this NAND circuit.
It has a pulse generator.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The ringer detection circuit l detects the input ringer (a),
Compare the DC amount value and voltage set in advance, and if it is higher than the threshold voltage, the logic level °'0°.

If it is low, a signal (b) of logic level "1" is output.

The first pulse generator 2 is activated by the rise of the signal (b) from the ringer detection circuit 1, and outputs a signal (C) of a pulse T1 having a set length.

The second pulse generator 3 is activated by the fall of the signal (b) from the ringer detection circuit 1, and outputs a signal (d) of a pulse T2 having a set length.

The NAND circuit 4 inputs the signals (C) and (d) from the first pulse generator 2 and the second pulse generator 3, and
A signal (e) whose ND logical value has been determined is output.

The third pulse generator 5 receives the signal (
It is activated by the rising edge of °e) and outputs a pulse T3 signal (f) with a set length.

FIG. 2 is a time chart showing the operation of an embodiment of the present invention.

The ringer (a) indicated by one period T is the ringer detection circuit 1.
The ringer is compared with the threshold voltage V7H set in
Obtain the detection circuit output (b). First pulse generator output (
c) is a pulse of length T1, where T1 is set shorter than the shortest period T m I n of the ringer.

The second pulse generator output (d) becomes a pulse of length T2, and like T1, it is set shorter than the shortest cycle of the ringer, T1°. NAND circuit output (e) is signal output (C)
, (d) becomes the NAND logic output.

The third pulse generator output (f) is the NAND circuit output (
The pulse ends after a time T3 from the final rise of e), and the pulse length is T+T3. If T3=T is selected, the pulse output becomes 2T, and the ringer (a) can be received without distortion, and even if distortion occurs, it can be suppressed to within ±T/2.

Furthermore, if the period T becomes shorter than T1 or T2, the pulse cannot be reproduced, so the ringer receiver circuit of this embodiment has high-frequency rejection characteristics.Furthermore, if the half period T/2 becomes longer than T1 or T2, Since pulse reproduction is not possible, this circuit exhibits low-frequency blocking characteristics, and when combined with the former, it has band-pass characteristics. The time T1 depends on the duty ratio of the signal (b) from the ringer detection circuit 1.
and DT2 are set, and when the duty ratio is 50%, it is appropriate to set T1=T2.

Furthermore, the pulse generator and NAND circuit in 1.2.3 above can be easily realized by combining commercially available monostable multivibrator integrated circuits.

〔Effect of the invention〕

As explained above, the present invention uses both the rising edge and the falling edge of the ringer detection circuit to start two pulse generating circuits, and uses the NAND circuit output of both pulse outputs to activate the third pulse generating circuit. By activating the ringer, it is possible to achieve low distortion bandpass characteristics for the ringer.
This has the effect of reducing reception distortion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of this embodiment. DESCRIPTION OF SYMBOLS 1... Ringer detection circuit, 2... 1st pulse generator, 3... 2nd pulse generator, 4... NAND circuit, 5... 3rd pulse generator.

Claims (1)

[Claims] a ringer detection circuit that compares the ringing signal with a preset threshold voltage and outputs a binary signal; and a ringer detection circuit that is activated at the rising and falling edges of the binary signal and has a pulse width shorter than the shortest period of the ringing signal. a first and second pulse generator that outputs a second signal; a NAND circuit that calculates and outputs the NAND logic value of the first and second signals; A ringer receiving circuit comprising: a third pulse generator that outputs a signal having a pulse width of time.