JPH0214620A - Variable length coding circuit - Google Patents

Abstract

PURPOSE:To facilitate the design of a variable length code by limiting the occurrence of zero run in a code string comprising outputted variable length codes. CONSTITUTION:A detection means 2 detects an equal length code A outputted from a delay register 1 and a final zero run length (n) of a variable length code corresponding to a final zero run length N, and a conversion means 4 outputs a variable length code B and a code length L of the variable length code B corresponding to the final zero run length N and the equal length code A. When the sum of the final zero run length N of the variable length code detected precedingly by the detection means 2 and a head zero run length of the present output variable length code exceeds a prescribed bit number, the conversion means 4 inserts '1' in the present output equal length code so that the sum of the final zero run length N and the head zero run length does not exceeds a prescribed bit number. Since the occurrence of the same code pattern (zero run of a prescribed bit number) as the synchronizing word in the outputted variable length code string is prevented, the code design is facilitated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a variable-length encoding circuit that converts equal-length codes into codes with different code lengths depending on the probability of occurrence of the same-length code, and particularly relates to a variable-length encoding circuit that converts equal-length codes into codes with different code lengths depending on the probability of occurrence of the same-length code, and particularly relates to a variable-length encoding circuit that converts equal-length codes into codes with different code lengths depending on the probability of occurrence of equal-length codes. By limiting the occurrence of zero runs in the code string created by
The present invention relates to a variable length encoding circuit that can improve encoding efficiency.

[Conventional technology]

Generally, variable-length encoded data cannot be decoded unless the delimiter rate of the rounding code is determined, the code length of which is not constant. Therefore, a synchronization word, which is a unique word that indicates the delimiter of the variable-length code, is added to the variable-length code string every certain period, and by detecting this synchronization word, the delimiter of the variable-length code can be determined. There is.

For this reason, in conventional variable length encoding circuits, the following restrictions have been placed on the variable length code pattern so that the same pattern as the synchronization word does not occur in the variable code string. For example, if the code of a synchronization word consisting of 9 bits is roooooooool J, all variable length codes must include one or more rlJ, and all combinations of variable length codes will have 8 "0"s. A restriction was added to the variable length code that it could not be more consecutive.

[Problem to be solved by the invention]

As mentioned above, in conventional variable-length encoding circuits, restrictions must be placed on the pattern of variable-length codes, which makes it difficult to design variable-length codes, and also reduces coding efficiency due to unusable codes. There was a problem that the value decreased.

[Means to solve the problem]

The variable length encoding circuit of the present invention includes a detection means for detecting the final zero run length of the variable length code to be output, and a detection means for detecting the final zero run length detected last time by the detection means and the current input equal length code. It includes a variable length code and a conversion means for outputting the code length of the variable length code. This conversion means converts the last zero run length N bits of the variable length code detected last time by the detection means and the leading zero run length Bo of the current output variable length code.
The sum of bits, that is, N+B (1 (N, Bo is a positive integer including 0) bits is a predetermined M (M is an integer greater than or equal to 2)
When the number of bits exceeds N+, the following measures are taken to
B6+1st bit M bit is not exceeded.

That is, this conversion means converts K' between the M-N bit and the M-N+1 bit from the beginning of the leading zero 2nd bit of the variable length code.
1" is inserted.

[Effect]

If the zero run length formed by the last zero run of the variable length code detected last time by the detection means and the leading zero run of the current output variable length code exceeds a predetermined number of bits, the converting means converts the value of the final zero run length and the leading zero run length. Correspondingly, "1" is inserted into the current output equal length code so that the sum of the final zero run length and the first zero run does not exceed a predetermined number of bits.

〔Example〕

Next, the present invention will be explained with reference to the drawings and tables.

The figure is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 1 denotes a delay register into which an equal-length code and a clock CLK synchronized with this equal-length code are input, and this equal-length code A is output after being delayed at an arbitrary timing synchronized with the clock CLK. 2 is a detection means, which is equal length code A output from delay register 1 and final zero run length N, which will be described later.
The final zero run length of the variable length code corresponding to K is detected based on the nft run length detection table 3. By the way, the final zero 2 length means the length of a run (continuous) of zeros including the final bit of this variable length code. Here, this final run length n is delayed by the time equivalent to one equal length code A in delay register 1, so from this delay register 1, the equal length code and the period before this equal length code (rima If the final length of the variable length code corresponding to the nine equal length codes inputted in the previous time is outputted at the same timing. Here, let this final run length be N. 4 is a conversion means which inputs the final run length N and the equal length code A, and converts the variable length code B based on the variable length code conversion table 5 in accordance with these.
The code lengths of the variable length code B are output based on the code length conversion table 6.

In addition, each of the above-mentioned nine conversion tables 3.5.8 is, for example, RO
This can be easily realized by M (R@ad 0aly M@mory) or the like.

Table 1 and Table 2 are each of the above conversion tables 3゜5.60
These two tables are designed based on the assumption that a 9-bit synchronization word, for example, 000000001J, as in the example, will be used. , does not occur in the variable length code string output from this variable length encoding circuit.

In Table 1, for example, when "23" is input as an equal length code person to this variable length code conversion circuit, the conversion means 4
A variable length code corresponding to the input equal length code r23JK is read from the variable length code conversion table 5. Thereafter, the conversion means 4 converts the final zero run of the variable length code corresponding to the previously input equal length code AK and the currently input equal length code "
The zero run length generated by the leading zero run of the variable length code corresponding to ``23'' and K, that is, the final zero run length N of the former.
If the sum of the leading zero run length of the latter exceeds the 7-bit limit, K "1" is inserted between the 7-Nth bit and the 8-Nth bit from the beginning of the latter variable-length code. If the sum does not exceed the limit of 7 bits, the latter variable length code is output as variable length code B as it is.

At the same time, the conversion means 4 reads out the code length of the variable length code B from the code length conversion table 6 and outputs it.

On the other hand, the detecting means 2 reads out the final digit r:I-) of the variable length code corresponding to the currently input equal length code "23" from the 2 length detection table 3 and outputs it to the delay register 1.

For example, if the variable length code corresponding to the previously input equal length code A is rollJ, then there are 8 bits: 0 bits b-000000010111 B-000000010111 L-12 bits n-0 bits. In this case, the zero-2 length (hereinafter simply referred to as zero-run length) between the last zero run of the previous variable-length code and the first zero run of the variable-length code read from the variable-length code conversion table 5 this time is O bits. The sum of 7 bits, that is, 7 bits, is rounded so that it does not exceed the limit of 7 bits, and the conversion means 4 does not insert "1" into the variable length code read from the variable length code conversion table 5 this time. , output as variable length code B as is.

Similarly, if the variable length code corresponding to the previously input equal length code A is ro 010J, then N = 1 bit b - 000000010111 B - 0000001010111 L = 13 bits n = 0 bit. The zero run length that occurs in this case is the sum of 1 pit and 7 bits, 8 bits, which exceeds the limit of 7 bits. Therefore, in order to prevent this zero run length from exceeding 7 bits, the first conversion means 4 converts the 7-1-6 bits from the beginning of the variable-length code read from the variable-length code conversion table 5 and the 8-1 7-bit bits. A "1" is inserted between the eyes and output as a variable length code B.

Similarly, if the variable length code corresponding to the previously input equal length code A is rooooolooJ, then N-2 bits b-000000010111 3 days 0000010010111 L-13 bits n and 0 bits. The zero run length that occurs in this case is the sum of 2 bits and 7 bits, or 9 pits, which exceeds the limit of 7 bits. Therefore, the converting means 4 inserts "1" between the 7-2-5th bit and the 8-2-6th bit from the beginning of the variable length code read this time and outputs it as a variable length code B.

As can be seen from the above explanation, the last zero run of the variable length code corresponding to the equal length code A input last time and the first zero run of the variable length code read from the variable length code conversion table 5 this time are formed. When the zero run length exceeds the limit of 7 bits) f, the conversion means 4 adds "1" to the first zero run of the variable length code so that "1" is located between the 7th and 8th bits of this zero run. " is inserted and output as variable length code B. For this reason, the number of zeros occurring in the code string of the variable length code B does not exceed the limit of 7 bits.

Note that here we have shown an example only when the final zero run length N of the variable length code corresponding to the previously input equal length code A is 0 to 2 pits, but even when N is 3 or 4 pits, the first
According to the table 5 above, the code length and final zero rough n f of the variable length code B1 can be determined.

The second table is composed of variable length codes of a different pattern from the first table, but is otherwise similar to the first table.

For example, if "8" is input as the equal length code A to this variable length code conversion circuit, the previous variable length code is [010
If it is J, N cabinet 1 bit b-oooo.

B biteoooo.

L-5 bits n=5 bits. The zero run length generated in this case is 1 pit + 5 bits - 6 bits, which does not exceed the limit of 7 bits, so the conversion means 4 does not insert "1" into this variable length code.

Similarly, if the previous variable length code was rooloooJ, then N■3 bits b■oooo.

B key 000010 L ■ 6 bits n = 1 bit. The zero run length that occurs in this case exceeds the shift bit limit of 3 bits + 5 bits - 8 bits. Therefore, in order to prevent the zero run length from exceeding 7 bits, the converting means 4 converts 7-3-
If KrlJ is inserted between the 4th bit and the 7th-2nd-5th bit and output as variable length code B, then the following is obtained.

As can be seen from the above explanation, as in the case of Table 1,
If the zero run length between the last zero run of the variable length code B output last time and the first zero run of the variable length code read from the variable length code conversion table 5 this time exceeds 7 bits, the converting means 4 converts the zero run between the two. ``1'' is inserted at the leading zero run of the variable length code so that rlJ is located between the 7th and 8th bits of 1.

Note that here, the final zero run length N of the previous variable length code B
Although only the cases where N is 1 and 5 bits are illustrated, even when N is other values, the code length and final zero run n of the variable length code B1 can be determined according to Table 2.

In addition, two types of variable length codes were explained as examples, but
By designing each table in the same manner as described above, it is possible to limit the zero/s in the variable length code string even in the case of other types of variable length codes.

, 4゜ [Effects of the Invention] As explained above, according to the variable length encoding circuit of the present invention, the final zero run of the variable length code output from this circuit and the variable length code output after that Since the length of the zero run caused by the leading zero run does not exceed a predetermined number of bits, the same code pattern as the synchronization word (zero run with a predetermined number of bits) is included in the variable length code string output from this circuit. can be prevented from occurring,
This makes code design easier as there is no need to consider every combination of codes as in the past, and there are fewer restrictions on the code patterns of variable-length codes that can be used, compared to the past. This has the effect of increasing encoding efficiency.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the variable length encoding circuit of the present invention. 1...delay register, 2...detection means, 3...
... Run length detection table, 4... Conversion means, 5...
...Variable length code conversion table, 6...Code length conversion table.

Claims (1)

[Scope of Claims] In a variable length encoding circuit that sequentially inputs equal length codes, converts them into variable length codes, and outputs the code length of the variable length codes, the final zero run length of the variable length code is detected. a detecting means; and a converting means for outputting a variable length code and its code length corresponding to the last zero run length and the current input equal length code detected by the detecting means; The final zero run length N (N is a positive integer including 0) bits of the variable length code detected last time by the detection means and the leading zero run length B_0 (B_0 is a positive integer including 0) bits of the current output variable length code. The sum, N+B_0 bits is the predetermined M(M
is an integer greater than or equal to 2) bits, the M-Nth bit from the beginning of the leading zero run of the variable-length code and the M-N+
A variable length encoding circuit characterized by inserting "1" between the first bits.