JPH02130646A - Abnormality detecting system for cpu - Google Patents

Abstract

PURPOSE:To attain the abnormality detection of a CPU not to be affected with the constitution of a program by requesting interruption to the CPU and checking an interruption permission signal when the CPU executes the abnormality detection. CONSTITUTION:An interruption requesting means 1 outputs an interruption requesting signal simultaneously with a counting means 2 and a system bus 7 to an arbitration circuit in a CPU 5. In the case of receiving the interruption requesting signal, the means 2 selects and receives the interruption permission signal outputted from the arbitration circuit to the bus 7. Further, the means 2 counts a time interval from the reception of the interruption requesting signal to the reception of the interruption permission signal, and the reception continuing time of the interruption permission signal. When respective counted values are in a set range set in advance, the interruption requesting signal is outputted again to the means 1 and when the counted values exceed the set range, an overflow signal is outputted to an abnormal signal output means 3. The means 3 outputs a failure signal showing that a failure is generated in the CPU 5.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention is applicable to microcomputer systems.
The present invention relates to an abnormality detection method for a PU (central processing unit).

B2 Summary of the Invention The present invention provides a method for detecting the CPU percentage of a microcomputer system by hardware, in which an interrupt request signal is cyclically output to the CPU, and a CI
Measure the time from when the arbitration circuit in UU receives this signal until it outputs a separate permission signal indicating acceptance of an interrupt to the system bus, and the duration of output of the same signal, and calculate the respective values. If the set range is exceeded, it is assumed that an abnormality has occurred inside the CPU, and an abnormality signal is output. This makes it possible to actively detect CPU abnormalities, and as a result, the microcomputer system It has become possible to provide a CPU abnormality detection method that is not affected by the system configuration and is highly versatile.

C0 Conventional technology Conventionally, as a CPU abnormality detection method, there are a program runaway detection method using software and a signal monitoring method using hardware to wait for redundancy. The fourth abnormality detection method
This will be explained based on the figure and FIG.

FIG. 4 is a diagram showing a program runaway detection method using software. In the figure, 5 is the CPU, 6 (1
) 6 (2) ... is various devices such as storage devices and input/output devices, 7 is the system bus, 8 and 9 (L)
9 (2) ... is system bus 7, CPU 5 and F
This is a bus that connects the J devices (1), 6, (2), and so on. Reference numeral 21 denotes a command circuit for instructing activation of a program runaway detection circuit, which will be described later. Reference numeral 22 denotes a program runaway detection circuit incorporating a watchdog timer (WDT) constituted by hardware.

Like this h! The operation of the software-based program runaway detection method will be described below. The software allows the CPU 5 to connect the system bus 7 and the signals w.
A start command is output to the command circuit 21 via &24 to start the runaway detection circuit 22. This is received by the command circuit 21
enables program runaway detection [IFl path 22]. As a result, the watchdog timer in the circuit 22 of the figure starts counting, but a reset program provided in the software causes the CPU 5 to program a reset signal via the system bus 7 and the signal line 23 at time intervals within a predetermined range. Since the signal is output to the runaway detection circuit 22, the watchdog timer in the circuit 22 is cyclically reset.

When an abnormality occurs in the CPU 5 and the reset signal is no longer output, the watchdog timer in the program runaway detection circuit 22 overflows, and the circuit outputs an abnormal signal from the signal line 26, indicating that the CPU 5 is abnormal.

However, such software-based CPU abnormality detection has the following problems. In other words, in order to detect a program runaway more quickly, a reset program for resetting the watchdog timer should be provided in program L with as short a cycle as possible, but software generally must be run with priority over the reset program. There are many programs that you must use. Is it technically possible to insert a reset program into such a program? l [This is not normally done because it would be sloppy. Therefore, the reset program provided on the program is inserted outside the frame of the priority program, and the interval at which the reset program is inserted onto the program cannot be made very short. As a result, the CPU abnormality detection cycle by software takes a considerably long time, and in extreme cases may take several tens of seconds. Also, if an eternal loop occurs in a part of the program that includes a reset program, the CP
Even though it is an abnormality of U, it becomes impossible to manifest it. Furthermore, there is also the problem that even if a hardware failure occurs, it cannot be detected.

As mentioned above, the program runaway detection method using software has various problems, but as a redundant means to compensate for these problems, the CPU signal monitoring method using the hardware configuration is generally used as the CPU abnormality detection method. It is often used in combination as A CPU signal monitoring system using a hardware configuration as such redundancy means will be described below.

Fig. 5 is a diagram explaining the CPU signal monitoring method using hardware. In this figure, the same parts as in Fig. I will omit it here.

Using software, the CPU 5 instructs the command circuit 32 to start abnormality detection via the system bus 7 and signal line 45. The command circuit 32 receives this and enables the abnormality detection counter circuit 33 via the signal line 46. ``j4 normal detection counter circuit 33 is thereby activated by clock generation circuit 35.
Counting of clock pulses outputted from the signal line 42 is started. When the CPU 5 is normal, a specific signal such as an address signal for accessing memory (hereinafter referred to as a monitor signal) is always outputted from the CPU 5 on the system bus 7 at least once within a certain period of time, but the monitor signal selection circuit 31 selectively receives this signal from the system bus 7 and signal line 43.

When this is received, it is converted into a reset signal and output to the abnormality detection counter circuit 33 via the signal line 44.

``A normal detection counter circuit 33 receives this signal and clears the cumulative value that has been counted up until now.A counter section (not shown) in the abnormality detection counter circuit 33 receives this signal from the CPU 5.
The overflow setting value corresponding to the time interval (meaning the fixed time mentioned above) at which the monitor signal is outputted to the system bus 7 is set. If the monitor signal is not received within the predetermined time (if an abnormality occurs in the CPU 5 and the monitor signal is not output within the predetermined time), the internal counter value exceeds this setting (a).

At this time, the circuit 33 outputs an overflow signal to the abnormal signal output circuit 34 via the signal line 47.

The abnormality signal output circuit 34 receives this overflow signal and outputs an abnormality signal indicating an abnormality of the CPU 5 from the signal line 48.

As explained above, in this method, a specific monitor signal output from the CP tJ to the system bus is always received by the hardware at a certain time, and if this signal is not received, an error occurs in the CPU. However, in this method, the time interval for the CPU to output a monitor signal to the system bus + 1111 times is quite short, so compared to the software-based program runaway detection method, the CPU outputs the monitor signal at a much faster time interval. It has the characteristic of being able to detect abnormalities. Another advantage is that failures caused by hardware can be detected at the same time.

D1 Problems to be Solved by the Invention However, the CPU signal monitoring method used as redundancy for the software-based program runaway detection method also has the following problems.

In other words, when this method is adopted for different systems, the time interval of the monitor signal output from the CPU will differ depending on the system, and even in the same system, the output of the monitor signal may vary depending on the program configuration. In some cases, the time interval between the two times is not constant. For this reason,
When setting the overflow set value in the abnormality detection counter circuit 33, there is a problem in that a certain amount of leeway must be allowed in order to adapt to various systems and to take into account differences due to program configurations. In other words, this cannot be said to be a versatile method for quickly discovering CPU abnormalities. A more fundamental problem is that this method cannot be used in systems where the CPU rarely accesses the system bus.

This invention was made in view of the above, and its purpose is to improve the CPU of a microcomputer system.
The present invention provides a highly versatile CPU abnormality detection method that does not care about differences in software program configurations or differences in system configurations of microcomputer systems.

E. Means for Solving the Problems FIG. 1 is a block diagram for explaining the present invention, and the present invention will be explained in detail below based on the same figure.

CPU5. System bus 7, peripheral devices 16 (1) to 6
A microcomputer system consisting of (n) is provided with a CPU abnormality detection device 10 comprising an interrupt requesting means 1, a counting means 2, and an abnormality signal outputting means 3,
The interrupt request means] simultaneously outputs an interrupt request signal to the 7-bit transmission circuit in the CPU 5 via the counting means 2 and the system bus 7, and receives this interrupt request signal to interrupt the arbitration circuit in the CPU 5. The counting means 2 selectively receives the interrupt permission signal outputted from the system bus 7 to the system bus 7, and furthermore, the counting means 2 calculates the time interval from reception of the interrupt request signal to reception of the interrupt permission signal and the reception duration of the interruption permission signal. is measured, and if each measured value is within a preset setting range, the interrupt request means 1 is made to output a training request signal again, and if the measured value exceeds the set range, an overflow signal is output as an abnormal signal. The signal is output to the means 3, and the same hand yi3 receives this signal.
It is configured to output a failure signal indicating that a failure has occurred within the PU or in the hardware configuration.

21 Operation The counting means 2 according to the present invention measures the time interval from when the arbitration circuit of the CPU receives the interrupt request signal until it outputs the interrupt permission signal and the output duration time of the interrupt permission signal. If these measured values exceed the set range, it is determined that an abnormality has occurred in c p ty or the hardware configuration, and an overflow signal is output.

G. Embodiment An embodiment of the present invention will be described below with reference to FIG. still,
In the figure, the same parts as those in the prior art are given the same reference numerals, but since detailed explanations have already been given, detailed explanations are omitted here.

In the figure, 11 is a timer circuit that determines the output cycle of the interrupt request signal, 12 is a timer circuit that measures the time from when the interrupt request signal is output to the CPU until the CPU outputs the interrupt permission signal, and 13 is a timer circuit that measures the time from when the interrupt request signal is output to the CPU until the CPU outputs the interrupt permission signal. a timer circuit that measures the output duration of the interrupt permission signal output from the CPU;
14 is an interrupt request circuit that outputs an interrupt request signal to the CPU in response to a command from the timer circuit 11; 15 is a monitor signal receiving circuit that selectively receives an interrupt permission signal output from the arbitration circuit in the CRU 5 from the system bus 7; , 16 is a command circuit for instructing the activation of the above-mentioned timer circuits 11, 12, and 13, and 17 is an abnormal signal output circuit which receives overflow signals output from the above-mentioned timer circuits 12 and 13 and thereby outputs an abnormal signal. Go outside. The CPU abnormality detection device 10 uses the various circuits 11 to 17 described above.
is configured. In the figure, the interrupt request circuit 14 and the timer circuit 11 constitute the interrupt request means 1 shown in FIG. The abnormal signal output circuit 17 is the abnormal signal output means 3 shown in FIG.

Next, the operation of this embodiment will be explained below along with the time chart shown in FIG.

Timer circuit 11.12.13 by initial setting signal (a)
, an initial Ua determination suitable for the system is performed for each of the abnormality detection circuits 17. With this setting, the cycle for outputting an interrupt request signal to the CPU is set for the timer circuit 11, and the cycle for outputting an interrupt request signal to the CPU is set for the timer circuits 12 and 13.
A time limit is set for determining whether or not the abnormality signal output circuit 17 operates normally, and the abnormality signal output circuit 17 is reset.

Next, when the software starts the system and requests the hardware to monitor the CPU for abnormalities, the
The PU 5 outputs an activation start signal (a) to the command circuit 16 via the system bus 7 in order to operate the abnormality detection device 10. When the command circuit 16 receives this signal, it outputs an enable signal (two) to the timer circuits 11 to 13 to enable each timer circuit. The timer circuit 11 should start counting as soon as it is enabled (A in figure W3).
When the time-up reaches the set time, a time-up signal (1) is output to the shoulder request circuit 14 and the timer circuit 12 (B) in FIG. 3, and the count is reset. When the interrupt request circuit 14 receives this signal, it outputs an interrupt request signal (O) to the CPU via the system bus 7 (C in FIG. 3), and when the timer circuit 12 receives this signal, it starts counting ( D in Figure 3). When the CPU 5 is operating normally, the arbitration circuit within the CPU receives an interrupt request signal (O) from the system bus 7 and outputs a separate permission signal (power) to the system bus 7 after a certain period of time. (E in Figure 3). The monitor signal receiving circuit 15 selectively receives this interrupt permission signal from the system bus 7, and when received, outputs a set/reset signal (K) to the timer circuits 12 and 13 during the receiving period (see FIG. 3). F) When the timer circuit 12 receives this signal (K), it is reset (G in Figure 3), but if the count amount of the circuit exceeds the initially set time limit (
To the CPU! (This means that the interrupt permission signal from the 7-bit transmission circuit in the same CPU is not output within a certain period of time), the abnormal signal output circuit 17
Outputs an overflow signal (ke) to the Timer circuit 13
starts counting when it receives the set/reset signal (K) (H in Figure 3), and stops counting when the reception is interrupted (■ in Figure 3), but the time limit set initially by Callan +-t is If it exceeds the limit (meaning that an abnormality occurs in the CPU and the time it takes for the arbitration circuit of the CPU to output an interrupt permission signal becomes abnormally long), an overflow signal (co) is sent to the abnormal signal output circuit 17. However, if the counted amount is within the initially set time limit, a start command (RI) is output to restart the timer circuit 11 (J in Figure 3). ) is restarted, and a series of operations similar to those described above are performed cyclically. On the other hand, the abnormal signal output circuit 17 outputs the above-mentioned overflow signal (k) or (c).
is received, an abnormality signal corresponding to the external system is sent to notify the external WN circuit or external system that an abnormality has occurred in the CPU of this system.
Output. Through the above-described operation and action, abnormalities in the CPU can be actively detected.

H1 Effects of the Invention As described above, according to the present invention, when detecting an abnormality in the cPU of a microcomputer system by hardware, a system is adopted in which an interrupt is requested to the CPU and an interrupt permission signal from the CPU is checked. It has become possible to actively detect abnormalities in the CPU, and as a result, it has become possible to provide a CPU abnormality detection method that is not influenced by the system configuration of the microcomputer system or by the program configuration. Furthermore, this method
Since we focused on checking the operation of the 7-bit transmission circuit of the CPU, we have the advantage that the detection rate of CPU abnormalities is extremely high and that no special interrupt processing program is required.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram for explaining the present invention in detail. Second
The figure is a hardware configuration diagram showing an embodiment of the present invention. ! f
Figure f3 is a time chart diagram for explaining the embodiment of Figure 2, and Figures 1 and 4 are block diagrams showing a program runaway detection method using software in the prior art. FIG. 5 is a block diagram showing a conventional hardware-based CPU signal monitoring system. 1... Interrupt request means 2... Counting means 3... Abnormality detection means 5... CPU 7... System bus Figure 1 Figure Figure

Claims (1)

[Claims] In an abnormality detection method for a CPU (central processing unit) in a microcomputer system, the system is provided with an abnormality detection device having an interrupt request means, a counting means, and an abnormal signal output means, and the interrupt request means is connected to the CPU.
The counting means outputs an interrupt request signal to U and a counting means, and the counting means receives an interrupt permission signal to be output to the system bus when the arbitration circuit in the CPU receives the interrupt request signal. The time interval from the reception of the interrupt request signal to the reception of the interrupt permission signal and the reception time of the interrupt permission signal are measured, and if each measured value of the coefficient means exceeds a preset setting range, an overflow signal is generated. Output to the abnormal signal output means,
By receiving this signal, the abnormality signal output means
An abnormality detection method for a CPU, characterized in that an abnormality signal indicating that a failure has occurred in a CPU is output.