JPH0213024A - Switching circuit - Google Patents

Switching circuit

Info

Publication number
JPH0213024A
JPH0213024A JP16106388A JP16106388A JPH0213024A JP H0213024 A JPH0213024 A JP H0213024A JP 16106388 A JP16106388 A JP 16106388A JP 16106388 A JP16106388 A JP 16106388A JP H0213024 A JPH0213024 A JP H0213024A
Authority
JP
Japan
Prior art keywords
circuit
alm
panel
standby
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16106388A
Other languages
Japanese (ja)
Other versions
JPH0728239B2 (en
Inventor
Takayuki Anamoto
隆幸 穴本
Kenji Shidara
設楽 堅次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63161063A priority Critical patent/JPH0728239B2/en
Publication of JPH0213024A publication Critical patent/JPH0213024A/en
Publication of JPH0728239B2 publication Critical patent/JPH0728239B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To prevent a phenomenon that an operation system is successively moved alternately between both panels by providing the output part of a lock signal to stop a switching to a switching circuit to automatically switch the panel of a standby system to the operation system when a trouble is generated to the panel to compose the operation system. CONSTITUTION:When an ALM is not generated to a circuit 2 and the ALM is generated to a circuit 1, the circuit 1 and circuit 2 are switched to the standby system and operation system, respectively. When the circuit 1 is the standby and the ALM is generated and when the circuit 2 is the operation system and the ALM is generated, the phenomenon that the operation system is alternately moved between the circuit 1 and circuit 2 is generated, and when a lock is applied, namely, at the time of a lock signal l7=0, an l5 (l6) is not influenced. Consequently, even when the ALMs are generated to both systems, by applying the lock signal from an external part, the phenomenon that the operation system is alternately moved between the circuit 1 and circuit 2 can be prevented.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、切替回路に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to a switching circuit.

特に、装置のパネルが、現用、予備構成となっていて、
これらのパネルを互いに切替可能とする切替回路に関す
るものである。
In particular, if the equipment panel is in active and backup configurations,
The present invention relates to a switching circuit that enables switching between these panels.

[従来の技術] 従来の切替回路は、運用系および待機系を構成する2つ
のパネルのうち、運用系をなすパネルに障害が発生した
とき、待機系のパネルに障害が発生していなければ、無
条件で自動的に待機系のパネルを運用系に切り替えるよ
うになっていた。
[Prior Art] In a conventional switching circuit, when a failure occurs in the active panel among the two panels that constitute the active system and the standby system, if the failure does not occur in the standby system panel, The standby panel was automatically switched to the active panel without any conditions.

[解決すべき課題] 上述した従来の切替回路では、待機系のパネルに障害発
生かなく、運用系のパネルに障害か発生した場合、待機
系への切替がなされ、待機系が運用系に、運用系が待機
系となる。
[Problems to be Solved] In the conventional switching circuit described above, if no failure occurs in the standby panel but a failure occurs in the active panel, switching to the standby system is performed, and the standby system becomes the active system. The active system becomes the standby system.

ところか、待機系となったパネルは、リセットされるの
で、一定期間「障害なし」と判定される。
However, since a panel that becomes a standby system is reset, it is determined that there is no failure for a certain period of time.

そして、この期間に再び運用系側て障害が発生すると、
従来の切替回路では自動的に切り替え動作がなされるた
め、結果として運用系が両パネル間を交互に連続して移
動してしまうという問題点かあった。
If a failure occurs again on the operational system during this period,
Since the conventional switching circuit performs the switching operation automatically, there is a problem in that the active system moves alternately and continuously between the two panels.

本発明は上記の問題点にかんがみてなされたもので、運
用系のパネルおよび待機系のパネルに障害が発生した場
合ても、運用系か両パネル間を交互に連続して移動しな
いように、外部からロックをかけることのできる切替回
路の提供を目的とする。
The present invention was made in view of the above problems, and even if a failure occurs in the active panel and the standby panel, it is possible to prevent the active panel from moving alternately and continuously between the two panels. The purpose is to provide a switching circuit that can be locked from the outside.

[課題の解決手段] 上記目的を達成するために本発明は、運用系および待機
系を構成する2つの同一のパネルを備え、これらパネル
のうち運用系をなすパネルに障害か発生したとき、自動
的に待機系のパネルを運用系に切り替える切替回路にお
いて、前記切替を停止させるロック信号の出力部を備え
た構成としである。
[Means for Solving the Problems] In order to achieve the above object, the present invention includes two identical panels constituting an active system and a standby system, and when a failure occurs in the panel constituting the active system among these panels, automatic The switching circuit for switching from a standby panel to an active panel is configured to include an output section for outputting a lock signal to stop the switching.

[実施例] 以下1本発明の一実施例について図面を参照して説明す
る。
[Example] An example of the present invention will be described below with reference to the drawings.

第1図は、実施例のブロック図である。FIG. 1 is a block diagram of an embodiment.

同図において、制御装置は、現用、予備構成となってお
り、lかN系回路、2かE糸回路である。これらの回路
1および2は、まったく同一のパネルである。したかっ
て、どちらが現用となり、予備となっても問題は生じな
い。
In the figure, the control device has a current and a standby configuration, and has an 1 or N system circuit and a 2 or E thread circuit. These circuits 1 and 2 are one and the same panel. Therefore, it does not matter which one is in use and which one is in reserve.

3および4はNAND回路である。これらNAND回路
3および4は、パネルに後述するロックかかかっていな
い場合には、パネルの障害発生(以下、ALMという)
、復旧を伝達するが、口・ンクがかかっている場合には
、パネルのALM状態とは無関係にhigh出力(rl
J)を伝達する。
3 and 4 are NAND circuits. These NAND circuits 3 and 4 will cause a panel failure (hereinafter referred to as ALM) if the panel is not locked (described later).
, recovery is transmitted, but if there is a talk/link, the high output (rl
J) to communicate.

5および6は、前記NAND回路3および4の出力を入
力するNAND回路である。これらNAND回路5およ
び6は、後述するように、互いに相手パネルの現用、待
機状態信号を受は取り、自分のパネルのALMの有無に
応して、現用または待機系になる信号を出力する。
5 and 6 are NAND circuits into which the outputs of the NAND circuits 3 and 4 are input. These NAND circuits 5 and 6, as will be described later, receive and receive active and standby state signals from the other panel, and output signals that indicate whether the panel is in active or standby mode depending on the presence or absence of ALM in its own panel.

1、はN系回路1のALM信号である。この信号文、は
、N系回路1て発生したALMかある場合rlJ (h
igh)てあり、ALMがない場合「0」である。
1 is the ALM signal of the N-system circuit 1. This signal statement is rlJ (h
(high) and is “0” if there is no ALM.

12はE糸回路2のALM信号である。この信号交2は
、前記信号又、と同様、E糸回路2て発生したALMが
ある場合rlJ (high)であり、ALMかない場
合「0」である。
12 is an ALM signal of the E thread circuit 2. This signal intersection 2 is rlJ (high) when there is an ALM generated in the E thread circuit 2, and is "0" when there is no ALM, similar to the above-mentioned signal 2.

lxはN糸回路lのACT用入力信号てあり、前記NA
ND回路3から出力される。
lx is the input signal for ACT of the N yarn circuit l, and the NA
It is output from the ND circuit 3.

旦、はE糸回路2のACT用入力信号であり、前記NA
ND回路4から出力される。
DA is the input signal for ACT of the E yarn circuit 2, and the NA
It is output from the ND circuit 4.

isは前記NAND回路5から出力されるN糸回路lの
ACT信号1文、は前記NAND回路6から出力される
E糸回路2のACT信号である。これらACT信号(文
、または文、)が「0」のとき1回路(N糸回路lまた
はE糸回路2)が運用系となり、「1」のとき、待機系
となる。これらACT信号13.fL6は、互いに相手
回路のNAND回路6,5に接続されており、切替判断
の信号であると同時に、自パネルの運用、待機状態を示
す信号となっている。
is is the ACT signal of the N thread circuit 1 outputted from the NAND circuit 5, and is the ACT signal of the E thread circuit 2 outputted from the NAND circuit 6. When these ACT signals (sentences or sentences) are "0", one circuit (N thread circuit 1 or E thread circuit 2) becomes the active system, and when it is "1", it becomes the standby system. These ACT signals 13. fL6 is connected to the NAND circuits 6 and 5 of the other circuits, and serves as a signal for determining switching and at the same time as a signal indicating the operation or standby state of the own panel.

文、は、現用、待機系の切り替えをストップさせるため
のロック信号てあり、図示せざる出力部より出力される
。このロック信号文、か「1」のときに切り替えが可能
であり、「0」のときに切替停止となる。また、このロ
ック信号文、がrlJて、かつ前記ALM信号(立、ま
たは文2)かO/1のとき、前記ACT用入力信号(1
ffまたは!14)か110となる。
Statement 2 is a lock signal for stopping switching between the active system and the standby system, and is output from an output section (not shown). Switching is possible when this lock signal is "1", and switching is stopped when it is "0". Further, when this lock signal statement is rlJ and the ALM signal (standing or statement 2) is O/1, the ACT input signal (1
ff or! 14) or 110.

以下、全体の動作について順次説明する。The overall operation will be sequentially explained below.

先ず、ロックがかかっていない場合、すなわちロック信
号1y=1の場合について説明する。
First, the case where the lock is not applied, that is, the case where the lock signal 1y=1 will be explained.

回路1において、ALMがない場合、 旦、=0で、又7;1であるから、交コ=1となり、!
2.6=1のとき、立s=oとなる。
In circuit 1, if there is no ALM, then = 0 and 7 = 1, so AC = 1, and !
2. When 6=1, standing s=o.

したかって、回路lは運用系に、回路2は待機系となる
Therefore, the circuit 1 becomes the active system, and the circuit 2 becomes the standby system.

ここて1回路2にALMかなく(J12=Oにより立a
 = 1 ) 、回路1にALMか発生したとすると、
i、y=1.かつ文、=1となるのて、見。
Here, there is no ALM in 1 circuit 2 (J12=O makes it stand a
= 1), and if ALM occurs in circuit 1, then
i, y=1. And the sentence becomes =1, see.

=0となる。そして、1s=1であるのて、文。=0. And since 1s=1, the sentence.

は「1」となる。したかって、回路2においては、文、
=1で文、=1となるので、文、=0となる。これによ
って、回路1が待機系へ、回路2か運用系へと切り替わ
る。
becomes "1". Therefore, in circuit 2, the statement,
Since =1 makes the sentence =1, the sentence =0. As a result, circuit 1 is switched to the standby system, and circuit 2 is switched to the active system.

次ぎに、運用系か1回路1と回路2との間で交互に変化
する場合について説明する。
Next, a case where the active system changes alternately between circuit 1 and circuit 2 will be explained.

回路lか待機(文、=1)でALM発生、回路2か運用
系でALMなしとする。このとき、回路工はALM発生
で回路がリセットされるため、定時間ALMなしB、=
o)とされる。
Assume that ALM occurs when circuit 1 is on standby (statement, = 1), and there is no ALM when circuit 2 is active. At this time, the circuit engineer will reset the circuit when ALM occurs, so there will be no ALM for a fixed period of time B, =
o).

ここで、回路2側てもALMか発生したとすると、 回路2ては、旦2−1、立、=1なので文。Here, if ALM occurs on the circuit 2 side as well, Circuit 2 is dan 2-1, standing, = 1, so it is a sentence.

=0、そして文、=1であるから、n a = 1とな
って、回路2は待機系へと変化する。
Since n = 0 and statement = 1, n a = 1, and circuit 2 changes to a standby system.

逆に回路1では、文、二〇、u、=1なので交互=1、
そしてl s = 1であるから、文、=0となって、
回路1は運用系へと変化する。
Conversely, in circuit 1, since sentence, 20, u, = 1, alternating = 1,
And since l s = 1, the sentence = 0,
Circuit 1 changes to the operational system.

ところか、回路lか再びALMを検出すると、回路2は
ALM発生のためにリセットされて一定時間ALMなし
となっているので、上記と同様にして、回路lが待機系
へ1回路2が運用系へと変化することとなる。
However, when circuit 1 detects ALM again, circuit 2 is reset due to the occurrence of ALM and there is no ALM for a certain period of time, so in the same way as above, circuit 1 is switched to the standby system and circuit 1 is switched to the operating system. It will change into a system.

このようにして1回路lと回路2とにALMが発生した
場合、運用系が、回路lと回路2との間て交互に移動す
るという現象が発生する。
When ALM occurs in circuit 1 and circuit 2 in this way, a phenomenon occurs in which the active system moves alternately between circuit 1 and circuit 2.

次ぎに、ロックをかけた場合、すなわちロック信号文、
=0の場合について説明する。
Next, when a lock is applied, that is, a lock signal statement,
The case where =0 will be explained.

例えば、回路1かALMなしく文、=0)て、運用系(
文、=Q)、回路2か待機系(立。
For example, if there is no circuit 1 or ALM, the statement = 0), and the operation system (
Sentence, = Q), circuit 2 or standby system (stand.

=1)であるとすると、 立、二〇、文、=oなので、立3=1であり、u、=l
であるから、文、二〇である。
= 1), then tate, 20, sentence, = o, so tate 3 = 1, and u, = l
Therefore, the sentence is 20.

ここて、回路1にALMか発生したとすると、交、=1
となるか、文、=0であるので、13 = 1のままて
あり、Is  C1s )には影響か及ばない。
Here, if ALM occurs in circuit 1, then cross = 1
Since the sentence = 0, 13 = 1 remains and has no effect on Is C1s ).

したかって、仮りに両系にALMか発生したとしても、
外部よりロック信号をかけることにより、運用系が回路
lと回路2との間で交互に移動するのを防止することが
できる。
Even if ALM occurs in both systems,
By applying a lock signal from the outside, it is possible to prevent the active system from moving alternately between circuit 1 and circuit 2.

[発明の効果] 以上説明したように本発明は、運用系のパネルおよび待
機系のパネルに障害か発生した場合でも、両系の状態を
ロックさせるロック信号を設けであるので、運用系か両
パネル間を交互に連続して移動するという現象を防止す
ることかできる。
[Effects of the Invention] As explained above, the present invention provides a lock signal that locks the status of both systems even if a failure occurs in the active panel and the standby panel. It is possible to prevent the phenomenon of continuous alternating movement between panels.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、 本発明の一実施例のツロ・ツク図であ る。 :パネル 文、:ロック信号 Figure 1 shows FIG. 2 is a diagram of one embodiment of the present invention. Ru. :panel Sentence: lock signal

Claims (1)

【特許請求の範囲】[Claims] 運用系および待機系を構成する2つの同一のパネルを備
え、これらパネルのうち運用系をなすパネルに障害が発
生したとき、自動的に待機系のパネルを運用系に切り替
える切替回路において、前記切替を停止させるロック信
号の出力部を備えたことを特徴とする切替回路。
In a switching circuit that includes two identical panels forming an active system and a standby system, and automatically switches the standby panel to the active system when a failure occurs in the panel forming the active system among these panels, the switching circuit A switching circuit characterized by comprising an output section for a lock signal that stops the switching circuit.
JP63161063A 1988-06-30 1988-06-30 Switching circuit Expired - Fee Related JPH0728239B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63161063A JPH0728239B2 (en) 1988-06-30 1988-06-30 Switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63161063A JPH0728239B2 (en) 1988-06-30 1988-06-30 Switching circuit

Publications (2)

Publication Number Publication Date
JPH0213024A true JPH0213024A (en) 1990-01-17
JPH0728239B2 JPH0728239B2 (en) 1995-03-29

Family

ID=15727908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63161063A Expired - Fee Related JPH0728239B2 (en) 1988-06-30 1988-06-30 Switching circuit

Country Status (1)

Country Link
JP (1) JPH0728239B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809402A (en) * 1992-10-07 1998-09-15 The Boeing Company ACARS/VHF transceiver interface unit (AVIU)
US5920807A (en) * 1992-11-13 1999-07-06 The Boeing Company ACARS/VHF transceiver interface unit (AVIU)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123532A (en) * 1987-11-09 1989-05-16 Hitachi Ltd Line automatic switching device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123532A (en) * 1987-11-09 1989-05-16 Hitachi Ltd Line automatic switching device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809402A (en) * 1992-10-07 1998-09-15 The Boeing Company ACARS/VHF transceiver interface unit (AVIU)
US5920807A (en) * 1992-11-13 1999-07-06 The Boeing Company ACARS/VHF transceiver interface unit (AVIU)

Also Published As

Publication number Publication date
JPH0728239B2 (en) 1995-03-29

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