JPH0212957A - Electronic apparatus - Google Patents

Abstract

PURPOSE:To prevent an electronic apparatus from erroneously operating and to improve electric reliability by providing first wirings linearly, and second wirings nonlinearly or smaller in width or thickness of the wirings than that of the first wirings in the apparatus which places a ZIP type semiconductor device. CONSTITUTION:A ZIP type semiconductor memory 2 connected to wirings 3, 4 is placed on an intersection between wirings 3 and 4 extending in different directions on a printed circuit board 1. The wirings 3 extending in columnar direction are composed linearly, and the wirings 4 extending in row direction are composed nonlinearly. Accordingly, the difference between the characteristic impedances of the transmission lines of the wirings 3 and 4 upon specific shape of the memory 2 is reduced, and the difference of voltage reflection coefficients of both is decreased. Thus, the phase difference of the signals to be transmitted to the wirings 3, 4 is reduced, thereby preventing the writing or reading of information from erroneously operating.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device, and particularly to a technique that is effective when applied to an electronic device in which a plurality of semiconductor devices are mounted on a wiring board.

[Conventional technology]

2. Description of the Related Art A so-called memory board, in which a plurality of semiconductor storage devices are mounted on a printed wiring board, is used as a storage device (electronic device) for an electronic computer. These storage devices are becoming larger in capacity, and the number of semiconductor storage devices mounted per unit area on a printed wiring board is increasing (the packaging density is increasing).

The storage device currently being developed by the inventor is a Z
I P (Zigzag In-1ine Pack
Equipped with a 1.5-age) type semiconductor memory device. This ZIP
The type semiconductor memory device is DRAM (Dynamic Random
It has a built-in dom Access Memory. In a ZIP type semiconductor memory device, outer leads are arranged in a zigzag pattern along one long side. Therefore, Z
An IP type semiconductor memory device is a DIP (Dual I
n-1ine Package) type semiconductor memory device,
The device can be mounted vertically, and although the height on the printed wiring board is increased, the area occupied can be reduced, and the packaging density can be improved.

The ZIP type semiconductor memory device has an electrical connection between the plurality of column direction wirings extending in the column direction and the plurality of row direction wirings extending in the row direction on the printed wiring board at the intersections of the respective wirings. Multiple units are connected and installed. Each of the column direction wiring and the row direction wiring is electrically connected to a driver semiconductor device that drives the ZIP type semiconductor memory device and a receiver semiconductor device that reads information. A ZIP type semiconductor memory device is mounted so that the longitudinal direction (the direction in which the outer leads are arranged) is parallel to the column wiring, and the width direction (actually, the thickness direction) is parallel to the row wiring.

In the ZIP type semiconductor memory device, the outer leads are arranged in a zigzag pattern as described above, and since there are no outer leads in the same row direction, the wiring in one row direction is made to extend in a straight line. On the other hand, the wiring in the first column direction extends in a straight line between the ZIP type semiconductor memory devices.

In this way, by extending each of the column direction wiring and row direction wiring extending in a straight line on the printed wiring board, it is possible to reduce the area occupied by the wiring and improve the packaging density, and also to improve the frequency characteristics. can be improved.

Note that this type of storage device (electronic device) is described in, for example, Japanese Utility Model Publication No. 15500/1983.

[Problem to be solved by the invention]

The above-mentioned ZIP type semiconductor memory device has a unique elongated structure with a dimension in the width direction as small as about one-tenth of the dimension in the longitudinal direction. This unique structure of ZIP
When column-direction wiring and row-direction wiring extend in straight lines on a printed wiring board based on a type semiconductor memory device, the wiring length of the row-direction wiring becomes extremely short compared to the wiring length of the column-direction wiring.

Therefore, the transmission line characteristic impedance of the column direction wiring and the row direction wiring are different, and the voltage reflection coefficients are different. This difference in voltage reflection coefficient causes a phase difference in the signals between the column wiring and the row wiring, and the driver semiconductor device connected to the column wiring and the driver semiconductor device connected to the row wiring. Differences occur in the operation timing between the two. The inventors of the present invention have found that this causes erroneous writing or reading of information, resulting in deterioration of the electrical reliability of the storage device.

An object of the present invention is to provide a technique that can prevent malfunctions and improve electrical reliability in an electronic device in which a ZIP type semiconductor device is mounted on a wiring board.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

A first wiring and a second wiring extending in different directions on the wiring board.
In an electronic device in which a ZIP type semiconductor device connected to each wiring is mounted at an intersection with the wiring, the first wiring is configured as a straight line, and the second wiring is configured as a non-straight line or as compared to the first wiring. The wiring width or thickness is made small.

[For production]

According to the above-described means, the difference between the transmission path characteristic impedance of the first wiring and the transmission path characteristic impedance of the second wiring due to the unique shape of the ZIP type semiconductor device is reduced, and the voltage reflection coefficient difference between the two is reduced. Since the reduction has been made, the first wiring, the second
It is possible to reduce the phase difference between signals transmitted to each wiring, thereby preventing malfunctions of the electronic device. As a result, the electrical reliability of the electronic device can be improved.

Below, regarding the configuration of the present invention, Z
An embodiment in which the present invention is applied to a mass storage device (electronic device) equipped with an IP type semiconductor memory device (DRAM) will be described.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 1 (plan view) shows a schematic configuration of a mass storage device (electronic device) that is an embodiment of the present invention.

As shown in FIG. 1, the mass storage device is provided with a memory area MA, logic areas XLA and YLA on a printed wiring board 1.

The printed wiring board 1 is formed of an insulating substrate made of glass epoxy resin, for example.

This printed wiring board 1 has a plurality of wiring layers formed thereon. For example, printed wiring board 1 currently being developed by the present inventor.
In this case, a single wiring layer used as signal wiring and power supply wiring is formed on the front side (mounting surface), and a six-layer wiring layer used as signal wiring and power supply wiring is formed on the back side. This printed wiring board 1 is configured so that it can be incorporated into an electronic computer or the like (not shown) as a mass storage device.

In the memory area MA of this printed wiring board 1, a plurality of ZIP type semiconductor memory devices 2 are mounted (mounted) in a matrix.
has been done. In the ZIP type semiconductor memory device 2, as shown in FIG. 2 (side view) and FIG. 3 (bottom view), a semiconductor chip (not shown) is sealed (resin molded) with a resin sealing portion 2A. As shown in FIG. 2, the ZIP type semiconductor memory device 2 has a longitudinal dimension of, for example, 25 to 26 m.
m], and the dimension H in the height direction is, for example, 8 to 9 [mm].

Further, as shown in FIG. 3, the ZIP type semiconductor memory device 2 has a dimension W in the width direction of, for example, 2.5 to 2.6 mm. In this ZIP type semiconductor memory device 2, outer leads 2B protrude from one end of the resin sealing portion 2A, and a plurality of outer leads 2B are arranged in a zigzag pattern along the longitudinal direction.

The ZIP type semiconductor memory device 2 incorporates a DRAM having a large capacity of, for example, 1 Mbitl. Outer lead 2 of ZIP type semiconductor storage device 2 incorporating this DRAM
A predetermined signal is applied to B as shown in FIGS. 2 and 3. AO-A9 is an address signal. CAS is a column address strobe signal. D out is a data output signal, and Din is a data input signal. Vss is a reference voltage, and Vcc is a power supply voltage. RAS is a row address strobe signal. WE is a read/write input signal. NC is a vacant pin.

The ZIP type semiconductor storage device 2 constitutes a byte machine, so for example, as shown in FIG.
There are 8 pieces arranged in the column direction and 8 pieces arranged in the row direction, for a total of 64 pieces. The memory area MA in which the ZIP type semiconductor memory devices 2 are arranged in this way is long in the column direction because the lengthwise dimension of the ZIP type semiconductor memory devices 2 is larger than the widthwise dimension W as described above. It is composed of a rectangular shape.

In the memory area MA of the printed wiring board 1, a plurality of wiring lines 3 extending in the column direction and arranged in the row direction are provided along the ZIP type semiconductor memory devices 2 arranged in the column direction. This wiring 3 is electrically connected to the ZIP type semiconductor memory device 2, and is also connected to the right side (
It is electrically connected to the DIP type semiconductor device 5 in the logic area XLA provided on the short side). This DIP type semiconductor device 5 mainly consists of Z
It is configured to drive the IP type semiconductor memory device 2 and to write and read information.

On the other hand, in the memory area MA, a plurality of interconnections 4 extending in the row direction and arranged in the column direction are provided along the ZIP type semiconductor memory devices 2 arranged in the row direction. This wiring 4 is electrically connected to the ZIP type semiconductor memory device 2, and is also electrically connected to the DIP type semiconductor device 6 in the logic area YLA provided on the lower side (long side) of the memory area MA. There is. The DIP type semiconductor device 6 is configured to mainly drive the ZIP type semiconductor memory devices 2 arranged in the memory area MA, and also to write and read information. The wiring 4 is composed of a wiring layer different from that of the wiring 3.

As shown in FIG. 1, the ZIP type semiconductor memory device 2 has a unique structure in which the dimension in the longitudinal direction is long. Therefore, the wiring 3 extending in the column direction in the memory area MA on the printed wiring board 1 is The wires are configured to extend substantially in a straight line to minimize wire length.

On the other hand, the ZIP type semiconductor memory device 2 has a widthwise dimension W of D.
Since it has a unique structure that is extremely short compared to that of the IP type semiconductor devices 5 and 6, the wiring 4 extending in the row direction of the memory area MA has a wiring length equal to that of the wiring 3 extending in the column direction.
It is configured to extend non-linearly so that it is equal to . Originally.

Since the outer leads 2B of the ZIP type semiconductor memory device 2 are arranged in a zigzag pattern, the wirings extending in the row direction are made to extend in straight lines. However, in the present invention, the wirings 4 extending in the row direction are It extends non-linearly. The wiring 4 of this embodiment is connected to a predetermined outer lead 2B of the ZIP type semiconductor memory device 2, and is partially bent in the column direction within a range that does not short-circuit with other adjacent wiring 4 extending in the row direction. It is extended by a broken line. Further, the wiring 4 is not limited to a broken line, but may be a curved line extending in the row direction while vibrating within a certain range in the column direction.

FIG. 4 (model diagram) shows a model of the transmission path between the ZIP type semiconductor memory device 2 arranged in the memory area MA and the DIP type semiconductor device 5 or 6 arranged in the logic area XLA or YLA.

When the load impedance Z of the ZIP type semiconductor memory device (DRAM) 2 and the internal impedance Zi of the DIP type semiconductor device (driver/receiver) 5 or 6 which is the signal source are the same, the voltage reflection coefficient ΦV is calculated by the following equation. expressed.

Z□−Z.

ΦV = 21+2° where Z is the characteristic impedance of the transmission line.As shown in the above equation, if the characteristic impedance Zl of the transmission line is different, the voltage reflection coefficient ΦV is different. Usually, the load impedance Z1 of the ZIP type semiconductor memory device 2 and the characteristic impedance Z0 of the transmission line are different (Z1≠70)
. In addition to this, the difference in characteristic impedance Z0 of the wiring 3 extending in the column direction and the wiring 4 extending in the row direction in the memory area MA means that the voltage reflection coefficient ΦV difference between the wirings 3 and 4 is As a result, it becomes necessary to increase the margin of operation timing.

For example, in FIG. 5 (DRAM time chart), the row address strobe signal RAS.

Each of the column address strobe signal τ1 and the write enable signal WE is transmitted as a Y thread signal through a wiring 4 extending in the row direction. The write data signal WD is transmitted as an X-system signal through the wiring 3 extending in the column direction. Since the ZIP type semiconductor memory device 2 has a unique structure, as the ZIP type semiconductor memory device 2 is spaced apart from each of the DIP type semiconductor devices 5.6, when each of the wiring lines 3.4 is extended in a straight line, the column The difference between the characteristic impedance Zx0 of the transmission line in the direction and the characteristic impedance Z3'o of the transmission line in the row direction increases (zxa>zyo), and the reflection noise difference based on the voltage reflection coefficient ΦV difference increases. Therefore, the write data signal W
Column address strobe signal CAS for input of D
The set-up time t, will vary, causing malfunction in the worst case.

Also, as shown in Figure 6 (driver signal waveform diagram),
Each of the DIP type semiconductor devices 5 and 6 that drive the ZIP type semiconductor memory device 2 has an internal delay time (gate delay time).
to is the same, but the longer the wire lengths (characteristic impedances of the transmission paths) of the wires 3 and 4 are different, the greater the time difference required until the output signal becomes stable. In other words, when the wiring 3 extending in the column direction and the wiring 4 extending in the row direction are both extended in a straight line, since the ZIP type semiconductor memory device 2 has a unique structure, Wiring 4 extending to
(Y system) delay time t□ is the wiring 3 (X
system), and if the difference between the delay times t1 and t2 becomes large, malfunctions often occur.

In this way, each wiring 3.4 is placed at the intersection of the wiring 3 and the wiring 4 extending in different directions on the printed wiring board 1.
In a mass storage device (electronic device) equipped with a ZIP type semiconductor memory device [2 connected to
By configuring it non-linearly, the difference between the characteristic impedance Zx0 of the transmission path of the wiring 3 and the characteristic impedance ZYa of the transmission path of the wiring 4 due to the unique shape of the ZIP semiconductor memory device 2 is reduced, and the difference between the two is reduced. Since the difference in voltage reflection coefficient ΦV is reduced, the phase difference between the signals transmitted to each of the wirings 3 and 4 can be reduced, and malfunctions in information writing and information reading operations can be prevented. As a result, the electrical reliability of the mass storage device can be improved.

As shown in FIG. 1, the DIP type semiconductor device 6 arranged in the logic area YLA has a structure in which outer leads are arranged in the same row direction, so the wiring 4 extending in the row direction is It inevitably extends in a non-linear manner.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the above embodiment, eight ZIP semiconductor memory devices 2 are arranged in the column direction and eight in the row direction of the memory area MA on the printed wiring board 1, but the present invention 4 in the column direction of MA, 1 in the row direction
Six ZIP type semiconductor memory devices 2 may be arranged. In this case, as described above, the wiring 4 extending in the row direction is made to extend in a non-linear manner.

Furthermore, the present invention provides a wiring width of the wiring 3 extending in one column direction ( The thickness of the wiring may be larger than that of the wiring 4 extending in the row direction.

Further, in the present invention, the materials of the wiring 3 and the wiring 4 may be changed in order to equalize the characteristic impedance.

Further, the present invention provides a method for converting the ZIP type semiconductor memory device 2 into a DRAM.
It may be configured with other memory or logic.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The electrical reliability of an electronic device in which a ZIP type semiconductor device is mounted on a wiring board can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of a large-capacity storage device (electronic device) that is an embodiment of the present invention. FIG. 2 is a side view of the ZIP type semiconductor memory device mounted on the mass storage device, FIG. 3 is a bottom view of the ZIP type semiconductor memory device, and FIG. 4 is a side view of the ZIP type semiconductor memory device mounted on the mass storage device. FIG. 3 is a model diagram of a transmission path between a DIP type semiconductor memory device and a DIP type semiconductor device. FIG. 5 shows the D built in the ZIP type semiconductor memory device.
FIG. 6 is a time chart diagram of the RAM and is a waveform diagram of the driver signal of the DIP type semiconductor device. In the figure, 1... printed wiring board, 2... ZIP type semiconductor memory device, 2B... outer lead, 3, 4...
・Wiring, 5, 6...DIP type semiconductor device, MA...
Memory area, XLA, YLA...logic area.

Claims (1)

[Claims] 1. A first wiring extending in a column direction on a wiring board and this first wiring
In an electronic device in which a plurality of ZIP type semiconductor devices connected to the first wiring and the second wiring are mounted in a matrix at an intersection with a second wiring extending in the row direction intersecting the wiring,
An electronic device characterized in that the first wiring is substantially straight, and the second wiring is non-straight or has a wiring width or thickness smaller than that of the first wiring. 2. Claim 1, wherein the first wiring extends in the longitudinal direction of the ZIP type semiconductor device, and the second wiring extends in the width direction of the ZIP type semiconductor device. Electronic devices as described in Section. 3. The electronic device according to claim 1 or 2, wherein the non-straight line of the second wiring is a broken line or a curved line. 4. Each of the electronic devices according to claims 1 to 3, wherein the ZIP type semiconductor device is a DRAM.