JPH02128393A - Memory having series control circuit - Google Patents

Abstract

PURPOSE: To improve a speed of a series output from a dual port memory by providing a decoder connected between a counter and a register and selecting plural positions in a register according to a value stored with the highest order part of the counter. CONSTITUTION: A group of cells in the register 8 is selected by the counter 22 and the decoder 10, and the bits of the data of the group are added to a multiplexer 124 through a latch 112. The counter 22 increases its contents in response to respective periods of a series clock signal. One bit or plural bits of the lowest order of the counter 22 are decoded 110, and one bit among the bits of one group is selected to be added to a series output terminal, and the matter that the whole contents of the counter 22 are decoded at every series bit is prevented. For the series output, the higher order bit of the counter 22 is updated initially, and then, the decoder 10 selects the outputted bit of the next group while the final bit of the former group is outputted. Thus, data transfer is executed for a proper time.

Description

[Detailed description of the invention]

The present invention is in the field of memory devices, particularly dual port random access semiconductor memory devices such as those used in graphics applications. With the advent of previously inexpensive semiconductor memory, modern computer and microcomputer systems are now able to use bitmap video displays for the output of data from the system. As you know,
A bitmap display device stores at least one binary digit (bit) of information for each pixel (pixel) of the display device.
Requires memory that can store each item. Additional bits stored for each pixel allow complex images on a video display device, such as background and foreground images such as multi-color images or graphic backgrounds with structural information on top of them. It provides the possibility for the system to express, etc. By using bitmap storage, data processing operations that easily generate and modify stored images are also contemplated. Modern video display devices are often of the rask scan type, in which an electron gun traces a horizontal line across the display screen to generate the displayed pattern. In order to continue displaying the displayed rask scanned image on the video screen, the image must be refreshed at periodic intervals. The common refresh rate for cathode ray tube (cathode ray tube) video display devices is 1/60th of a second, since refresh operations performed at this rate are not noticeable to the human being at the knee of the system. However, as the number of pixels displayed on the screen increases, more pixels of information must be accessed from the bitmap memory between refreshes to increase the resolution of the displayed image. If this bitmap memory has only one input/output port, then if the refresh interval remains constant, υ1 of the time during which the data processing device can access the bitmap memory.
In this case, the cell size of the display device is reduced to 6. Additionally, the speed of the memory must be increased because more bits must be output in a given period of time. Multi-port random access memories have been developed which provide a continuous output of data to video display devices and likewise provide increased access possibilities of the contents of the memory to data processing devices. It is something to do. Multi-vote memory accomplishes this by providing a first port for multiple random accesses and updates by the computer system's data processing unit, and a second port independent of and asynchronous to the first port. and a second port for serial output of the memory contents to the video display device, thereby allowing access to the memory contents during output of data to the video display terminal. Examples of multi-vote random access memory are U.S. Pat.
7th issue), and No. 4.636,986 (1987
(Published on January 13, 2016) (Both have been given to Texas Instruments, Inc.)
(These corresponding E1 applications are Patent Publication IFi1M No. 1933.
1-216200). In each of these conventional multi-vote memories, data is shifted from some or all memory cells in a row of a random access array to a register during a special transfer period. Serial output is then achieved from the registers, but in a manner that is independent of and asynchronous to the random access operations of the data in the array. Serial input possibilities can likewise be provided in such devices with other types of transfer periods that can shift the contents of serial registers into selected rows of a random access array. The serial side of these conventional multi-baud L-memories has been constructed according to various structures. For example, the device described in the aforementioned U.S. Pat. , and one column output starts from the selected cell in the shift register from the tap contained in the shift register. Each six column clock pulse causes data to be output from the tapped shift register cell. The serial input, of course, provides the input data to the tap points to shift the input data stream along the shift register]
・It can be achieved by doing. However, if fewer tap points than cells are provided to the shift register of this device, the flexibility of the serial output (and input) origin is compromised. Greater flexibility in the starting point of series power/output
4,636,986, in which a double register contains serially output data. In this arrangement, a counter stores the address from which a column output originates, and a decoder operates in response to the counter to select, for example, one of the register cells from which a successive output originates. To provide a serial data stream, each pulse of the serial clock signal causes the counter to increment its stored value and the decoder to successively enable the next register cell accordingly. Serial input is similarly achieved by increasing the number of register cells that receive input bits from the serial clock. The use of a counter/decoder structure provides increased flexibility as to the origin of the serial output, but the serial register pin 1-
The counter and decoder circuitry necessary to select and update the selection includes a built-in delay. For example, to increment the location of the 0 column register, the counter must increment its contents in response to a serial clock pulse, and the iCog must increment its contents before the next serial register cell is selected. The output of has to be decoded again. Such delays can be reduced through design and manufacturing techniques and are inherent in this particular structure. It is therefore an object of the present invention to provide a vibline structure for the serial side of a dual-port memory in order to improve the speed of serial output from the same. It is a further object of the present invention to provide a vibrate such that the vibrate is overridden for serial input so that the serial input data is stored in the appropriate location in the serial register. A further object of the invention is to disable the pipeline for output while selecting other locations of the serial register. Other objects and advantages of the invention will become apparent to those skilled in the art upon reference to the following description, taken in conjunction with the accompanying drawings. The present invention may be incorporated into a dual-port random access memory having a serial register for serial output of data independent of and asynchronous to random access to the memory array. . A counter and decoder selects the group of register cells from which the serial output will originate and latches the bits of data for that group into the multiplex signal. This counter increments its contents in response to each period of the serial clock signal. The least significant bit or bits of the counter are decoded and one bit of a group of bits is selected and applied to the serial output terminal, preventing the entire contents of the counter from being decoded for each serial bit. For serial output, the more significant bits of the counter are updated initially, so the decoder selects the next group of bits to output while outputting the last bit of the previous group. In serial input mode, the more significant bits of the counter can be incremented normally, rather than by the initial update used on the serial output, so that serial input data received by the serial register is stored in the preferred register location. Ru. The Vibration line also has new serial registers.
It may be destroyed when selecting the address, so the initial output is not disturbed by the initial increment of the counter. 1 will now be described, which is a functional block diagram of a dual port memory 1 constructed in accordance with the present invention. Similar to the memory of the aforementioned U.S. Pat.
It receives clock signals RAS, CΔS, and 5CLK, a write enable signal WE, a transfer enable signal TR, and a serial output enable signal SOE. A built-in masking mechanism is included in dual port memory 1 so that only a single column address strobe CAS- can be used in dual port memory 1.
Note that memory 1 receives and uses. Dual Boat Memory 1 is based on U.S. Patent No. 4.6
36.8 random access power/output wires D rather than four like the memory input/output terminals of No. 36.986.
O to D7, and of course the present invention described here,
It can be applied to any dual boat memory structure or any other structure. Therefore, dual boat memory 1 is 8
arrays 2, each containing 128 kilobits of storage organized in this embodiment in 512 rows and 256 columns. Associated with each seven array 2 is a sense amplifier bank 4, which is well known in the art of sensing, restoring, and writing data to and from the dynamic memory cells of the array 2. It includes 256 sense amplifiers. On the random access side, the RAM logic 16 performs address latching and address decoding, such as that performed in the memory of the aforementioned U.S. Pat. No. 4,636,986, so that the row address strobe signal RAS- and column address - Each of the ST[1-B signal CAS and the address lines Δ0 to 88 are received. Address line AO to 8
The row address value appearing on line 19 is latched by the row address strobe signal RAS and communicated via line 19 to the One row at a time in array 2 can be selected. Similarly, (because the column address signal on aAB is unnecessary to select one of the 256 columns), the address △0
The column address values appearing on Δ7 through Δ7 are latched by RAM logic 16 in response to column address strobe signal CAS, and the wrapped column address values are communicated from RAM logic 16 to X decoder 20 by line 21. , 8
Each of the arrays 2 has an X decoder 20 associated with them. Thus, each Y-decoder 20 assigns the preferred bit line in its associated array 2 to its associated input/output buffer 24 corresponding to the latched column address value.
It works to connect to. In addition to the functions described in the aforementioned U.S. Pat. Additional controls exist. 8
Each of the input/output buffers 24 is connected to the multiplexer 2
6 to the data terminals Do to D7. For random access reading, the output of input/output buffer 24 is received by output drive circuit 31 and thereby transmitted to the terminals of lines Do through D7. The output drive circuit 31 may be constructed of one of many well-known shapes, and may be of the RAM theory I! ! 6 of 16 controls, line T R
It is enabled by an external signal above. Of course, for random access writes, output drive circuit 31 is disabled by RAM logic 16 to prevent data conflicts. During the write cycle, the line W'r from the special 11 function logic 30
CL R controls multiplexer 26 so that the data values appearing on data terminals DO through D7 are
Input/output buffer 7241 logic 1 through! ! The user selects one of the contents of the color register 50 in the color register 30 by the user's selection function.Special I! function logic 3
o is also operable to control a stored mask mechanism similar to that described above for U.S. Pat. No. 4,636,986, but the special function logic 3o The write mask value is operable to store the value of the write mask during multiple periods, and after the write mask value is initially loaded, and after an unmasked random access write. After , it can be recalled for any number of cycles. The contents of the matching mask register 54 or the contents of the unmasked write signal are preferably set by the special function logic 30 to the application serial number cylinder 053,200.
to input/output buffer 724 through BWCLK, as described in the above. Although the serial side of the dual port memory 1 is described, the transfer gate 6 is connected to the array 2 as in the dual port memory of the aforementioned U.S. Pat. No. 4,636,986.
is connected to each of the pit lines of the array 2 to transfer data from the array 2 to and from the data register 8. In this example, data register 8 is a 256-bit register, so 256 bits of data are transferred for each bank of transfer gates 6, ie, 2048 bits of data are transferred in each transfer period. The serial logic 14 is connected to the serial clock (i,
The serial iTJ enable signal on line 5OE- and the transfer signal on line rR- are received as well as the signals from RAM logic 16, and thus the data Transfers can be performed at appropriate times. As will be explained in more detail below, a counter 22, which may also include a pre-decoder, selects one pit in each data register 8 to which serial input/direct output is to be initiated. select. Accordingly, counter 22 receives the latched column address signal from RAM logic 16 on line 21 and receives the latched column address signal from RAM logic 16 on line 21,
For the No. 6.986 mailbox, the signal selects the position in the series where the series input or output begins. Serial logic 14 controls counter 22 to load the latched column address value during the transfer period and l! A signal is provided to the counter 22 for each period of the clock signal on JSCLK so that the 1 stored in the counter 22 is
11 increases with each series period. In the real example, counter 22 further includes a predecoder that partially decodes the values stored therein. Each serial decoder (or pointer) 10, as associated with each data register 8, receives the partially decoded contents of counter 22. The contents of the data register 8 are described in Iv3 U.S. patent m4, 636, 986 (7).
- each period of the clock signal on line 5CLK is not shifted in for each serial period as in The position of that bit will increase. The contents of the bits of each data register 8 as indicated by the associated one of the serial decoders 10 are stored in the serial power/output buffer 712 for input and output.
connected to the relevant one of said series input/output buffers? one associated with each of the eight arrays 2 and data registers 8. Series human power/output buffer? 12 conveys data between the associated serial power/output terminal SDO to SD7 and the bits of the associated data register 8 indicated by the serial decoder 10. Terminals 5OE- are serial human power/output terminals SDO to SD7
to put it in series input mode or series output mode,
Signals are received during various stages of the memory cycle. H in m1 diagram
In E, execution of the memory-to-register transfer cycle automatically places the serial side in serial output mode. In serial output mode, a high logic level on line SOE disables the serial output and 1! Since the low logic level on SOE enables serial output, the signal received by terminal 5OE- is used for output enable control in a manner well known in the art. In order to switch the serial side of dual port memory 1 from serial read mode to serial write mode, pseudo transfer l is used.
~ Execute period. Terminals RΔSWE, TR, and 5O
The signals provided on E- are used to perform and set up this cycle as well as to perform transfer operations. 1st
Referring to the table, the truth table of these signals during the high-to-low transition of RAS is described with respect to performing transfers in both directions and the pseudo-transfer period 111 that sets up the serial input mode. 0 0 0 Transfer from register to memory 001 Setup serial input mode 01 Note that we use the ``select'' to select the row from or to which the register transfer will occur. Pseudo transfer frequency J to set up serial input mode
1, the memory cells in the addressed row are refreshed. - Once connected manually, terminal 5OE -
The high logic state of terminal 51) disables the serial input at terminals 51)0 to $1]7, and the low logic state of terminal 5OE- enables six column inputs there. Therefore, in serial input mode, 5OE- performs an input enable function. Referring now to FIG. 2, the construction and operation of counter 22 and six column decoder 10 in accordance with a first preferred embodiment of the invention will now be described in more detail in conjunction with data register 8. The series loader 1° and data register 8 will be described below as being associated with one of the series input/output terminals SDO to SD7, but of course such a circuit can also be used with other series output terminals. It should be understood that this is also repeated for each of the output terminals SDO and SD7. Counter 22 is a ripple counter and will be output (or input data will be stored)
It includes eight presettable 1° radii 100o for storing the address value of one of the 256 bits of data register 8. Each of the latches 1oOn preferably has both true and complement T (toggle) inputs and true and complement Q outputs. Each latch 100o has a loadable signal on ILDEN and l3
tI'lJA may be preset by the signal line PSO to [ ] 87 from the RAM logic 16 so that the first position of the data register 8 for serial power/output can be loaded into it. . As previously discussed, this initial value is selected by the column address signal on lines AO-8 during the transfer cycle. After the pre-hit, line LDEN returns to the inactive state and latch 100n is no longer responsive to the logic state of lines PSO-PS7. The latch 100n has i, L! Latch 1oOo is a T-shaped whose stored content toggles in response to a low-to-high transition on its T input (i.e., a high-to-low transition on its −“ input). It stores the least significant bit and toggles its contents in response to the serial clock signal received at terminal 5CLK.Latch 1001 and latches 1003-100. is removed, therefore, latch 1
00o and the content of one of the latches 1002 to 1006 changes from 1 to O, 11? The contents of the next most significant of latches 100o are toggled to enable the value stored in counter 22 to properly increment. Q and Q-output of latch 1001 and wrap 1
Between the T and T inputs of 002 is a multibrella 1 to 10.
This multi-break +#102 selects either the output of the latch 10o1 to the latch 10Q2 or the output of the NAND gate 104 to the latch 1002. The multiplexer 102 is controlled by the signal 81 from the serial logic 14, which signal S1, as selected according to Table 1 above, determines whether the series side of the dual port 102 is in the serial input mode or not. Indicates whether it is in output mode. As will be explained in more detail below, in the non-column output mode, the true and complement outputs of NAND gate 104 are connected to the [and
- Connect to human power, latch 10o1 to latch 1002
Anticipate a carry to. In series input mode, latch 1
The true and complement outputs of 001 are connected to latch 100. ．． T of
and T-Connect to human power. The two least significant bits of the stored address value are stored in latch 1.
00 and 1001, but it is decoded by the LSB decoder 110 in the counter 22 and the four lines P
One of the trees MXO through PMX3 is driven to a high logic level in response to the values stored in latches 100 and 1oo1. For example, line PMXO is connected to LSB decoder 10 in response to latches 100Q and 1001 storing VJoo.
0, line PMX1 is driven high in response to 1If01 stored therein, and so on.
This is irI. Therefore, IilPMXO to P M
A high logic level driven on X3 will only activate the Lebel and exclude the other levels, so there is no time penalty. The lines PMXO to PMX3 control the multiplexer 124 to control, for each data register 8 in the dual port memory, the data register 8 selected by the predecoder 108 and the serial decoder 12, which will be described below. Select 1 bit out of 4 bits. Line PMX3 carries a high logic level only when latches 100o and 1001 contain the value 11, and NΔAND gate 10
It is connected to No. 4's first power. NAND gate 104
The second human power is the theory of line LDEN I! I! The complement is received (via inverter 11), but the line LDEN causes the latch 100 to pass from 12Pso to PS7 during a high logic state.
Allows loading of new values into . Once a new memory is loaded and the series output or input begins, line LDEN goes to a low logic level, thereby allowing the logic state of iilPMX3 to control the output of NAND gate 104. Both the true and complement (inverted by inverter o5) are provided to multiplexer 102. In serial output mode, multiplexer 102 outputs the outputs of NAND gates 1-104 (without inverting) to latch 1002. and the output of inverter 105 is connected to the input T- of latch 1002. Thus, in series output mode, latch 1002 is configured such that the contents of latches 100o and 1001 change from 1ffi11 to IrlOOl%l:increase and 2' (7ch 100
t '7) Q and Q- outputs of latch 1002
- and inputs), the contents of latches 100o and 1001 are stored in latches 100 to 100□ when they increase to fifullll and decoded by predecoder 108 contained within counter 22. The address stored in counter 22 is added to each of the eight data registers 8 in dual port memory, so rather than completely decoding the same value at eight locations in memory, counter 22 It is useful to perform at least a partial decoding of this address within. Of course, the number of outputs from predecoder 108 varies depending on the number desired to be predecoded in counter 22; for example, predecoder 108 decodes the outputs of latches 1004 through 100 degrees from 4 to 16 at its output. latches 1002 and 10
The output state of 03 passes through the predecoder 108. Thus, the serial decoder 10 associated with each data register 8 is operable to select location II of the 256 locations of its associated data register 8 in response to the output from the predecoder 108. If necessary,
An intermediate output buffer may be provided, as is well known in the art, to provide buffered data from among four selected locations in data register 8. Such intermediate output buffers are not specifically shown in FIG. 2 for the sake of clarity. For serial output, the contents of the four data registers 8 selected by the serial decoder 10 are connected to the 4-bit latch 112 by bus transistors 114 and 116. Only one bus transistor 114 and 116 is shown in FIG. 2 for clarity;
A pass transistor 114 parallel to 6 is of course provided for each of the four data lines between data register 8 and latch 112. If necessary, bi-directional tri-state buffers and 6 line pass transistors 1
It may be used instead of 14 and 116. The gate of pass transistor 114 is gated by the output of OR gates 1-113, at the inputs of which are lines Sr and LDEN. Therefore, during the series output mode (line Sl is low), a low logic level on line LDEN causes 1-transistor 114 to be nonconductive. Except during the time when a new value is being loaded into latch 100n, line LDEN is in such a low state and pass transistor 116 connects data transistor 8 and wrap 112 during the series output, as will be explained in more detail below. You can control the communication of data between any of them. The gate of pass transistor 116 is set to υ by the Q output of RS latch 118.
However, the set input of Rs clutch 18 is line 1)
Controlled by M X O. The input to latch 118 is controlled by the output of OR gate 120, and the second input to OR gate 1-120 is controlled by AND gate 1.
22 output. The inputs of AND gate 122 are connected to lines PMX3 and LDEN. The serial input problem is that the n state of line S1 causes pass transistor 114 to communicate data between latch 112 and data register 8 regardless of the state of latch 118. Latch 112 is a 4-bit latch that connects data register 8 (via either pass transistor 114 or 116) to multi-seven lexer 124. Store the data to be communicated between. Multiplexer 124 is IIPMXO to PM
X3, and those lines determine which of the four bits of latch 112 are output to the serial power/output terminal SDo (or which of the four bits of latch 112 are input data from the serial power/output terminal SDo). (remember)
shows. Required manpower and output buff? is constructed in a known manner and is connected between the output of multiplexer 124 and the serial power/output terminal SDo. Now, with reference to FIG. 3, the operation of the circuit of FIG. 2 in the serial output mode will be described. A first example of such operation is that the contents of latches 100o and 1001 are changed from the previous address to the value 0.
An example of circuit operation when a new address is loaded into counter 22, starting from an initial state incrementing to 0, will now be described. Therefore, line LDEN is at a much lower logic level in this example, rendering pass transistor 114 non-S conductive and causing the output of AND gate 122 to be at a lower logic level. Additionally, line SI at the 1I11 input to multiplexer 102 will select the output of NAND gate 104 to be connected to the T and T-power of latch 1002. The MOO of latches 100° and 1001 causes a high logic level on lines PMXO from LSB decoder 110 and PMXl, PMX
2, and produces low levels on PMXa. wire PMXO
The high level above sets the RA clutch 18 (as shown by "Q118" in FIG. 3) and sets the data register 8.
is connected to latch 112 to connect latches 1002 to 100.
Load the contents of the four locations addressed by 1. A high logic level on line PMXO causes multiplexer 12
4 will select the corresponding 161 of the four bits of latch 112 for output to the serial input/output terminal SD (designated BITO in FIG. 3). . The state of latch 100o toggles from 0 to 1 upon the next low-to-high transition of the serial clock signal at terminal 5CLK. Since the Q-output of latch P100o is connected to the input of latch 10o1, the input of latch 1001 will experience a high-to-low transition and will prevent latch 1001 from toggling at this time. In response to the change in the value of latch 100o, line PMX1 from LS8 decoder 110 goes high and line PMXO therefrom returns low. Therefore, multiplexer 124 selects the second of the four bits stored in latch 112 (designated BIT1) for output to column a power/output terminal SD. Following the next low-to-high transition of the serial clock signal at terminal 5CLK, the contents of latches 1oOo and 1001 become 10. Therefore, the LSB decoder 10
drives high and returns IPMXI to its low state. The low to high transition on line PMX2 causes OR gate 1 to
20 and resets the output of RS latch 118 to a low level (as shown in FIG. 3). Since the contents of the latch 112 contain the bit fjS3 and number 4, which is output at the serial power/output terminal SDo, no data is lost by the separation of the data register 8 from the wrap 112, and by this separation: This allows a new set of four bits to be selected in data register 8 without having to separate the contents of latch 112. The third bit stored in latch 112 (ie, BIT2 in FIG. 3) is selected for output by multiplexer 124 in response to line PMX2. The next cycle of the serial clock signal of terminal 5CLK will cause the contents of latches 100 and 1001 to be increased to the value 11, followed by 1. SB decoder is aPMX
3 and will pull line PMX2 low. Therefore, the output of NΔND gate 104 goes from high level to low level. Line S1 connects multiplexer 102 to 1. I
J m L with latch 1002 T and T - NA for manual use
Since the output of the ND gate 104 can be selected, the latch 100
2 - "The input will undergo a transition from low to high and change state (line T I N in Figure 3)) LJ
see T1o02), Conolatchi 1002f7)l
- the value stored in the latches 100 to 1007 is increased by the gluing, and the values stored in the predecoder 8 and the serial decoder 1
0 responsively selects the next group of four bits in data register 8. However, since the output of the RS latch 118 is low, the data register 8 is isolated from the latch 112 and therefore the selection of the next group of 4 bits will cause the data stored in the latch 112 to be output at the serial power/output terminal SDo. Don't interfere. The fourth pitch of latch 112 (- is high as shown in Figure 3 for BrT3).
Selected for output by multiplexer 124 responsive to PMX3. This fourth bit is of course from the previous set of four bits in the data register selected by serial decoder 10. The next low-to-high transition of the serial clock signal at terminal 5CLK sets the contents of latches 1oOo and 10o1 to the value O
increases to O. As previously discussed, this sets the output of RS launch 118 so that pass transistor 116 communicates the four selected bits of data register 8 to latch 112 for output therefrom. wire PMXO
is asserted as described above, and the 1st to 8th bits of the 4 bits of the latch 112 are selected for the output (indicated by BITO' in Figure y43). From the above discussion, it can be seen that the serial output of data from dual-port memory 1 occurs for each incremented position of data register 8 without requiring the entire contents of counter 22 to be decoded each time. That is clear. The only operations required for the 2i through 4th bits stored in latch 112 are decoding the two least significant bits stored in latches 100o and 10o1 and decoding the other data bits in latch 112 by multiplexer 124. The key is to choose. Referring to the line T INPUT 100□ in FIG. 3, the dotted line indicates the time that a single person's force on the latch 1002 is toggled without the vibrate mechanism. Latch 1 connected to T- and T inputs of latch 1002
001's Q and Q- outputs allow the remaining latch 100o
Similarly, launch 1oO2 toggles the contents of latches 100o and 1oo1 increasing from their maximum value 11 to their overflow Id100. Thus, the pipeline mechanism of the circuit of Figure 2 allows the most significant bit of the data register address to be decoded one serial clock period in time, and thus (in the previous example) the next set of By the time the 1st ft of 4 bits are output, the value stored by the five most significant pits of counter 22 has been incremented and decoded. This structure therefore provides a faster i-death stream than conventional serial ports, which require de-loading the contents of counter 22 after each serial serial increment. However, the initial increment of the six most significant bits of counter 22 presents a problem if a serial input is desired. For example, if the contents of latch 1002 were toggled to 1 while serially input to the 4th bit of 411ii1 of the previous group (line PMX3 high), the contents of the 4 bits stored in latch 112 is stored in an incorrect location in the data register 8 (ie, 4 bits one group before the originally selected group). Therefore, pipelines should preferably be disabled for serial input. To accomplish this, rather than connecting the true and complement outputs of NAND gate 104 to the T- and T-powers of latch 1002 by line SI, we select the Q and Q- outputs of latch 1001 to connect thereto. Achieved by Thus, in the case of a serial input, the signal seen at the input of latch 1002 will be as shown by the dashed line in FIG. During input, the contents of latches 1oo2 through 100. are incremented and decoded so that the serial input data received at serial power/output terminal SD via latches 112 is placed in the desired position of data register 8. This ensures that the new starting position of data register 8 is at address 12.
Latch 10o via pso to PS7. to 1007 respectively, incorrect addressing will occur if the new address contains a square 11 in the two least significant bits. Such a problem is caused by the LSB in response to the value 11 in latches 10oo and 1oo1 toggling the contents of latch 1oo2 after the state of line PS2 is latched into latch 1002.
This can be caused by line PMX3 generated by decoder 110. For example, the preferred address value is 000000112
If so, the undesired toggling of latch 1002 causes the address value decoded by predecoder 108 and column a decoder 11° to be 00000111, ie, four bits before the desired location in data register 8. Therefore, the initial decoding into the first group of 4 bits 1 will result in the two most significant bits (1111 "preempting" the next group of 4 bits).
It is desirable to do this according to the actual value of the address, without having to do so. The circuit of FIG. 2 allows new addresses to be added while preventing undesirable increases in the six most significant bits stored in latches 1o02 through 10o7 until the first group of four pins 1- is loaded into latch 112 for output. counter 22
It offers the possibility of writing [1-] to [1-]. A high logic level on line LDEN allows latch 100o to be loaded with the logic state on IaPSO through PS7. This high logic level is connected to the NAN via inverter 111.
The output of NAND gate 104 is prevented from toggling regardless of the state of line PMX3 because it is connected to the output of D-gate 104. A high logic state on line LDEN turns on pass transistor 114 so that the four bits corresponding to the values stored in latches 10o2 through 1007 are transferred to latch 112 immediately after DE':1-. As mentioned above, the output of the LSB decoder 110 is connected to the serial power/output terminal SD by controlling the multiplexer 124.
At point o, one pit of the four bits of latch 112 is selected for output. Once aLDEN returns low, bus transistor 114 is turned off and the state of line PMX3 again toggles latch 1002 to change the selected state of the fourth bit of latch 112. Because of this toggle, pre-decoder 108 and serial decoder 10
will select the next group of 4 bits for output while outputting the 4th to 4th bit of the previous group. As previously discussed, the high logic state on 8PMX2 resets the RS latch 118, thus isolating the wrap 112 from the data register 8 while the next group of four bits is selected. AND gate 122 and O
2 of the loaded address by providing an R gate 120
Latch 112 is isolated when the least significant bit of Mx2 is 11 (i.e., there is no l' M X 2 signal to reset RS launch 118). If line LDEN and line PMX3 are both in a high logic state at the same time (i.e., the loaded address ends with 11), a high level is applied to AND gate 122
1 gate 120, thus resetting the RS latch 118 and causing the pass transistor 116 to turn A.
It will be deleted. Line LDEN turns on bus transistor 114 and disables the toggling of NAN I) gate 1-104, so the four bits selected by the new initial address are transferred through bus transistor 114 to latch 112. and the 4i-th bit is 1-,
Selected by multiplexer 124 in response to a high logic state on line PMX3 from S B decoder 10. 11! When -ILDEN subsequently returns to a low logic state when dPMX3 is ar&, pass transistor 114 turns off and OR gate 120 and AND gate 122
The actuation of latch 118 resets latch 118, thereby isolating latch 112 from data register 8. Similarly, when line LDEN subsequently returns to a low logic level (line PMX
3 is high) the output of NAND goo h 104 goes low, toggling the T output of latch 1002, causing latch 10
Increment the stored count from 0 to 1007. This allows predecoder 8 and serial decoder 10 to decode the incremented count and select the next corresponding group of four bits in data register 8. As previously mentioned, on the next period of the serial clock signal at terminal 5CLK, it goes high following the toggle of lines P M The four data bits are connected to latch 112 for output therefrom. Referring now to FIG. 4, another preferred embodiment of the invention will now be described. The elements of the embodiment shown in FIG. 4 perform functions similar to those of the embodiment of FIG. 2 and are designated by the same reference numerals. According to the embodiment of FIG. 4, vibration lining is performed according to the state of the least significant bit of the address stored in latch 1oOo. . Therefore, the seven most significant bits of the address stored in latches 1001 to 100□ are
Decoded by column decoder 10 to select 2 bits out of 256 pits of data register 8. Latch 1 by multi-branch 102 in series output mode
Latch the Q and Q of 00o and the T and ■ of 1001
- respectively connected to human power and thus in response to the contents of the wrap 100o switching from 0 to 1, the zero column of the actual value;

[Latch 100.1 cycle before the cock signal. toggle. As a result, frea'-da 108 and serial decoder 1
Q is allowed to increment the contents of the seven most significant bits of the stored address while outputting the second of the two bits of the previous group. In series input mode,
Latches 100 and 10 by multi-branch 102
01 is reversed so that the Q and Q- outputs of the latch 100o can be connected to the D- and T inputs of the latch 1001, respectively, but this is different from the connections of the other latches 1001 to 100□. The same is true. Therefore, the signal on line St fills the multi-branch 102 for selection of the serial decoder's vibe line connection. Similarly,
I! 1lLDEN'? JL-1-7L/ri"J102
as the aI control input to Wrap 1001.
latch 1 connected to the T and ``inputs respectively
The series input mode connection of the Q and Q-outputs of 00o is connected to the line p
Selected when loading latches 1001 to 1007 from so to PS7. The latch 112 is connected to a 2 to 1 multiplexer 124 whose control inputs are connected to the Q and Q outputs of the latch 100° so that the 2 of the information stored therein for conveying to the output terminal SDo
Select from pits. Bus transistor 114 is connected between data register 8 and latch 112 to transmit two bits of the data. As in FIG. 2, only one bus transistor 14 is shown in FIG. 4 for clarity, but of course two bus transistors 114 are used for each of the two data lines. l・restate・back 7
is also used there. The gate of bus transistor 114 is connected to the output of OR gate 1-200. The OR gate 200 has three powers, one of which is connected to the output of the AND gate 1-202, and the other two powers are connected to the lines LDEN and Sl. In this way, bus transistor 114 (line L
o During the loading of latches 100 through 1007 (when IEN is at a high logic level) or during times when the serial clock signal on line 5CLK and the Q-output of latch 100o are both high (line SI is conductive in series power mode (high logic level). The operation of the alternative preferred embodiment of FIG. 4 will now be described with reference to FIG. 5, which is shown after the low day leg of latches 10o-10o1 during the serial output mode. Wrap 100.17) The Q output is shown as changing the full period of the serial clock signal received on line 5CLK. Series 8
Since we selected 1 Rikishi-do, the power of latch 1001 follows the Q output of latch 100o, and the I! output of latch 100o transitions from low to high. c) Latches 1001 to 100. content increases. Latch 100 shown in FIG. The dashed waveform of the T input of 100o shows the relationship of the Q-output of latch 100o connected thereto during the series input mode. Therefore, in series output mode, latch 10o
The contents of 1 through ioo are incremented one full period of the serial clock i8@ than when they are incremented in serial input mode (ie, without the pipeline mechanism described herein). During the serial output stream, lines SI and LDEN are both low, so OR gate 200 is responsive to the output of AND gate 202. AND gate 202 is connected to latch 10oo
high output from OR game 1-200 (so Q100o in FIG. 5 has an output such that the serial clock signal on line 5CLK is high). [Turns on bus transistor 114, connecting the selected pair of pits from data register 8 to latch 112. After the column clock signal on line 5CLK returns low, bus transistor 114 is a turn
Turned off, latch 112 is isolated from data register 8. As mentioned above, since the f input of launch 1001 makes a low-to-high transition such that the Q output of latch 100o is high, the seven most significant pits of counter 22 are incremented and Serial decoder 10
decoded by This is particularly important when the second pit of the selected pair (eg [31T 1 in FIG. 5) appears at the output. Since the output of OR gate 200 is low at this time, bus transistor 14 isolates latch 112 from data register 8 so that the output data is output to latch 1oO
Not to be disturbed by the completion of the decoding of the increased content of fly 1007, which the terminal S CL
K serial clock signals occur during this period. Terminal SC
In response to the next low-to-high transition of the serial clock signals [, K, the output of OR gate 200 goes high, so that the bus
Transistor 14 conveys the next group of two bits selected in data register 8 to latch 112, and the Q-output of latch 100o outputs the first pit of the two bits through multiplex block 124. This is indicated by BIT O- in FIG. During serial input, pipelined decoding is preferably disabled, as in the embodiment of FIG.
Preferably, the second pit of the input data is not written two bits before the desired position. Therefore, by line S1, multiplex clear 102 is connected to latch 100o.
The Q and Q- outputs of latch 100n are connected to the T- and T inputs of latch 1001, respectively, and the other latches 100n are similarly connected. Furthermore, since this decoding occurs consistently with the input data, line Sl, via OR gate 200, remains conductive throughout the series input operation. Similar to the embodiment of FIG. 2, the new contents are latched 1oO1
Potential ambiguities that might otherwise arise during the L''-code from 10o7 to 10o7 can be avoided by the structure of FIG. During this loading, if line L DE N is at a logic level, multiplexer 102 connects the Q and Q- outputs of latch 10oo to the [- and T-outputs of latch 1001, respectively.
Connect to the input, and do the same for the other latches 100. In this way, an initial increase in the state of 1001 will no longer disturb the first output bit from data register 8. Additionally, the OR gate 200 is high on the line L DE
In response to N, pass transistor 114 is turned on.
On, the bit pair selected by the new contents of counter 22 is passed directly to wrap 112. Line L
Once DEN returns low, operation continues as described above in connection with FIG. The features of the embodiment described here are, of course, that
... It is appreciated that it can be applied to various structures on the serial side of the dual-port memory 1, such as the data register 8. These split data
The register 8 allows transfer between the split data register 8 and one of the transfer gates 4 during the serial output from another split data register 8, such as the output using vibration lining as disclosed herein. be made into Although the present invention has been described above with reference to embodiments, it should be understood that this description is merely an example and is not intended to be interpreted in a restrictive manner. Furthermore, it will be obvious and possible to make many modifications and additions to the details of these embodiments of the invention to those skilled in the art upon reference to this description. I hope you understand that. Furthermore, those skilled in the art may readily replace what is described herein with existing and future equivalent arrangements to achieve the same results as the described embodiments. Such modifications, substitutions, and additional embodiments are intended to be within the spirit and scope of the following claims. In connection with the above description, the following sections are further disclosed. (1) having an array of memory locations arranged in rows and columns and a register, in response to a serial clock signal, the register having a plurality of memory locations in a selected row of the array;
In a type of memory in which the contents of a cell can be transferred and the data from its register can be output serially at a serial output terminal, a serial control circuit is arranged in the most significant part and the least significant part. a counter for storing a value corresponding to a position in the register, the counter receiving the serial []tk signal;
responsively increasing its contents; a decoder connected to the counter and the register to select locations in the register according to the value stored by the most significant portion of the counter; a latch for storing the contents of a plurality of register locations selected by a decoder; and means connected between the register and the latch for selectively isolating the latch from the register in response to an isolation control signal. and connected to the uppermost portion of the counter to generate the separation control signal to the separation means in response to the contents of the lowermost M1 portion of the counter and to control the predetermined set of counters. and υ control logic for increasing the contents stored by the stages. (2) In the series control circuit according to paragraph (1), the counter is a ripple counter including a plurality of stages, each stage having a toggle input, and the lowest stage of the counter a clock signal is received at its toggle input, the lowest stage of the topmost part of the counter has a toggle power connected to the control logic, and the other of the stages is connected to the output of the next lowest stage. Series control circuit with toggle input connected. (3) In a series control circuit according to paragraph (2), the control logic is configured to control the control logic of the counter in response to the lowest portion of the counter reaching a value less than an overflow. A series control circuit that provides a toggle input to the lowest stage of the uppermost part. (4) In the series control circuit J3 as described in paragraph (2), the stage of the counter further has a preset input and a load control input, so that each stage responds to the load enable signal to A series control circuit that is controlled by the logic state of the Bricht input. (5) In the serial control circuit described in item (4), the separating means connects the register to the latch in response to the rfX load enable signal. (G) In the series υIt11 circuit described in paragraph (5), the 1III control logic controls the uppermost portion of the Nr counters in response to the lowermost portion of the counter reaching its maximum value. Increasing series! 11 control circuit. (7) In the serial control circuit according to item (6) rn, the control logic is configured to, in response to the load enable signal, when the most significant portion of the counter reaches the maximum value, ``'r; (8) The series control circuit described in paragraph (1), further comprising: between the Iyi latch and the serial output terminal. and having control power in response to the content of the uppermost portion of the counter to select the position of one of the latches for transmission of data. A series control circuit including a multiplexer. (9) A series 1iIJ control circuit in which the lowest part of the counter stores a single bit in the one-column control circuit described in paragraph (1). (10) Paragraph (1) In the series control circuit described in
A serial control circuit in which the first stage of the counter stores a count bit. (11) Series as described in paragraph (1)! ! I 111
In one circuit, a series control circuit in which a 1-do-1 notation W logic increments the most significant portion of the counter in response to the least significant portion of the counter reaching its maximum value. 12) Serial control in the series ft, I control circuit described in paragraph (11) to generate the separation control signal prior to the !100 logic incrementing the contents of the predetermined set of stages. <13) an array of memory locations arranged in rows and columns; means connected to the array for selecting a row of the memory locations in response to a -C1 row address signal; a serial access terminal; a register containing a location; means connected between said array and said register for transferring the contents of a plurality of memory cells in a selected row of said array to said register; and a column clock signal; a serial clock terminal for receiving a serial clock terminal; Dynamically connected, so that its contents are incremented in response to fFJ serial L]tk (3) and that there is a connection between the lyl counter and the said register: and a decoder for selecting a plurality of positions of said register in response to the contents of a predetermined set of stages of said counter, wherein said stage of said N constant phases is the highest of said colors. a multiplexer connected between the register and the Maki series/Cress block to convey in its darkness the contents of a selected one of the plurality of register locations; register position 11!2ffi6'f corresponds to the remaining contents of the counter and is not in the predetermined set of stages; Predetermined 11 other than
control logic for incrementing the contents of the predetermined set of stages of the counter in response to increasing tI. (14) The memory described in paragraph (13),
further comprising: isolation means connected between said register and said latch for isolating said latch from said register in response to an isolation control signal; generating the isolation control signal in response to reaching a predetermined value other than an overflow value. (15) In the memory described in paragraph (13),
A memory in which the remainder of the counter includes a single stage. (16) In the memory described in paragraph (13),
A memory in which the remainder of the counter includes multiple stages. (11) In the meter described in paragraph (13),
the counter is a ripple counter, the stages therein having toggle power, the lowest stage of the counter receiving the serial clock signal at its toggle input, and the lowest stage of the predetermined set having a toggle input; the toggle input of the other stage of the counter is connected to the output of the next i74th stage; and the control logic is configured such that the remaining contents of the counter in response to reaching a predetermined value other than the A-Purflow value;
The memory is characterized in that a signal is provided to the 1-Glue inputs of the lowest stage of the predetermined phase. (18) In the menu described in paragraph (17),
The control logic determines whether the register receives serial input data.
responsive to a serial selection signal indicating a serial input need to be taken, the control logic during the serial input mode selects the predetermined set of stages in response to the remaining content reaching its overflow value; Memory to increase the contents of. (19) In the memory described in paragraph (18),
A memory in which the serial access terminal is also adapted to receive and receive serial input data. (20) In the memory described in paragraph (19),
The control logic is connected to the output of the remaining stages of the counter.
a decoder, said decoder having an output corresponding to a predetermined value other than its overflow value stored in said remainder of said counter; and a υIgA multiplexer connected to said output of said LS8 decoder. a data input connected to the output of the most significant stage of the remaining stages; a control input for receiving the serial input selection signal; and a toggle input of the least significant bit in the predetermined set. an output of the top of the remaining stages, such that the output of the top of the remaining stages is communicated to the output of the iII1wJ multiplexer during the serial input mode, and the output of the L S B decoder is coupled to the serial input. and being communicated to the output of the control multiplexer when the control multiplexer is not in the mode. (21) In the email described in paragraph (19),
A memory in which the remainder of the counter includes the first row. (22) In the memory described in paragraph (21),
The Qi control logic is a ljJ III multiplexer having a data input connected to the output of the remaining stage, a data input connected to the complement of the output of the remaining stage, and a data input connected to the output of the remaining stage; having an output connected to the toggle input of the topmost pit and a t,l+511 input receiving the serial input selection signal, so that the output of the multiplexer is responsive to the overflow contents of the remaining stages. provides a toggle signal to the least significant bit in the given silk during the serial input mode, and the output of the remaining stages changes when the output of the control multiplexer is not in the serial input mode but overflows. and providing a toggle signal to the memory in response to the non-responsive memory. (23) Discloses a 1J dual port memory with the features of Vibrine 6-row ports. The serial side of the dealport memory is divided between predetermined stages and includes a pull counter 22. Gecodes the contents of the stages above the divide to select one group of pins 1- of the serial register 8 for output, and the contents are latched by the latch 112. Therefore, in response to the steps above the break approaching a certain value, the steps above the break are incremented by 4 degrees, and the increased value is decoded. Bus transistor 114 between register 8 and latch.
116 is turned off during such times that the increased value is being decoded, so the new value does not disturb the output. The latched output is sent to multiplexer 1 which selects the latched bit according to the chain below the vlth stage.
24. The value of the stage is the maximum! t
When a 1 (i.e., the first bit of the next group) is reached, it enables pass transistors 114, 116 so that the contents corresponding to the increased contents of the stages above the split are next represented at the output. Yonizuru. Logic is provided to prevent splitting of stages during serial input and to prevent the initial increment of counter 22 19j prior to storage of input data. Logic is similarly provided so that after the counter is loaded with a new value, the first bit is output first, unencumbered by the initial increment of the counter stages one above the divide.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a preferred embodiment of a dual-port memory constructed in accordance with the present invention. FIG. 2 is a schematic electrical diagram of a first embodiment of the serial input/output circuit of the memory of FIG. FIG. 3 is a timing diagram illustrating the operation of the serial output from the circuit of FIG. 2. FIG. 4 is a schematic electrical diagram of a second embodiment of the memory serial input/output circuit of FIG. FIG. 5 is a timing diagram illustrating the operation of the serial output from the circuit of FIG. 4. Explanation of main symbols 1: Dual port memory 8: Data register 10: Serial decoder 22: Counter 100.112: Latch 102.124: Multiplexer 108: Predecoder 110: LSB decoder 14°: Bus transistor

Claims (1)

[Claims] (1) having an array of memory locations arranged in rows and columns and a register for transferring the contents of a plurality of memory cells in a selected row of the array to the register in response to a serial clock signal; In a type of memory in which data from the register can be output serially at a serial output terminal, a serial control circuit is arranged in the most significant part and the least significant part to output data from said register in series. a counter for storing a value corresponding to a position of the serial clock signal, the counter receiving the serial clock signal and incrementing its contents in response; a counter connected to the counter and the register; a decoder for selecting a plurality of locations in the register according to a value stored by the most significant portion of a counter; a latch for storing the contents of the plurality of register locations selected by the decoder; and a combination of the register and the latch. means for selectively isolating the latch from the register in response to an isolation control signal; and means for selectively isolating the latch from the register in response to an isolation control signal; and control logic for generating said separation control signal for said separation means and for incrementing the contents stored by a predetermined set of stages of said counter.