JPH02127888A - Nonstandard signal deciding circuit - Google Patents

Abstract

PURPOSE:To convert a video signal into a digital signal and to decide standard/ nonstandard signal by generating a television signal with a prescribed time difference from a television signal from an A/D converter converting a television signal into a digital signal and comparing synchronizing signals of television signals with a prescribed time difference. CONSTITUTION:A video signal inputted from an input terminal 10 is converted into a digital signal by an A/D converter 14. Moreover, a burst PLL clock generating circuit 12 outputs a clock signal of 4fSC to each section. The digital signals is retarded by delay elements 16, 18, 20, and when the input video signal is a standard signal, the signal is delayed by 1H, 1H, 524H respectively at the delay elements 16, 18, 20 and the video signal is converted into 1-bit synchronizing signal by synchronizing separator circuits 40, 42, 44. Two synchronizing signals inputted to a phase difference detection circuit 46 are standard television signals, then the signals are in-phase signals delayed by one frame, and no output is obtained and if any output exists, it is the nonstandard signal. Thus, the decision of the nonstandard is applied independently of the characteristic of an A/D converter or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION (() Industrial Application Field The present invention relates to an IDT equipped with a large capacity memory in field units.
V, relates to a non-standard signal determination circuit built into EDTV.

(B) Prior Art In recent years, memory has become cheaper, and it has become possible to provide inexpensive television receivers (TVs) that use field memory and frame memory to improve images.

These TVs use these field and frame memories to perform inter-field processing or inter-frame processing.

Incidentally, frame type YC separation and field type scanning line interpolation are well known as these inter-field/frame processes. These T
When performing YC separation, V is the frame type YC separation processing output and the intra-field YC separation processing output (YC separation processing output by BPF).
C separation, line type YC separation) are switched (or the mixing ratio is varied) depending on the magnitude of the image movement. Also, when performing scanning line interpolation, the mixing ratio of the line type scanning line interpolation processing output and the field type scanning line interpolation processing output is varied or switched depending on the magnitude of image movement.

Note that these motion adaptive shadow signal processing are described in the following documents and are well known.

(a) "ID
TV and Home Video Technology Wi”.

(b) P12 of the magazine “Nikkei Electronics, September 4, 1986 issue, No. 403” published by Nikkei McGraw-Hill.
3-P143, ``High-definition televisions using digital technology, which are expected to become the pillar of the next generation of home appliances.''

(c) Magazine “TV Technology,” published by Denshi Gijutsu Publishing Co., Ltd.
June 1988 issue, pages 19 to 32, ``Next-generation, high-definition digital color television, (NEC1I DTV system high-definition S digital television "C-29D70") (Toshiba, frame double scan system, digital television '3)
01DI")"・C By the way, the above-mentioned TV is intended for standard color television signals in accordance with broadcasting standards. The feed frame memory is controlled using a clock signal synchronized with the color subcarrier. For this reason, home VTR
As the reproduced video signal from
It cannot support non-standard color television signals that do not maintain 5/2 f□.

Incidentally, this is also shown in P26 and P27 of the above-mentioned document (c) and the following documents and is well known.

(d) P33 of 1986 Television Society National Conference, published on August 1, 1986.
7. "Study of 1mprovedTv compatible with non-standard color TV signals" written by Ishikura and Achiha (Nikke Seisakusho) of P2S5.

(e) JP-A-62-175091 (HO4N9 /
78) With these TVs, when a non-standard color TV signal is input,
Motion adaptive signal processing is stopped and intra-field processing (inter-line processing) is performed.

Therefore, a detection circuit is required to detect when this non-standard color TV signal is input. This detection circuit basically detects whether or not the following equation holds true. In other words, for a standard NTSC television signal, the following equation holds.

fsc' Color printing carrier wave frequency fM: Horizontal synchronization frequency fv: Vertical synchronization frequency f,: Frame frequency This detection circuit is called a non-standard signal determination circuit. This circuit frequency-divides the outputs of, for example, a horizontal AFC circuit and an APC circuit synchronized with a color subcarrier, and compares the frequencies of the divided outputs to determine whether the frequency is standard or non-standard.

By the way, when a video signal is converted into digital data and processed, elements such as an A/D converter and a reference clock generation circuit are added to the system. When performing 3D YC separation,
A clock that is phase-locked to the color burst signal is used, but depending on the characteristics of this PLL circuit, due to the influence of noise etc., even if the analog signal is a signal (standard signal) that complies with NTSC in terms of frequency, it may be difficult to use a clock that is phase-locked to the color burst signal. The signal may be converted into a digital signal (non-standard signal) unsuitable for next-form processing.

(...) Problems to be Solved by the Invention However, the standard/non-standard determination is more accurate if it is made using a digital video signal processed in memory.

Further, in order to simplify the circuit for this determination, it is better to use the field/frame delay circuit for the three-dimensional processing circuit also.

Further, it is better to derive the standard/non-standard determination from more determination results.

(d) Means for Solving the Problems The present invention provides a clock generation circuit (clock generation circuit) for creating a clock signal synchronized with the color burst of an input television signal.
12), an A/D converter (14) that converts the television signal into digital, and this A/'D converter (14)
delay means (18, 20) or (18) for creating a television signal with a predetermined time difference from the television signal from
) and a phase difference detection circuit (40, 42, 46, 58) that compares the synchronization signal of the television signal with this predetermined time difference.
, 66, 62) or (42, 44, 48, 60, 68,
64) A non-standard signal determination circuit comprising:

The present invention also provides delay means (18, 20) for delaying a television signal by one frame, a three-dimensional processing circuit (22) to which this television signal and a television signal delayed by one frame are input, and a three-dimensional processing circuit (22) for delaying the television signal by one frame. This is a non-standard signal determination circuit that includes a phase difference detection circuit (46) that compares the synchronization component of the signal and the television signal delayed by one frame.

Further, the present invention includes a circuit (66) that detects a phase difference in a synchronization signal between one frame of a television signal to determine non-standard, and a circuit (66) that detects a phase difference in a synchronization signal between one line of the television signal. a circuit (68) for determining non-standard by detecting whether or not the vertical synchronization period of the television signal is 262.5x horizontal synchronization period;
6) and three circuits (66) (68) (
an output circuit (70) that outputs a non-standard discrimination signal to the three-dimensional processing circuit (22) when even one output of the output circuit (56) is non-standard;
) is a non-standard signal determination circuit.

(N) Function In the present invention, the television signal A/D converted by the A/D converter (14) is transmitted to the delay means (18) or (18, 20).
Two correlated television signals (I
H and 2H1 or lH and 526H) signals are created, and these synchronization signals are compared to determine standard/non-standard.

Further, standard/non-standard is determined using the l-frame period difference signal created for three-dimensional processing.

In addition, non-standard judgment can be made by OR (
If even one item is determined to be non-standard, it is determined to be non-standard).

(f) Example An embodiment of the present invention will be described with reference to the drawings.

(10) is an input terminal to which an analog video signal is input. (12) is a burst PLL clock generation circuit synchronized with the burst of this video signal, and 4f. Outputs a clock signal with a frequency of (14) is an A/D converter which outputs an 8-bit digital video signal. (16
)(18) is a 910 clock delay element and operates as an IH delay element. (20) is a 910×524 clock delay element, which operates as a 524H delay element.

(22) is a well-known motion adaptive YC separation circuit (three-dimensional processing circuit). (23) is a motion detection circuit, (24) (2
6) (28) is an adder, (30) (32) is a subtracter, (
34) is a percentage multiplier, and (36) and (38) are mixing circuits in which the mixing ratio is controlled according to the amount of movement. (40)(42)(
44) is a sync separation circuit that outputs a sync signal containing horizontal and vertical components, and outputs a 1-bit sync separation signal.

(46) is an exclusive OR circuit, which here functions as an interframe phase difference detection circuit for detecting a mismatch in synchronization phase between frames. In other words, the two inputs to the phase difference detection circuit (46) are synchronized separated signals with a l-frame period difference separated from the IH delayed digital video signal and the 526H delayed video signal.

(48) is also an exclusive-OR circuit, and here it functions as an inter-line phase difference detection circuit for detecting mismatch in synchronization phase between lines. This phase difference detection circuit (48)
The two manual inputs are open and separated signals with a one-line period difference.

(50) is a vertical synchronization signal separation circuit. (52) is 2
62,5H delay element (] field delay circuit),
Delay the vertical synchronization signal by one field. Furthermore, this circuit (
52), for example, is reset by the vertical synchronization separation circuit (50), and the separately created 2f, cycle clock signal is sent to 525.
It may also be configured with a counter circuit that outputs a signal when counting. (54) is an exclusive OR circuit, which here functions as a phase difference detector for detecting mismatch in vertical synchronization phase between fields.

The circuits (46, 48, and 54) each determine whether the following equations hold true.

910X525XjF==4 f,.

910X f, = 4 f, c 2xfF=fv (56) is a launch circuit.

(58) and (60) are counter circuits. These counter circuits (58) and (60) respectively count clock signals when the outputs of the exclusive OR circuits (46) and (48) between one field are "present". (62) and (64) are reference level setting circuits. (66) and (68) are comparison latch circuits, and this comparison latch circuit performs a count operation by 1.
The reference level setting circuit (reads out every field period)
62) Compare with the reference level of (64) and output the determination result. After this determination, the counter circuits (58) and (60) are immediately reset and start counting again.

(70) is an AND circuit. This AND circuit (70)
The non-standard identification signal from is output to the three-dimensional processing circuit (22) to stop three-dimensional processing and perform in-field processing.

The above operation will be explained.

A video signal input from an input terminal (10) is converted into a digital signal by an A/D converter (14).

In addition, the burst PLL clock generation circuit (12) is
This clock signal is output to each part.

The digital signal is delayed by delay elements (16), (18), and (20). At this time, if the input video signal is a standard signal, each delay element (16) (18) (20)
524H is delayed.

The video signal is separated by synchronous separation circuits (40), (42), and (44).
Converted to a bit synchronization signal.

If the two synchronizing signals inputted to the phase difference detection circuit (46) are standard television signals, they are completely in-phase signals delayed by one frame, so there is no output. In other words, if there is an output, it is non-standard.

Similarly, if the two synchronization signals input to the phase difference detection circuit (48) are standard signals, the homosynchronous signal delayed by one line is completely in phase, so there is normally no output. still,
The output is present at the beginning and end of the equalization pulse in the vertical synchronization signal period, and the reference level of the reference level setting circuit (64) is set by including the count value for this period in advance. Incidentally, this may be done by detecting the vertical synchronizing signal period and stopping the operation of the counter circuit (60) during this period.

The counter circuits (58) and (60) operate the phase difference detection circuit (
46) If there is an output from (48), count the clock signal.

Then, at the end of this predetermined period, this count value and the reference level are compared by comparison latch circuits (66) and (68). In other words, the comparison latch circuit (66) determines that the frame is non-standard when the total amount of jitter between frames exceeds the reference level value at the end of a predetermined period, and outputs a low level signal until the next predetermined period elapses. .

The comparison launch circuit (68) determines that the line is non-standard when the total amount of jitter between lines exceeds the reference level value, and outputs a low level signal.

Further, the open signal is vertically separated by the same amount by a vertical synchronization separation circuit (50). Then, the phase of the signal delayed by 262.5H is compared with the phase detector (54). This phase detector detects field synchronization. Phase detection when 2・f,=fv is not the case! (54) outputs a signal, and the launch circuit (56) determines that it is non-standard and outputs a low level signal.

AND circuit (70) is circuit (66) (68) (56
') is at a low level (non-standard judgment signal), outputs a low-level signal (non-standard judgment signal) to control the processing of the three-dimensional Y/C separation circuit (22). Switch to internal processing.

In addition, (72) is a timer circuit, which is a one-time AND circuit (
70) When the output becomes low level, a low level signal is output for a predetermined period (for example, 1 second) regardless of the input signal to stabilize the output when the non-standard/standard discrimination output is unstable. inserted for.

Then, after this predetermined period has elapsed, the timer circuit (72)
If the input signal of \ is a high level signal, the timer circuit (72) outputs a high level signal, and if it is a low level signal, it outputs a low level signal again for a predetermined period.

In addition, when a - degree low level signal is input instead of this timer circuit (72), the reference level setting circuit (6
2) The reference level in (64) may be converted to a smaller value to increase the standard signal determination accuracy criterion. and,
When a high level signal is input, the reference level is returned to the original level, so that the determination has hysteresis characteristics.

Also, although the predetermined period of the counter circuit (5g) (60) may be created regardless of the vertical dosing signal, it is practically better to set it to an integer multiple of one field period (also, it is better to synchronize with the vertical dosing signal). For example, it is better to use l field or one frame brightness.

By adopting the method described below, burst PLL circuits and A
Regardless of the characteristics of the /D converter, it is possible to determine whether or not a digitized signal can be processed in 3D.
It is possible to verify the relative relationship between SC+IH and rv, rather than the absolute frequency such as 'SC+IH,rv. Moreover, summing the phase difference over a period (field or frame) has the effect of filtering out deviations from the standard signal such that sudden, instantaneous visual disturbances do not occur.

With this device, the (sc'-
It is possible to detect signals whose phases and frequencies are uncorrelated, burst discontinuous signals when the LD is stationary, non-increment signals from personal computers, etc., and received signals in extremely weak electric fields.

()) Effect of the invention According to claim 1.2.3.4, since the determination is made in the digital stage, the A/D converter (14), the parsing) PL
Non-standard determination can be made regardless of the characteristics of the L clock generation circuit (12).

According to claim 5, since the delay elements (18) and (20) for the three-dimensional processing circuit (22) are also used as delay elements for determination, the circuit is simplified.

According to claim 6, a plurality of determination circuits (66) (68) (
Since non-standard is judged based on the judgment result of 56),
More accurate judgments can be made.

[Brief explanation of drawings]

The drawings are diagrams showing one embodiment of the present invention. (12)... Clock generation circuit (burst PLL clock generation circuit), (14)... A/D converter, (1g) (20)... Delay means (delay element), (40
)(42)(44)...Synchronization separation circuit, (46)(4
8) Exclusive sheave OR circuit (phase difference detection circuit), (54) Exclusive sheave OR circuit (phase difference detector), (58) (60) Counter means (counter circuit)
, (66) (68)... Comparison circuit (comparison latch circuit)
, (22)... Three-dimensional processing circuit (motion adaptive YC separation circuit), (66)... Discrimination circuit (comparison latch circuit) (68
)...Discrimination circuit (comparison latch circuit) (56)...
- Discrimination circuit (latch circuit) (70)...output circuit (AND circuit).

Claims (6)

[Claims] (1) A clock generation circuit (1) that creates a clock signal synchronized with the color burst of the input television signal.
2), an A/D converter (14) that converts the television signal into digital, and a delay unit that creates a television signal with a predetermined time difference from the television signal from the A/D converter (14). (18) A non-standard signal determination circuit comprising: (20); and a phase difference detection circuit that compares synchronization signals of television signals with a predetermined time difference. (2) Claim 1, wherein the predetermined time difference is one frame period.
Non-standard signal judgment circuit. (3) The non-standard signal determination circuit according to claim 1, wherein the predetermined period is one line period. (4) The phase difference detection circuit includes a synchronous separation circuit (42) (
40, 44) and exclusive-or circuit (46) (
48), and counter means (58) for integrating the outputs of the exclusive-OR circuits (46) and (48) for a predetermined period of time.
(60) and comparison circuits (66) (6) that compare the count values of the counter means (58) (60) with the reference level.
8). The non-standard signal determination circuit according to claim 1, comprising: (5) delay means (18, 20) for delaying the television signal by one frame; a three-dimensional processing circuit (22) to which this television signal and the television signal delayed by one frame are input; the television signal and A phase difference detection circuit (46) that compares the synchronization components of a television signal delayed by one frame.
A non-standard signal determination circuit comprising; (6) a circuit (66) that detects a phase difference in a synchronization signal between one frame of a television signal to determine non-standard; and a circuit (66) that detects a phase difference in a synchronization signal between one line of the television signal and determines non-standard a circuit (68) for determining standard; a circuit (56) for determining non-standard by detecting whether the vertical synchronization period of the television signal is 262.5×horizontal synchronization period; A non-standard signal determination device comprising an output circuit (70) that outputs a non-standard discrimination signal to a three-dimensional processing circuit (22) when even one of the outputs of the three circuits (66, 68, and 56) is non-standard. circuit.