JPH0212693A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption, to decrease transient current and to reduce the number of precharge MOS transistors (TRs) for high circuit integration by precharging only a bit line selected alternatively from an output line used in common by each bit line via a selection MOS TR. CONSTITUTION:A precharge power supply Vcc for bit line precharge is connected to an output line 9 for data transfer used in common by bit lines B1-Bn selected alternatively by a selective MOS TR 8 via a precharge MOS TR 21. A precharge voltage applied via the precharge MOS TR 21 is applied only to a bit line selected via the selection MOS TR 8 selected alternatively to apply bit line precharge. Thus, the precharge power consumption is reduced and the transient current in the precharge and discharge is reduced and the number of precharge MOS TRs is saved to attain high circuit integration.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor memory device of a dynamic operation type having a MOS transistor configuration, and more specifically, relates to a bit line precharge R bucket of the semiconductor memory device, and is capable of reducing power consumption for precharging, precharging and Enables reduction of transient current during discharge, as well as MOS for precharging
In order to reduce the number of transistors and enable high integration, the selection MOS transistors connected to each bit line are selectively made conductive to select one of the bit lines. In a semiconductor memory device that outputs data to an output line shared by each bit line, a precharge MOS is used to supply a precharge power supply for bit line precharging to the output line.
The configuration is such that the bit line is precharged by being connected through a transistor.

[Industrial Field of Application] The present invention relates to a dynamic operation type semiconductor memory device having a MOS transistor configuration, and more particularly to a bit line precharge a top of the semiconductor memory device.

In a dynamic operation type semiconductor memory device, when reading data from each memory cell, the bit line is precharged and then discharged according to the memory cell data, and the state of the bit line corresponding to the memory cell to be read at that time is changed to that memory cell. It is read out as data. Therefore, this type of semiconductor memory device is provided with a bit line precharge mechanism for this purpose.

[Prior Art] Conventionally, in a dynamic operation type semiconductor memory device having a MOS transistor configuration, for example, a dynamic ROM circuit as shown in FIG. is enhancement type MOS transistor 2 for discharge.
(Hereinafter, MOS transistor is simply referred to as MOSTr)
A memory cell is connected in series with a predetermined number of enhancement type MO3Tr3s connected in series. The gates of each MO3Tr3 except for the discharge MOSTr2 are connected to the word line group W extending from the word line decoder 4.
It is connected to corresponding word lines WO to WV3 inside.

Further, the gate of each MO3Tr2 for discharge is connected to the discharge signal input line 5.

The SOS of an enhancement type MO3Tr6 for precharging is connected to one end of each of the bit lines 81 to Bn, and the drains of the MOSTr6 are respectively connected to a precharge power supply VCC. The gate of each MO3Tr 6 for precharging is connected to a precharge signal input line 7, and the precharge signal Φ1 input to the input line 7 and the discharge signal Φ2 input to the discharge signal input line 5 are shown in FIG. As shown, the logical levels are opposite to each other.

Then, the logic level of the precharge signal Φ1 is a positive potential (referred to as H level), and the discharge signal Φ2 is at an O level.
When the potential (referred to as L level), each M for precharging
O3Tr6 is conductive and each MO3Tr for discharge
2 becomes non-conductive.

As a result, all bit lines 81-Bn are precharged to I level.

In the bit line decoder 1, each bit line 81 to B
Enhancement type M OS for selection corresponding to n
T' r 8 is connected, and each gate is connected to a corresponding select signal input line 81 to Sn. or,
Each MO3Tr 8 for selection is connected to one output line 9 shared by each bit line 1 to Bn. The output line 9 is an enhancement type MO3T connected to a data bus 13 via an inverter circuit 10, a NAND circuit 11 which inputs a read signal Φ3 to one input terminal, and an inverter circuit 12.
Connected to r14. 15 is an enhancement type MOS for precharging the data bus 13.
It is 7rr.

In the dynamic ROM circuit constructed in this way, each data D1 to D1 shown by the chain line in FIG.
The sequential reading of data D6 is carried out according to the timing chart shown in FIG. 3, but the case of reading data D1 will now be described.

Now, when the precharge signal Φ1 is at the 1■ level and the discharge signal Φ2 is at the L level, each M for precharging
O8Tr6 is conductive, and each MO3Tr for discharge
2 becomes non-conductive, and all bit lines 81 to Bn are precharged. Subsequently, when the BRITISH signal Φ1 is at the L level and the discharge signal Φ2 is inverted to the H level,
Each MO8Tr6 for pre-charging becomes non-conductive, and each MO3Tr2 for discharging becomes conductive and discharge is performed.

Address signal AWO input to each word line WO to WV3 during this precharge and discharge
-A wy3 is word line w1. WYO L level A1
Kuresu 1 Otsu No. 141. Except for AW■0, the select signals ΦS1 to Φsn input to each bit select signal input line 81 to Sn are at the H level, except for the select signal φS1 at the H level of the bit select signal input line S1. level.

Therefore, bit line B1 is selected and data D1
Since MOST r 3 is in a non-conductive state, the bit line B1 is not discharged and maintains the high level.
The H level state is output to the output line 9 as data D1.

[Problems to be Solved by the Invention] However, in this dynamic ROM circuit, every time the precharge signal Φ1 goes to H level, all bit lines 81 to Bn, that is, unnecessary bits other than the selected one bit line are Since all lines are precharged at the same time, the power consumption for precharging was large. or,
Each bit line that is unnecessarily precharged has a problem in that unnecessary transient currents are generated during precharging and discharging.

Also, since each bit line 81 to Bn is precharged at the same time, MO3 for precharging is used for the number of bit lines.
Since such a dynamic operation type semiconductor memory device requires a transistor, it is also disadvantageous in achieving high integration.

Therefore, it is conceivable to provide a selection circuit on the side facing the bit line decoder 1 across the bit line, and use the selection circuit to selectively select and precharge the bit line. However, in this case, a selection circuit must be newly provided, which poses a problem in achieving high integration.

An object of the present invention has been made to solve the above problems, and it is possible to reduce power consumption for precharging, reduce transient current during precharging and discharging, and to reduce MO3Trl& for precharging. An object of the present invention is to provide a semiconductor memory device that can be reduced in size and highly integrated.

[Means for Solving the Problems 1] In order to achieve the above object, the semiconductor memory device of the present invention includes an output line for data transfer that is shared by each bit line that is selectively selected by a selection MOS transistor. A precharge power supply for bit line precharging is connected to the bit line precharging through a precharging MOS transistor. The precharge voltage applied via this precharge MOS transistor is applied to one selective MOS transistor selected alternatively.
Bit line precharging is performed by applying the voltage only to the selected bit line through the transistor.

[Operation: The precharge voltage is applied only to the selected bit line through one selection MOS transistor alternatively selected from among the selection MOS transistors provided for each bit line. From, MO3 for precharging
) Only one transistor is required.

Furthermore, since bit lines other than those selected for data reading are not precharged, power consumption is reduced, and unnecessary bit lines do not generate excessive a current that occurs during precharging and discharging.

[Embodiment] An embodiment in which the present invention is applied to a dynamic ROM circuit will be described below with reference to FIG.

Since this embodiment is characterized by the precharge mechanism of the dynamic ROM circuit, the precharge mechanism will be explained in detail and compared to the conventional dynamic ROM circuit shown in FIG.
Components that are the same as the M circuit are given the same symbols and detailed explanations are omitted for the sake of convenience.

In FIG. 1, the bit line decoder 1 has a selection MOS'[
' r 8 are provided respectively, and each MO3 'T'
r8 is connected to one output line 9 shared by each bit line 81 to Bn. The gate of each MO3Tr8 is connected to the corresponding select signal input line S1 to Sn.

Then, each MOS'
r' r 8 is alternatively selected and one is made conductive to electrically connect the bit line corresponding to the selected MOS 'I' r to the output line 9 .

Further, the source of an enhancement type MO3Tr 21 for precharging is connected to the recording output line 9, and the MO3T
The drain of r21 is connected to the precharge power supply Vcc. The precharge 1S number Φ1 is input to the gate of this MO3Tr21 for gridage.

Next, the operation of the dynamic ROM configured as described above is expressed by each data D1 to D6 shown by the chain lines in FIG.
The following describes the reading operation. In addition, each data D1~
Each signal when reading D6 is the same as the conventional timing chart shown in FIG. 3, so for convenience of explanation, the explanation will be made according to this timing chart.

When reading data D1, in FIG.
1. Address signal A141°A at L level on WyO
0 is connected to other word lines WO, W2, W3, WV
Address signal AWO, A14 at H level from 1 to Vvy3
2. A113, AJV1 to A W73 are input, and the H level select signal ΦS1 is input only to the select signal input line S1, the selection MO3Tr8 corresponding to the bit line B1 becomes conductive, and only the bit line B1 is output. It is electrically connected to line 9.

In this state, the precharge signal Φ1 becomes H level, and when the precharge MO3T'r21 becomes conductive, a precharge voltage is applied via the bit line decoder 1. That is, only the bit line B1 is precharged via the output line 9 and the selection MO3Tr 8 which is in a conductive state.

Precharge signal Φ1 goes from H level to L level,
When the discharge signal Φ2 changes from the L level to the H level, the MO8Tr2 for discharge becomes conductive. At this time, since MO3Tr3 of data D1 is non-conductive, bit line B1 is not discharged and is held at I] level, and the output of output line 9 also becomes H level. This H level is output as data D1 via the inverter circuit 10 and the NAND circuit 11.

Next, when reading data D2, word line W2,
The address signal AlA2.wyo is at L level. AWLL
o is the other word line WO, Wl, W3, Wy1
to wy3, the address signal A140. A.W.
2. A143. AWV1 to AWy3 are input, and the select signal ΦS1 of ()-Level is input only to the select signal input line S1, and bit llB1 is input.
The selection MO3'r'r8 corresponding to the bit line B1 is electrically connected to the output line 9.

In this state, when the precharge signal Φ1 becomes H level, only the bit line B1 is precharged via the output line 9 and the selection MOST r 8 which is in the conductive state, as described above.

Precharge signal Φ1 goes from H level to L level,
When the discharge signal Φ2 changes from the L level to the H level, the discharge MOSTr2 becomes conductive. At this time, the circuit for data D2 is always conductive, so bit line B
1 is discharged to the L level through the MO3Tr2 for discharging, and the output of the output line 9 also becomes the L level.

This L level is output as data D2.

Next, when reading data D3, word line W3,
Address signal AW3.Wyo at L level. AWyO is H to other word lines WQ~W2, WVl~Wy3.
Level address signal AWO~AW2゜Awyl~A
At the same time that Wy3 is input, the select signal Φs2 at the T level is also input only to the select signal input 'dAS2, the selection MO3Tr8 corresponding to the bit line B2 becomes conductive, and only the bit line B2 becomes the output line 9. electrically connected.

Along with this state, when the precharge signal Φ1 becomes the level (), the output line 9 and the selection MO3Tr in the conductive state
Only the bit line B2 is precharged via the bit line B2.

Precharge signal Φ1 goes from H level to L level,
When the discharge signal Φ2 changes from the L level to the H level, the MO3Tr2 for discharge becomes conductive. At this time, the circuit for data D3 is always conductive, so bit line B
2 is discharged to the L level through the MO3Tr2 for discharging, and the output of the output line 9 also becomes the L level.

Then, this L level is output as data D3.

Thereafter, in the same way, when reading data D4, only the bit line B2 is used, and when reading data D5, only the bit line B2 is used.
3, and when reading data D6, only bit line Bn is precharged, and the data D6 is read.
4, D5, and D6 are read out sequentially.

In this way, in this embodiment, the bit line decoder 1
Since the bit line is precharged via the selection MO3Tr 8 which is selectively selected from the output line 9 of The bit line is not precharged, so no wasteful precharge power is consumed, and power consumption can be reduced.

Also, the overload that occurs during precharging and discharging
Since the at current is generated only in the selected bit line, it is possible to reduce the transient current as a whole.

Moreover, precharging can be done using existing bit line decoder 1.
Since this is done via the MO3Tr that is selectively selected from among the selection MOST r8 in the middle, only one MO8Tr21 is required for precharging, and it is not necessary to provide it for each bit line as in the conventional case, or to Compared to newly providing a selection circuit for precharging the bit line, the number of elements for precharging can be significantly reduced, and higher integration can be achieved accordingly.

It should be noted that the present invention is not limited to this embodiment, and can of course be embodied in, for example, a dynamic operation type semiconductor memory device having a memory cell structure different from the memory cell structure shown in the embodiment.

[Effects of the Invention] As detailed above, according to the present invention, only the bit line selectively selected from the output line shared by each bit line via the selection MOS transistor is precharged. Therefore, it is possible to reduce the power consumption for precharging and reduce the transient current, and the M for precharging can be reduced.
This has the advantage of reducing the number of OS transistors and achieving higher integration.

[Brief explanation of the drawing]

FIG. 1 is a dynamic ROM circuit diagram showing an embodiment of the present invention, FIG. 2 is a conventional dynamic ROM circuit diagram, and FIG. 3 is data D1 in the dynamic ROM circuit.
It is a timing chart diagram for reading ~D6.

Claims (1)

[Claims] 1. Selectively conduct each selection MOS transistor (8) connected to each bit line (B1 to Bn),
In a semiconductor memory device that selects one of each bit line (B1 to Bn) and outputs data to an output line (9) shared by each bit line, the bit line precharge is used for the output line (9). 1. A semiconductor memory device characterized in that a bit line precharge is performed by connecting a precharge power supply (Vcc) of a precharge power source (Vcc) via a precharge MOS transistor (21).