JPH02123912A - Switch controller - Google Patents

Abstract

PURPOSE:To conduct a test while keeping monitoring by detecting a zero phase current and voltage to provide switching circuits respectively to two circuits making a signal treatment, and inputting either a test current or voltage from a test signal generator. CONSTITUTION:A zero phase current of a power system 1 is detected by a CT2, and it is inputted to an overinput protective circuit 22 through an input transformer 21. A zero phase voltage is detected to input to an overinput protective circuit 32 through transformers 3a and 31. The protective circuits 22 and 32 are separately inputted to a CPU 4 through test switching circuits 23 and 33, filters 24 and 34, effective value smoothing circuits 25 and 35, level convention circuits 26 and 36, and phase pulse circuits 27 and 37. By a command of the CPU 4, a test signal generation circuit 9 is started, either the test switching circuit 23 or 33 is switched to input the test signal to a signal treatment circuit 20 or 30, and the result is displayed on a diagnostic circuit 10. According to the constitution, while keeping monitoring either current or voltage, a test for the other is conducted, and a quick action against a fault curing the test is taken.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to switch control devices, particularly SOG (Storage Overc) having a self-diagnosis function.
urrcntG round ) type opening/closing control device.

(b) Conventional technology Generally, the device is connected to a three-phase load, detects excessive current and ground fault current, and when the ground fault current exceeds a predetermined level, current is sent to the trip coil upon detection, and the switch is disconnected. There is also an SOG type switch control device which, when an overcurrent is detected, causes a current to flow through a trip coil to disconnect the switch on the condition that the power is cut off.

Conventionally, in this type of switch control device, a test switch is installed to perform tests, and the operator operates the test switch with the power supply cut off and inputs a simulated signal. was.

(C) LL and Q to be solved by the invention In the conventional switch control device described above, when conducting a test, the operator must always press the test switch, and the test cannot be performed when the operator is not present. There is a problem in that it is time-consuming because it always requires an operator's operation. Furthermore, since the power supply is cut off during the test, there is a problem in that if an accident occurs in the power system during the test, it cannot be confirmed.

The present invention was made in view of the above-mentioned problems, and an object of the present invention is to provide a switch control device that can perform tests without an operator present and that can monitor the power system status even during the test. It is said that

(d) Means and operation for solving the problems The switch control device of the present invention includes a zero-sequence current detector that detects the zero-sequence current of a three-phase bus, and a a first signal processing circuit that processes signals; a zero-sequence voltage detector that detects the zero-sequence voltage of the three-phase bus; and a second signal processing circuit that receives signals from the zero-sequence voltage detector and processes the signals. and a means for determining whether or not the outputs of the first signal processing circuit and the second signal processing circuit are each greater than or equal to a preset value, and whether or not the determination result by the discrimination means is both greater than or equal to the predetermined value. means for shutting off the switch of the bus bar in response to a determination output that the busbar switch is disconnected, the test signal generation means for generating a test signal for self-diagnosis, and a current self-test command and a voltage self-test in a time-sharing manner. test command output means for outputting a command; and a first switch for inputting the test signal into a first signal processing circuit instead of the output from the zero-sequence current detector in response to the voltage self-test command. and a second switching circuit for inputting the test signal to a second signal processing circuit instead of the output from the zero-phase voltage detector in response to the voltage self-test command.

The second switch control device normally determines whether the outputs of the first signal processing circuit and the second signal processing circuit are each higher than a set value, and if not, a ground fault occurs. Continue operation as is. If the re-outputs are all above the set value, it is assumed that a ground fault has occurred, and the bus switch is disconnected to turn off the power.

Next, when the timing to perform a self-test is reached, the test command output means first outputs, for example, a current self-test command, and in response to this, the first switching circuit converts the input from the zero-phase current detector into a test signal. The signal is then manually input to the first signal processing circuit. The output of this first signal processing circuit is used as a zero-sequence current detection signal for self-test. On the other hand, the second switching circuit at this point remains unchanged, and the detected voltage of the zero-phase voltage detector is input to the second signal processing circuit. The output of this second signal processing circuit is a normal monitoring signal. When a voltage self-test command is output following the current self-test command, in response, the second switching circuit switches the input from the zero-phase voltage detector to the test signal, and performs the second signal processing. input to the circuit. The output of this second signal processing circuit is used as a zero-phase voltage detection signal for self-test. In the first switching circuit at this point, the detected current of the zero-phase current generator is input to the first signal processing circuit. The output of this first signal processing circuit is i(1), which is a constant monitoring signal. If the voltage signal or zero-sequence current signal value of the first signal processing circuit exceeds the set value when deriving the zero-sequence voltage for self-test from the second signal processing circuit and during test processing, priority is given to the self-test. For example, if the zero-sequence voltage detector exceeds the setting point during current self-test acquisition, the next step is to check the output from the zero-sequence current detector.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 1 is a block diagram of an SOG type switch control device in which the present invention is implemented. In the figure, a 6600V power supply system 1 is connected to a zero-sequence current detector (zero-sequence current transformer) 2 and a zero-sequence voltage detector 3, which detect zero-sequence current and zero-sequence voltage, respectively. It looks like this. The zero-sequence current detected by the zero-sequence current detector 2 is converted into a voltage signal,
The signal is input to the CPU 4 via the input quadrature transformer 21, the overload protection circuit 22, the test switching circuit 23, the filter circuit 24, the effective value smoothing circuit 25, and the level conversion circuit 2G. Similarly, the zero-phase voltage detected by the zero-phase voltage detector 3 is transmitted to the voltage converter 3a, the input voltage transformer 31, the over-input protection circuit 32, the test switching circuit 33, the filter 34, the effective value smoothing circuit 35, and the level converter 3a. The circuit 36 is input to the CPU 4.

The over-input protection circuits 22 and 32 are circuits that have the function of suppressing the detected zero-sequence current and zero-sequence voltage when they exceed the levels, and the test switching circuits 23 and 33 protect against over-input during normal monitoring. The filter circuit 2 filters the zero-sequence current detection signal and zero-sequence voltage detection signal from the protection circuit 22.32.
4.34, and a test signal is input to the filter circuit 24.34 instead of the detection signal during the self-test. Details of the switching circuits 23 and 33 will be described later. Filter circuits 24 and 34 are provided to remove harmonic components. The effective value smoothing circuit 25.35 is a circuit for converting the detection signal etc. into a DC component, and the level conversion circuit 26.3
6 is a circuit for converting into a signal suitable for import into the CPU 4, and phase pulse circuits 27 and 37 convert pulse signals corresponding to the zero cross points of the outputs of the filter circuits 24 and 34 into phase pulse signals, respectively. It is inputted to the CPU 4 as a signal and used when detecting a phase difference in each of the zero-phase current detection system and the zero-phase voltage detection system.

The setting circuit 5 has a setting value of zero-sequence current I0, zero-sequence current ■. This is a circuit for setting the setting value and setting time T of D.
The C test switch 6a is a manual switch for conducting a ground fault test, and the SOHK test switch 6b is a manual switch for conducting an overcurrent test. The display section 7 includes a V0 level display, a power supply display, and a forecast display. The output unit 8 is equipped with a DC display due to ground fault eruption and an SO display due to overcurrent, and also has a relay for tripping in the event of a ground fault, a relay for tripping in the event of overcurrent, a relay for forecasting, an abnormality relay, etc. It is equipped with

The CPU 4 also includes a test signal generation circuit 9 and a test circuit.
A diagnostic circuit 10 is attached. The test signal generation circuit 9 is 1
, for example, a four-step self-test current signal r0, and a self-test voltage signal ■. occurs.

Current signal! . is the voltage signal ■ to the test switching circuit 23. are respectively input to the test switching circuit 33.

The test circuit/diagnostic circuit 10 is a general term for various diagnostic/test functions executed by the CPU 4, such as a constant voltage check function, a contact check function, a TC check function, and an inertia function check.

In addition, this switch control device includes a filter circuit 11, a constant voltage circuit 12, and constant voltage level conversion circuits 13 and 14 as its own power supply section.

Note that a commercial power supply voltage is applied to the terminals P+ and Pz, and a trip coil for interrupting the switch of the power supply system 1 is connected between the terminals V, , and V. The TC detection circuit 15 is a circuit for detecting that a trip coil is connected to the terminals V, VC, and VC.

FIG. 2 is a circuit diagram showing specific circuits of the test switching circuit and the test signal generation circuit. In the figure, a four-stage self-test current signal ■ is sent from the CPU 4. 9, ■. 2, ro3, ■
. 4 and a 4-step self-test voltage signal■. 1. ■. 2, ■
. 3.■. 4 is output. Current signal ■. 1 is high and other I. 2. When TO3 and ro4 are low, resistor R1
A voltage determined by the voltage division ratio of and Rot is input to the test switching circuit 23 via the capacitor COI. Other ■. 2.I
03 and T 04 are considered to be 1 high, and each r. 2, L3, ■. 4 is input to the test switching circuit 23. Voltage signal VOI, V
OZ, v03, and VO4 are also selected in exactly the same way, and the corresponding voltages, for example, V. 2 is selectively output, a voltage determined by the voltage division ratio of the resistor R1□ and Roz is input to the test switching circuit 33 via the capacitor CO2.

Further, the CPU 4 outputs a self-test command signal T at regular intervals. And this self-test command signal T.

is the self-test current command TSI that is output in a time-division manner.

and a self-test voltage command TSV.

When these self-test commands TSIO (or TSVO) are input, the switch element T r + (T rv ) of the test switching circuit 23 (33) is turned off and the detection signal from the over-input protection circuit 22 (32) is filtered. circuit 24
(34) cannot be done manually. And self-test directive TS
1. While (TSV.) is being input, the self-test signal ■. (V,) is input to the test switching circuit 23 (33). Therefore, during a self-test, one of the signal processing circuits for the current system and the voltage system derives a detection signal, and the other derives a test signal and inputs each to the CPU 4.

Next, with reference to the flowchart shown in FIG. 3, the self-test processing operation of the apparatus of the above embodiment will be explained.

When entering the self-test timing that comes every predetermined period, first the I0 self-test current command TS1. Output [Step S
T (hereinafter abbreviated as ST) 1], as well as the current self-test signal ■. is output (Sr1).

Then, ■ from the level conversion circuit 26. In addition to taking in analog data (Sr1), from the level conversion circuit 36
. Take in analog data (Sr1). Also ■. ,v
Detect the phase of o (Sr5). Then, it is determined whether the current I0 is the operating value, that is, whether it is greater than or equal to the set value (Sr1)
. If the test signal is a small value that has not reached the operating value, the determination is No, and the process moves to 5T13.

Determine whether it is a self-test or not. Here, since the determination is YES, data analysis is performed in accordance with the purpose of the test (ST15), and the process moves to the next process (ST17).

In ST6 above, ■. If is greater than the set value, the judgment is YES, and Sr7 is ■. Determine whether it is a self-test. Since the judgment here is YES, the next step is Sr1, and the voltage V is applied. It is determined whether or not is an operating value, that is, greater than or equal to a set value. If it is smaller than the set value, the process moves to 5T13 without any particular problem and the same processing as above is performed. However, in Sr1, ■. If is greater than the set value, the detected voltage ■ from zero-phase voltage detection '2'i3. is greater than the set value, and in this case, there is a high possibility that a ground fault will occur, so ∎ o Self-test should be canceled (5T9) and return to Sr1. Then, I0 and V0 analog data are taken in again (Sr1.5T4). The current I0 in this case is the detection current of the zero-phase current detector 2, and the voltage V
0 is the detection voltage of the zero-phase voltage detector. As a result ST6
In the current■. is also an operating value, the determination is YES, ST7
If the judgment is NO, proceed to 5TIO. Here, the judgment of 5TIO's ■o self-test is also No, therefore, 5TIO
12, it is determined whether or not the V0 operating value is reached. Here again,
If vo is also greater than or equal to the set value, the process moves to phase determination. After returning from Sr9 to Sr1, the current ■ in Sr1.

is not an operating value or I. is the operating value, but ■
. If is not the operating value, the process moves to 5T13. here 5
■ of TI3. Self-examination or ■ of S T 1.4. The determination as to whether it is a self-test is No, and the process moves to the next step in 5T17.

In addition, Io and V in the above example. All self-test signals have 4 stages To,,"' TO4, vo1,...,V
64, and four outputs are output individually from the CPU 4, but the stages of both signals are not limited to this.
Further, the signal output from the CPU 4 may also be coded.

(F) Effects of the Invention According to this invention, the first switching circuit is connected between the output of the zero-phase current detector and the first signal processing circuit, and the first switching circuit is connected between the output of the zero-phase voltage detector and the second signal processing circuit. On the other hand, when the test signal from the circuit that generates the test signal is input to the first and second switching circuits and a self-test is performed, only one switching circuit is operated and the test signal is processed. Since the detection signal is input into one circuit and the other signal processing circuit is constantly monitored, if a ground fault occurs even during a test, it can be dealt with immediately.

In addition, by periodically outputting a self-test command, a self-test can be performed without requiring the operator to operate a switch, and a detailed test check can be performed without the operator having to go to the site.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an SOC type switch control device showing an embodiment of the present invention, and FIG. 2 specifically shows a test switching circuit and a test signal generation circuit that constitute the same switch control device. The circuit diagram and FIG. 3 are flowcharts for explaining the operation of the opening/closing control device. l: power supply system, 2: zero-phase current detector, 3: zero-phase voltage detector, 4: CPU, 9: test signal generation circuit, 20: first signal processing circuit, 23: first test switching circuit, 30: Second signal processing circuit, 33: Second test switching circuit. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura

Claims (1)

[Claims] (1) A zero-phase current detector that detects the zero-phase current of the three-phase bus; a first signal processing circuit that receives and processes signals from the zero-phase current detector; and a zero-phase current detector that detects the zero-phase current of the three-phase bus; a zero-phase voltage detector that detects voltage; a second signal processing circuit that receives a signal from the zero-phase voltage detector and processes the signal;
means for determining whether the outputs of the signal processing circuit and the second signal processing circuit are each greater than or equal to a predetermined value, and determining that the results of the discrimination by the discrimination means are both greater than or equal to the predetermined value; A switch control device including means for shutting off the busbar switch according to an output, a test signal generating means for generating a test signal for self-diagnosis;
test command output means for outputting a current self-test command and a voltage self-test command in a time-division manner; a first switching circuit that inputs the test signal to a signal processing circuit; and a second signal processing circuit that inputs the test signal in place of the output from the zero-phase voltage detector in response to the voltage self-test command; a second switching circuit, which performs a self-test using the output of either the first or second signal processing circuit;
A switch control device characterized in that input monitoring is performed using the other output.