JPH02118739A - Data processor - Google Patents

Abstract

PURPOSE:To make the title processor fit to the debug of software by permitting an information conversion means converting internal information into external information and outputting it to give the instruction of an access timing to outside when it accesses an external memory and sets conversion information in a conversion table. CONSTITUTION:When the external memory is accessed to the information conversion means and conversion information is set, an instruction signal instructing the access timing to outside is outputted from a data processor to outside. Namely, the timing of memory access can be identified by the instruction signal. Consequently, a table for accumulating conversion information which is set in the information conversion means outside in response to the instruction signal and for inversely converting information outputted outside from the information conversion means into internal information based on accumulated information can be generated. Thus, information which has been converted and outputted outside is inversely converted and internal information before conversion can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having a built-in information conversion means, such as a microprocessor having a built-in address conversion means. Concerning effective techniques applied to software debugging in processing systems.

[Prior art]

As application programs and control programs become more sophisticated and multi-functional, the address space of data processing systems that execute such programs is becoming increasingly large. In addition, in data processing systems that perform large-scale multitasking processing, it is necessary to prevent programs and data from being destroyed by unauthorized access, and to protect programs and data from unauthorized access. is desired. For these reasons, a virtual memory method is adopted in data processing systems. When this virtual storage method is adopted, physical addresses and logical An address translation mechanism such as a memory management unit with an address translation buffer indicating correspondence with addresses is utilized.

By the way, when such an address conversion mechanism is built into a microprocessor, the microprocessor outputs a physical address to the outside of the microprocessor, and does not directly output a logical address. Therefore, the logical addresses required when debugging the software of a data processing system equipped with such a microprocessor cannot be directly monitored outside the microprocessor.

With this in mind, in order to debug software in the data processing system as described above, for example, the PloL and P2O3
There is a method as described in

The method described in this document will be briefly described below. In other words, in addition to a microprocessor as an actual chip that has an address conversion mechanism and outputs the physical address converted by this address conversion mechanism, there is also a microprocessor dedicated to planning that can output the logical address before address conversion to the outside. Prepare each and operate these differentially.

While performing emulation, logical addresses can be stored as trace information along with each stray path information and control information.

[Problem to be solved by the invention]

However, when debugging the software of a data processing system that includes a microprocessor with a built-in address translation mechanism, a special evaluation-only microprocessor such as the one described above that can output logical addresses to the outside of the microprocessor is used. , such a special microprocessor is newly required. Furthermore, such an evaluation-dedicated processor must be operated in parallel with a microprocessor serving as a real chip that outputs physical addresses, which complicates the circuit configuration of the emulator and its control operation.

An object of the present invention is to provide a complete data processing device suitable for motion analysis.

Another object of the present invention is to provide a microprocessor suitable for software debugging.

Another object of the present invention is to
The objective is to provide a microprocessor suitable for software debugging.

Another object of the present invention is to pressure data so that corresponding internal information can be obtained based on the converted information given to the outside without directly giving the internal information before conversion by the information conversion means to the outside. Our goal is to provide processing electrical manufacturing.

Another object of the present invention is to provide a data processing system in which a microprocessor can be evaluated without a special evaluation microprocessor.

Another object of the present invention is to provide a data processing system that is easy to configure.

The above and other objects and novel features of the present invention Vi,
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

It is equipped with a conversion table that stores conversion information in a rewritable state, including external correspondence information such as physical address information supplied from external memory, and refers to this conversion table to convert internal information such as logical addresses to physical A data processing device incorporating information conversion means such as an address conversion mechanism that converts into external information such as an address and outputs it, the information conversion means accessing an external memory and setting conversion information in a conversion table. When the access timing is to be accessed, an instruction signal can be outputted to externally instruct the access timing. The information conversion means such as the address conversion mechanism described above is, for example, a memory management unit having an address conversion buffer.

[Effect]

According to the above means, when conversion information is set in an information conversion means such as an address conversion mechanism by accessing an external memory, an instruction signal for instructing the access timing to the outside is sent from the data processing device. It is output to the outside. The timing of memory access performed to set conversion information in the information conversion means can be identified by this instruction signal. In response to this instruction signal, information including the conversion information set in the information conversion means is stored externally, and based on the information stored externally, the physical information is output from the information conversion means to the outside. It is possible to create a table for converting translated information such as addresses back to internal information such as logical addresses. As a result, the internal information before conversion by the information conversion means is not directly output to the outside of the data processing device, and the trace results of the converted information output to the outside are inversely converted.
You can get internal information before it is converted.

Furthermore, since the logical address is not directly output to the outside, it is possible to prevent the number of external terminals of the data processing device from increasing significantly.

〔Example〕

FIG. 1 shows a block diagram of a data processing system including a data processor which is an embodiment of a data processing apparatus according to the present invention.

The configuration of the data processing system shown in FIG. 1 is a first configuration of a system for debugging a user system developed by a user. In the figure, when debugging a user system, a data processor 1 is installed in the user system instead of a microprocessor (target processor) that should be originally installed in the user system, and serves as an Emmy Laser gross processor for the target processor. It is. Although not particularly limited, in this embodiment, the emulation processor is not placed on the user system side but on the emulator side, and is coupled to the user system via a cable.

The main memo IJ 10 is, but is not particularly limited to, a memory included in a user system or a substitute memory included in an emulator. In FIG. 1, a data processor 1, an emulator 20. and main memo IJ 10
A data bus DB and a here address path AB that interconnect the
The interface cables connecting the emulator and the user system and the system bus within the user system are shown without distinction, and the data processor 1. The connection relationship between the emulator 2° and the main memory 10 is shown.

Although not particularly limited, the main memo IJ 10 is mainly composed of a plurality of semiconductor memory devices.

The data processor 1 (microprocessor) shown in FIG. 1 is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited. That is, each circuit block surrounded by a two-dot broken line is formed on one semiconductor substrate using semiconductor integrated circuit technology.

This data processor 1 includes, but is not limited to, an instruction 7 for prefetching macro instructions from the main memory 10.
an instruction decode unit 3 that decodes the operation code of the fetched 7'E macro instruction;
A control unit 4 reads a series of microinstructions based on address information etc. output from the instruction decoding unit 3 and generates various control signals based on this, and a control unit 4 generates various control signals based on the control signals output from the control unit 4. ,
an execution unit 5 that performs arithmetic processing on operands in macro instructions; an external memory 10f; a memory management unit 7 that converts addresses when accessing; It includes an input/output control unit 6 that performs input/output control.

The memory management unit 7 converts the logical address (virtual address) LADR8 included in the address specification field in the macro instruction etched by the instruction etching unit 2 to the physical address (although not limited to % busyness).
It has a conversion table such as an address conversion buffer 8 for converting (actual address) PADR8&C and outputting the result.

Although not particularly limited, the memory management unit 7 of this embodiment
In addition to the above-mentioned address translation function, the memory also has a protection function for protecting the external memory from unauthorized access. That is, when accessing the external memory, it is checked whether the access is to a storage area that is permitted, and, for example, a portion other than the storage area preset in the memory management unit 7 is illegally accessed. This is to prevent this from happening.

The logical address space of the data processor 1 of this embodiment is divided into n sections, although not particularly limited, and each section is further divided into n page frames.

The above logical address LADR8 is not particularly limited, but
As shown in FIG. 2, there is a section index SX for specifying a predetermined section number from a plurality of sections, and a page index P for specifying a predetermined page frame number from a plurality of page frames.
It is made up of X, offsera) OT and K that indicate the position from the beginning of the specified page frame to a predetermined address. Main memory 10K Fi% Section table 8T and page tape A/A for address conversion
The PTs (PT, . . . , PTn) are formed in advance by, for example, a program. Logical address LADR8
K: The above-mentioned section intex SX and page index PX included in the above-mentioned address translation buffer 8
This is the t5 information used to search between the conversion information set in IJ, that is, the IJ search information.

It is also used as information specifying the location where necessary information is stored in the section intex SX and page index pxIIi, as well as in the section table ST and page table PT formed in the main memo IJ 10.

Section table 5T in the main memory IOK above
KFi, page table address PTA (1'TA, . . . corresponding to the start address of each page table PT)
, P'l'An) are stored sequentially. Section Intex SX at the above logical address LADR8K
U, pace address BASE of section table ST
It is composed of offset address information from ([J, start address of ttf sexy table ST) to an address trench in which a desired page table address is stored.

Each page table PTKq has a real page address RPA (几PA,...) corresponding to the start address of each page frame.
..., RPAn) are stored sequentially. Taking one page table PTi as an example, the page index PX in the logical address conversion function S is determined by the offset address information from the start address of the page table PTi to the address where the desired real page address is stored. configured.

The address conversion process for converting the logical address LADR8 into the physical address ADR8 using the cephsilon table ST and page table address in the main memory 10 will be explained first with reference to FIG. Logical address LA
As mentioned above, the section index SX included in DR8 is offset address information with respect to the pace address BASE, so the section index SX included in the base address BASE is
By adding the offset address indicated by the section index SX, the page table address, for example PTAi, indicated by the section index SX is obtained from the section table ST. Next, page index PX included in logical address LADR8 is set as offset address information for this page table address PTAi,
The real page address corresponding to the page index PX from the i-th page table PTi, for example, R
Obtain PAj. That is, the page table address PT
By adding the offset address indicated by the page index PXK to Ai, the real page address PAj indicated by this page index PX is obtained from the j page table PTi. By adding the offset oT included in the logical address LADR8 to the real page address RPAj obtained in this way, a physical address PADR8 corresponding to the logical address LADR8 is obtained. The physical address PADR8 thus converted is used as an address signal for accessing the ff hatching area of the jth page, frame, located in the real storage space.

The address conversion buffer 8 provided within the memory management unit 7 is a conversion table for directly searching the corresponding real page address RPA from the logical address LADR8.

As shown in FIG. 3, the address translation buffer 8 stores in advance a plurality of pairs of logical address sections and physical address sections. Internal correspondence information consisting of a sexy stamp index SX and a page index PX is stored in advance in each of the logical address parts as the searched information to be compared with the search information included in the logical address LADR8. On the other hand, each of the physical address sections is busy, and the real page address RPA, which has a one-to-IK correspondence with the sexy, index, x SX, and page index PX stored in the logical address section, which is paired with it, is Stored in advance. For example, in the physical address part that is paired with the logical address part that stores the sexy index 5Xn (SXm, 8Xi) and the page index PXn (PXm, PXi), i
), page index PXn (pxm, PXj
) and the real page address R corresponding to i to IK.
PAn(RPAm, RPAi) is stored. In this way, the address translation buffer 8 contains the logical address LA.
Conversion information for determining a real page address from the index in DR8 is stored as an entry, and a conversion table is thereby configured. In this manner, the address translation buffer 8 is capable of holding a predetermined plurality of sets of translation information consisting of a logical address section and a physical address section in a rewritable format. That is, the address translation buffer 8 has a rewritable memory (holding means).

FIG. 5 shows a functional block diagram of the memory management unit 7. As shown in FIG. Memo 1) 7tj:
, the address translation buffer 8 and the control means CN, and the address translation buffer 8 includes a writable storage device capable of storing a plurality of sets of the above-mentioned logical address section and physical address section.

mυ control means CN Fis m ri 7)”Response L A
D RS , % row unit internal pressure Receives the base address from the base address register provided, data (page table address, real page address) LD and detection signal from the main memory 10 via the input/output control unit 6, and receives the above The section index SX, page index, box PX, and control signal C are output to the address conversion buffer 8.

Sector 1 index S in logical address LADR8
If the logical address information corresponding to the page index PX is stored in advance in the address translation buffer 8, the address translation buffer 8 converts the real page address RPA corresponding to this logical address information to the control means CN. Output to. The control means CN adds the offset OT included in the logical address LADR8 to this real page address RPA to form a physical address, and outputs this as P4DBS.

On the other hand, if the logical address information compatible with the sexy index SX and page index PX in the logical address LADR8 is not stored in the address conversion buffer 8 in advance, the control means CN It is recognized by the detection signal that the logical address information does not exist, and the main memory 10 is
The address signal for accessing the section table ST within is determined, and the instruction signal φ is asserted. An address signal for accessing this section table ST is supplied as PADR8 to the main memory 10 via the address bus AB. main memory 10
The page table address read from the cefushirane table ST in the main memory 10 is added to the page index PX in the control means CN to form an address signal for accessing the page table PT in the main memory 10. The address signal for accessing this page table PT=i is sent to the address bus A as PADR8.
It is supplied to the main memory 10 via B. The real page address read from the page table PT in the main memory 10 is added to the offset OT in the logical address LADR8 in the control means 10 to form a physical address for accessing the main memory 10, It is output as PADR8. In this embodiment, the instruction signal φ is negated at the timing of accessing the page table PT in the main memory 10, although this is not particularly limited. Furthermore, the base address BASE in this embodiment can be changed arbitrarily by setting a desired value in the base address register in the execution unit 5, and thereby the address in the main memory 10 of the section table can also be changed freely. Can be changed.

FIG. 1 shows the operation flow of the memory management unit 7. As shown in FIG. Also, Fig. 6 (5) to (C) K F1
! , a waveform diagram of the data bus DB, address bus AB, and signal lines conveying the instruction signal φ is shown when the memory management unit 7 accesses the section table 8T and page table PT in the main memory 10.

Next, the operation of the memory management unit will be described using FIGS. 3 to 6.

a memory management unit comprising the address translation buffer 8;
To the door, from instruction 7 etch unit 2 to logical address LA
When DR8 is supplied, all entries are searched associatively by referring to the logical address section in the address translation buffer 8 using the sexy index SX and page index PX contained therein as search information (see Fig. 1). step S1). As a result, if there is searched information that matches the searched information (YES), the real page address R, PAK, and logical address LAD that are paired with this searched information are
Offset 0Tt included in R8 - additional step S
2) The resulting physical address PADR8 is output to the address bus AB.

On the other hand, if the entry corresponding to the search information of the input logical address LADR8 does not exist in the address translation buffer 8 (No), the memory management unit 7 first performs the following steps.
The sexy index SX contained in the logical address Kt is added to the base address BA8EK as offset address information for the base address BA8E (
Step 83). With the address signal obtained from K, the main memory 10 is accessed and the instruction signal φ is asserted (low level) (step s4.
s5). By accessing the main memory 10, the page table address corresponding to the sexy index SXK, for example, P
TAi is read onto the data bus DB and deposited into the memory management unit y door. Next, the page table address P'l''AiK is added to this page table address PTAi using the page index PX included in the logical address LADR8 as offset address information (step s6).The address signal obtained thereby is added to the address bus. AB is output, and the main memory 10 is accessed (step 57) 9 With this access, the real page address corresponding to the page index PX, for example RPAj, is read out from the page table PTi to the data bus DB, and the memory management unit 7. When the memory management unit 7Vi takes in the real page address RPAJ in this way, it uses the section intex SX and page index PX included in the logical address LADR8 at this time and the corresponding real page address RPAJ. New conversion information is formed and this conversion information is stored in the address conversion buffer 8 as a desired address conversion entry (step S8).Then, the instruction signal φ is negated (step 89), and the captured real page address RPAJK is , the offset OTi in the logical address LADR8 is added (step S2), so that the physical address An instruction signal φ is output to externally instruct the state, that is, the access timing of the main memory 10. This instruction signal φ is supplied to a bonding pad BPK provided on the chip of the data processor 1. Pad BP is coupled to an external terminal (bin) provided on the package of data processor 1 .

Therefore, the instruction signal φ generated in the memory management unit 1'7 is outputted to the outside of the data processor 1 via the bonding pad BP and the external terminal as described above. For example, the memory management unit 7 is the main memory 1
Section table 8T and page table PT in 0
The instruction signal φ is asserted (low level) at a predetermined timing for accessing the page table PT, and the instruction signal φ is negated at the timing when a predetermined real page address RPA is taken into the address translation buffer 8 from the page table PT.

Although not particularly limited, according to this embodiment, the instruction signal φ is supplied to the emitter 20.

This emulator 20 includes, but is not particularly limited to, an emulator control section, a breakpoint control section, a trace memory section, a substitute memory section, and a master processor that controls the entire system, as shown in FIG. It is equipped with 1-in-1 processing functions, real-time tracing functions, break functions, memory substitution functions, and other debugging functions. Except for the master processor, each of the units constituting the emulator 20 is not particularly controlled, but is composed of a plurality of semiconductor integrated circuit devices. Therefore, this emitter 20, for example,
Constructed on a printed circuit board.

The emulator 20 stores the state of the user system in the trace memory 21 while the user is developing and emulating the next system.

That is, the user system sends the instruction signal φ and other various control signals to the data bus D for the address and data generated in each bus cycle.
A first trace memo IJ 21 receives these via the address bus AB and the like and is included in the trace memory section 21.
Store in A in chronological order.

Furthermore, during the period when the instruction signal φ is asserted,
Second trace memory 2 included in trace memory section 21
The information on the address bus AB and data bus DB is also taken into 1B in chronological order.

Therefore, when new conversion information is set in the address conversion buffer 8, as shown in FIGS. 6(5) to 6(q), the sector index SX included in the logical address LADR8 is Section tape S as offset address information for address BABE
Address bus A is used to obtain the page table address PTA corresponding to the section intex SX from T.
The address signal (BASE+SX) output to B and the page table address PTAC/i'TA output from the second table ST to the data bus DB.
1) and then its page table address PTA
The page index P included in the logical address for
An address signal (PTAi + PX) is output to the address bus AB in order to obtain the real page address RPA corresponding to the core page index PX from a predetermined page table PT by adding offset address information to - The real page addresses R and PA (RPAj) output from the table PT to the data bus DB are stored in the second trace memory IJ 21 B in chronological order.

In this way, the information taken into the second trace memory IJ 21 B during the period in which the instruction signal φ is asserted is information including at least the conversion information set in the address conversion buffer 8.

That is, while the system developed by the user is being emulated, all information corresponding to newly set conversion information is stored in the 1-address conversion buffer 8 in the wc2 trace memory 21BK. In other words, the physical address P from ADR8 where emulation is being performed
When an address translation buffer is used to form the ADR 8, all information corresponding to the translation information including the logical address part and physical address part used in the address translation is stored in a second trace memory provided outside the data processor 1. It can be stored in 21B.

The emulator 20 or a console (not shown) includes an address inverse translation table 22 for inversely translating the physical address PADR8Q into the logical address LADR8.

Although not particularly limited, in this embodiment, the address inverse translation table 22 is provided in the emulator 20, as shown in FIG.

The reverse conversion information constituting this address reverse conversion table 22 is formed by the data stored in the second trace memo IJ21B. The operation for forming this inverse conversion information is not particularly limited, but is performed at the time of break after the emulation operation is completed.

The process for forming the inverse translation information constituting the address inverse translation table 22 is not particularly limited, but corresponds to almost the reverse process of the address translation process shown in FIG. That is, the real page address RPA taken into the first and second trace memories 21B during the period in which the instruction signal φ is asserted seven times is taken as the real page address of the test plan information, and the address used to obtain this real page address PA is signal and page table address PTA (data bus D before the real page address RPA is output to data bus DB).
The page index PX is obtained based on the offset amount (difference between the address signal and PTA) with respect to the data output to B), and this page table address PTA is
Ninthly, the address bus AB is obtained from the main memory 10.
The sexy index SX is obtained based on the offset amount (difference between the address signal and BASE) between the address signal supplied to the base address register and the pace address BASE set in the base address register.

The sexy index 8X and page index PX obtained through such processing are information (logical address information) that forms a pair with the real page address (physical address part) as the searched information. By performing such processing every time the instruction signal φ is asserted, a plurality of pieces of searched information set in the address translation buffer 8 can be obtained during the period in which emulation is being performed.

Address inverse translation table 22 formed by pressing in this way
converts the physical address PADR8 stored chronologically in the first trace memory 21A to the logical address LAD.
Used to convert to R8.

In the address inverse translation table, real page addresses RPArl to RPAi+1, which are searched information, and
The correspondence relationship with the physical address PADR8 to be converted that is read from the first trace memory 21A is not particularly limited, but if the size of the page frame (the size of the storage space that one page has) is fixed. , the physical address PADR8 to be converted within the above fixed page size starting from the real page address RPA.
This can be determined by whether or not it is condensed.

That is, physical address PADR8t logical address LADR
When searching the address inverse conversion table for the inverse conversion information necessary for converting physical address PA
Inverse conversion information can be searched depending on whether DR8 is included. For example, as shown in FIG. 7, the physical address PADR8 is the real page address RPA! stored in the address reverse translation table! 1 and the page size fixed to this real page address RPAn (2)
A comparison is made to determine whether the page address is within the range between the page address obtained by adding . If it is not within this range, then it is determined whether it is between the real page address RPAm and R,PAm+2. In this way, it is determined from time to time, for example, the physical address P
ADR8 uses real page address RPAi and address RP
A i+2, in the address inverse translation table, the sexy index sxi and page index PXi corresponding to the actual address RPAi are changed to the sexy index sxi and page index PXi of the logical address LADFL8. It is considered an index. Then, the difference between the physical address P A D B, S and the above-mentioned real page address RPA i is taken as the offset of the logical address LAPR8.

As understood from the detailed explanation above, in the address inverse translation table, the physical address PAD to be translated is
When the reverse conversion information corresponding to R8 is retrieved, the offset amount between the real page address RPA included in the retrieved reverse conversion information and the physical address PADR8 to be converted is set as the offset OT of the logical address LADR8,
Furthermore, the sexy index SX and page index PX included in the inverse conversion information can convert the logical address PADR8 to the logical address conversion mechanism S. The physical address PADR8 stored in the first trace memo 1721A as described above
are sequentially converted into logical addresses. The converted logical address LADR 8 is displayed in chronological order along with other trace information on a console 9 (not shown), and is used for depacking the software of the system developed by the user.

According to the above embodiment, the following effects can be obtained.

(1) When accessing the main memory 10 and setting translation information in the address translation buffer 8, the memory management unit 7 asserts an instruction signal φ for instructing the access timing to the outside.

An external circuit such as the emitter 20 that receives this instruction signal φ sequentially stores information included in all the conversion information set in the address conversion buffer 78, and stores (2) From the above operation and effect, the address inverse conversion table 22 , the physical address PADR8 output by the data processor l can be later converted externally into the logical address LADR8.

(3) From the above effect (2), it is possible to indirectly obtain the logical address translation mechanism S required for software debugging externally in a data processor l having a built-in address translation mechanism. L
A special method that does not require a data processor dedicated to evaluation that outputs ADR8, and controls the operation of such a data processor dedicated to evaluation in parallel with a data processor that outputs physical address PADR8 for proxy control. Since no emulator is required, software debugging of a system including the data processor 1 incorporating such an address translation mechanism can be easily performed with an extremely simple configuration.

(4) A data processorless inverse translation table 22 incorporating an address translation mechanism can be formed.

The configuration for achieving the above is obtained by the output function of the instruction signal φ. As a result, the logical address LAN)l'tS
A special evaluation data glossary that also outputs
Its configuration is simpler than that of K, and the only difference from the data processor as an actual chip is the function of outputting the instruction signal φ to the outside, so it is possible to implement the data processor chip by simply changing the package. Can be used commonly for chips and evaluation chips.

(5) The data processor 1 only needs to be provided with an external terminal for outputting the instruction signal φ, without providing a plurality of external terminals for outputting logical address signals in addition to physical address signals. Therefore, it is possible to prevent the data processor 1 from becoming expensive.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, although the logical address space in the above embodiment is composed of sections and seven frames, the present invention is not limited thereto, and the logical address space may be composed of pages or even segments. therefore,
The configuration of logical addresses and further the table configuration of the address translation buffer can be changed as appropriate according to the concept of logical address space.

Further, in the above embodiment, the instruction signal φ is directly supplied to the outside from the memory management unit via the external terminal provided in the data processor 1, but the instruction signal φ is directly supplied to the outside via the external terminal provided in the data processor 1. The signal may be applied to the outside via an external terminal. ,Also,
In the above embodiment, the data processor l was described as a processor that replaces the target processor during emulation execution, but this data processor can be used not only for emulation, but also for systems developed by users. Available. in this case,
When the instruction signal φ is not required for system operation, the bonding pad BP (electrode) for the instruction signal φ provided on the chip of the data processor 1 is used to transmit the instruction signal φ to the outside. It does not need to be connected to an external terminal. Depending on the situation, it is possible to use a package that does not have an external terminal for outputting the signal φ to the outside.

Furthermore, in the above description, the instruction signal φ continues to be asserted while the memory management unit 7 accesses the main memory IO in order to store conversion information, but this is not limited to this. For example, the instruction signal φ may be asserted only when the memory 10 is accessed.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to software debugging in a data processor with a built-in address translation mechanism, which is the field of application that formed the background of the invention. The present invention is not limited and can be widely applied to data processing devices incorporating various information conversion mechanisms.

The present invention is applicable to a device equipped with a conversion table that rewritably retains at least conversion information given from the outside, and has a built-in information conversion means for converting internal information into external information by referring to this conversion table. can do.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when accessing the external memory (7) and setting conversion information in the conversion table, an instruction signal for instructing the access timing to the outside can be output.

Based on this instruction signal, information including the conversion information set in the conversion table is stored externally, and based on the stored information, the converted information supplied externally from the information conversion means is reversely converted into internal information. It becomes possible to create a table externally. As a result, internal information can be easily obtained by inversely converting it externally based on the trace results of the converted information that is provided externally, without directly providing the internal information before conversion by the information converting means to the outside. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing system including a data processor which is an embodiment of a data processing device according to the present invention, and FIG. 2 shows a logical address converted to a physical address by an address conversion mechanism built in the data processor. 3 is a diagram showing a schematic structure of conversion information set in an address translation buffer included in the address translation mechanism. FIG. 1 is an operation flow diagram of the address management unit. Figure 5 is a block diagram of the address management unit, Figure 6 is a waveform diagram when the address management unit accesses the main memory, and Figure 7 is a diagram showing the process of inverse translation using the address inversion table. It is. φ Fig. O Fig. S × X T

Claims (1)

[Claims] 1. A data processing device to be coupled to a storage device via an address bus and a data bus, the data processing device comprising: means for forming a first address signal; and writable information. a second address signal to be supplied from the first address signal to the address bus by using the address conversion information held in the information holding means;
The address conversion means includes an address conversion means for forming an address signal and a bonding electrode, and the address conversion means converts at least part of the address conversion information held in the storage means to the information storage means. and means coupled to the bonding electrode for supplying an instruction signal to the bonding electrode in response to access by the writing means to the storage means. 2. a first storage means; a means for forming a logical address signal; an address conversion means for converting the logical address signal into a physical address signal; a data processing device comprising: means for storing the converted data in the address translation means as at least part of conversion information for address translation; and means for forming an instruction signal representing the access timing; a second storage means coupled to the second storage means for capturing data supplied to the data processing device from the first storage means in response to the instruction signal.