JPH02118474A - Testing device for propagation delay time - Google Patents

Abstract

PURPOSE:To obtain data in a short time and at the time of a normal/defective test by storing respective memories with respective decision results of outputs of a body to be measured under various test conditions which differ in decision timing, and reading them out and making a normal/defective decision. CONSTITUTION:Various test inputs are supplied from a test unit to the body DUT to be measured and its outputs are supplied to comparators DC in parallel to decide whether or not the outputs are normal at different timing. The decision results are written in the memories CM which are provided separately. The contents of the memories CM are checked to know whether the tested body is normal or not and the maximum delay when the tested body is abnormal. The results of the memories CM are read every time a test is conducted and results of respective tests which are conducted under various conditions are stored; and the test results under the respective conditions can be read out at a time and decided after a series of the tests.

Description

[Detailed Description of the Invention] [111 points of the invention] Regarding a testing device for a fixed object such as a semiconductor device (delay time), it is possible to acquire data in a short period of time, and it can be used even during a good/bad test. The purpose is to provide a test device that can acquire data and also detect the pass/fail judgment when ensuring that there are no intermittent changes in the output signal. a test unit 71- which supplies the output of the object to be measured, a plurality of :I comparators which are supplied with the output of the object to be measured in parallel and which judge the quality of the output at different timings, and a memory into which the judgment results of each comparator are stored. +i'! to prepare for +i'!

(Industry. Second Field of Application) The present invention relates to an apparatus for testing U and N of a test object such as a semiconductor device (5 delay times).

Semiconductor devices in recent years have become increasingly large-capacity and ultra-high-speed, and it has become increasingly time-consuming to acquire data for evaluating their performance. The present invention particularly provides data acquisition for evaluating semiconductor devices in GO/No''GO test conditions (
The present invention relates to a test device that is capable of making GO (good)/No Go (defective) judgments under one test condition.

[Conventional technology]

In semiconductor devices, pass/fail is determined by passing a series of test patterns under one test condition, and the test is repeated under different conditions to obtain the required data. For this reason, the test time is enormous.

Tests are also repeated to ensure that there are no intermittent changes in the output signal.

[Problems to be Solved by the Invention] Conventionally, testing was repeated to obtain test data on the object to be measured, resulting in a time-consuming evaluation process.

The present invention enables data acquisition in a short time, and G.

To provide a test device that is capable of acquiring data even during a (good)/No GO (bad) test, and can also be detected by GO/NOGo judgment even when ensuring that there is no intermittent change in an output signal. The purpose is to

[Means to solve the problem]

As shown in FIG. 1(a), the test device of the present invention has a
11 - Computer CPU, test unit TO which supplies test conditions to the δIII constant object (test head TH in this case), pattern generator PC, format controller FC, level generator Vl/VO , a digital comparator DC that judges the signal output from the object to be measured, and a memory CM that records the judgment result.
It has an output device OP that outputs measurement results, and an input device IP that can input a test program defining measurement conditions to a computer CPU.

Object to be measured D U'r' (Device
The relationship between the comparator DC and the memory CM is as shown in FIG. 1(b).
There are a plurality (N) of both C and CM. The output of the device under test DUT, for example a readout output in the case of a memory, is input in parallel to each comparator DC. The determination strobe signal S is supplied to each comparator DC, but it is delayed sequentially, so when viewed on the time axis, as shown in Figure 1 (C), it appears as if N strobes were input in one cycle. Become.

(Operation) In this device, the object to be measured OUT produces an output under one condition, and inputs the output to N comparators DC. The comparator determines the input when the strobe signal S is input. For example, assuming that the output of the DUT under test is OUTa in Figure 1 (C), a comparator (DC.) that operates at the timing of the strobe S1 has an input L level, and a strobe that is delayed by a time T. The comparator (DC) that operates at the timing of strobe S2 also has an L level input, but the input of the comparator (DC) that operates at the timing of strobe S3, which is further delayed by T2 time, has an input of I-level. Further, a comparator (r5c.) that operates at the timing of strobe S4 delayed by T3 time is also set to H level. If the expected values are all H like OUTe, the comparison results of comparators 1 and 2 will be bad (different from the expected values of 1 and 1), and the comparison results of comparators 3 and 4 will be good. . This defect 1 is written into the memory CM. Therefore, by reading each memory CM, you can find out whether it is good or bad, and if it is bad, the maximum delay.

When the test conditions are changed, the output OUTa of the device under test DUT changes (the H, I change point becomes slower or more advanced, the 0 part disappears, etc.), and the output of the comparator DC also changes.

This is also written to the memory CM, and by selling the memory three times, it is possible to know whether it is good or bad.

You can read out the memory CM every time you take an exam to see the results.
Alternatively, you can sequentially store the results of each test performed under various test conditions in the memo IJcM, read out the data stored in the memory CM after a series of tests are completed, and collect the test results under each test condition at once. It can also be taken out and judged.

In this way, in the present invention, each judgment result of the output of the measured object under various test conditions with different judgment timings is written in each memory, and the data stored in these memories is read out and judged as pass/fail. Tests under test conditions can also be conducted quickly.

For example, in the conventional Bandai, the judgments from 31 to S4 in Fig. 1(C) are made by making D[JT output four times and
+SM+ . . . is determined each time, but according to the present invention, this can be done only once. The advantages of the present invention become even more effective when a large number of such tests are performed.

〔Example〕

An example is shown in FIG. In 2\, the judgment circuit J includes the digital comparator DC and the conveyor memory CM.

The determination strobe signal S is directly input to the first determination circuit 1, but is sequentially input to the other determination circuits via the range (delay) circuit R.

The output 0UTa of the DUT under test is a signal that rises from L to H or falls from H to L as shown by the solid line, but the comparator CO? 'IP is set, and if the dark value is higher than the dark value, the H output is set, and if the dark value is lower than the L output, etc. This dark value is H for judgment circuits 1 to N.

The output differentiated into L (also assumed to be 0UTa) is input.

The output 0UTa of comparator COMP is determined by each judgment circuit 1~
The length of the signal line 2 input to N is not large enough for each determination circuit, and considering the 115th generation, the output 0UTa is not input to each determination circuit at the same time, and the input timings are staggered. The range circuit R also compensates for this delay. Immediately the first
Assuming that the delay T I + T 2 +... in Figure (C) is equal to ``ζ'' and is T, each range circuit R only needs to have a delay T, but in addition to this, the signal between each judgment circuit・With the propagation delay of the line P (also taken as ΔT), “f−tΔ
'(') This is shown in FIG. 3(C).

To explain the operation, the output signal OU of the DUT under test
Ta is input to the comparator COMP, and when it is determined to be H level, it is turned on at the time when the 11th level is determined.
A rectangular wave (0 (JTa)) is output as ゛ζ and inputted to each judgment circuit 1-N.The judgment strobe signal S is given the delay and inputted to the °C evaluation circuit, and as a result (,) As shown in FIG. 3 (1)), the delay of the determination circuit 1 is corrected, and the output 0UTa is at the time point L2, the determination circuit 2 is at the time point L2, and the determination circuit N is at the 111I point. 4
Then, H/L judgment will be made. In this example, the judgment circuit 4
Judgment until the end of the judgment circuit 5 and beyond is l (judgment).Depending on the test conditions, the output OUT
a is delayed by II) τ -COUT b. In this case, the II/L determination result also changes. These determination results are written to the memory CM if they are determined to be defective.

If the time difference between each judgment timing LI+L 2+... is made small, the H/L of the output OU 'I' a
will be examined in detail. i.e. t) The time difference defines the resolution, and if the time difference is small, the resolution is high. However, the number of determination circuits increases.

After completing the test pattern 91 (experiment), the memory CM is read out one by one using the memory bronch select signal CMLIS as an address, and the successive output CMI?13 (C
Judging the quality of the DUT under test using
(11! Extract the worst value of delay time, etc.

The memory CM is set to 1 in advance by the CPU before the test.
(It is converted to 11. In this case, there is no need to store the '0' of the good judgment result (it has already been written). Also, if the judgment result is good, the memory is not updated. It is possible to detect the worst value of the delay time even for patterns of all degrees Celsius that can be generated by the pattern generator PC and for highly cell-dependent products such as memory devices.

As shown by the dotted line in FIG. 3(b), the output OLJ T may become ■1, then drop to L, and then change again to ■]. 1, 7 where the output signal changes intermittently like this
The present invention is also effective for sexual devices.

In this case, the determination result of the judgment circuit 1-N is ooo.

111001...etc. (usually 0001
11111...], it can be seen that this is an abnormal output.

The memory CM is I-sword × N pin-'tf + ¥ (l-to-1', that is, ■ address only, and the l address is N pieces of I-bit data star. Figure 2 assumes this), instead of M Words×N bits (M words or M addresses, each address having a capacity of 1 bit N(1/, I) may be used. An example of this case is shown in FIG.

The address signal ADD to the memory CM and the address signal to the DUT under test are made to match and are set in the test program. This allows the test results under each test condition to be stored in the memory C.
M's address 1, 2. ......to M) δ payment, DL
If the IT is a memory, the test results for each cell can be read out at once, and the worst value of the propagation delay time corresponding to the cell array can be quickly retrieved. FIG. 3('') shows the configuration of the memory CM in this case.

A specific example of the range circuit R is not shown in FIG. 5 (21). G11
G2. ... is a gate circuit that constitutes a delay element,
S.

S2+... is a switch for output output, S E
I- is a selection signal. If the selection signal SEL is used to take out the output from SI, a delay of only gate G1 will be added, and if the output is taken out from S2, G, , G
The delay of the sum of each delay of , is added. In this way, a desired delay can be added to the input S (strobe signal).

FIG. 5(b) does not show a specific example of the comparator COM 11 and the like that publishes the H/L output of the DUT to be measured. The comparator COMP is the H level reference value ■. Comparison to compare with H ÷! : i Cl and I, level J, (quasi value ■.

, and a comparator C2 that compares with . Gorera's output V
,, V2 is the output of the DUT is ■. , if it is 4 or more, V +
= V 2 = l'l, if below VOL, V, -Vz
= L, V between Voo and VOL + = L, V
,=11. This is used as comparison data REF by comparator C3.
You can tell whether it is good or bad by comparing it.

If it is defective, write 1 to memory CM. In this embodiment, the number of wires l shown in FIG. 2 is two. FIG. 6G shows the connection relationship of each element PG, TO, FC, . . . of the test equipment. The pattern generator PG outputs an eggplant pattern, and the format control FC outputs a DUT drive waveform. The level generator VIVO is a driver for the DUT and determines the level of the drive signal (or address signal in the case of a memory).

For example, if 'I'T' L, L is OV, H is 3V, IE
CL normalization is -1.8V, II is -0. 9 V, etc., and the driver νIVO creates this level.

When the DUT to be measured is a memory, there are various known testing methods. To explain some of them, SCA
There is a test called N, and the simple one is to set the memory '7 address to 0 to rl and perform WOO.

WO l, ... is the address O, ...
Writing O, l to lma00, ROI,...
is Woo, WIO as the above 0, 1 of address 0, . . .

--- ・--Wri O, R O O
, R 1 0, -----R r+
O, WOl, Wl l, -=-Wn I,R
Let O 1, R l 1,---Rnl. In the SCAN test called Strive, wo o, wt i
W2 0,...ROO, R11, R20,...
...WO l, Wl O, W2 1, ...
・Rot, RIO, R21, ...... In addition, in a method called ping pong, as shown in Figure 3, the memory is first cleared, and O, O (the first number of H is the row address, the next number is the address),
If S, read 0, IO) 0, then add l to OO again, read 0 of 0.2, write l to 0.0 again, 0.3
The process of reading 0 is repeated. The present invention can be applied to determining whether the output is good, bad, or delayed during a test.

This can be easily grasped, and in the case of logic, it is possible to obtain access data for each memory cell, or for logic, to obtain access data for each test pass in one pattern AsE experiment (GO/No GO).

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the configuration and operation of each part, and Fig. 4 is a block diagram of another embodiment of the invention. , FIG. 5 is an explanatory diagram of a specific example of each part, and FIG. 6 is a clear diagram of the connection state of each part in 11). In FIG. 1, S is a strobe signal for determination, and OUT. , I is the output of the object to be measured, and OUTe is its 1υ11, Y value. [Effects of the Invention] As described above, according to the present invention, it is possible to efficiently test the propagation delay time of the output of a device to be measured, which requires repeated testing many times and takes a long time. In addition, abnormal changes in output, etc. Applicant: Minoru Aoyagi, Patent Attorney, Fujitsu Limited (a) N No. 1 concavity (b) Figure 3, an explanatory diagram of the configuration and operation of each part Output

Claims (1)

[Claims] 1. A test unit (TU) that supplies various test inputs to a device under test (DUT), and an output of the device under test that is supplied in parallel and determines the quality of the output at different timings. multiple comparators (
What is claimed is: 1. A propagation delay time testing device comprising: a DC); and a memory (CM) into which the judgment results of each comparator (DC) are written.