JPH02114293A - Graphic display device - Google Patents

Abstract

PURPOSE:To eliminate a ROM to store a program, to save space, and to improve a maintenance facility by composing the title device so that the address space of a shared memory can be dynamically allocated to two types of space, namely, a reset vector area and an I/O area, by changing over a switch. CONSTITUTION:For a shared memory 1, its allocation can be dynamically changed to two types of space, namely, the reset vector area and the I/O area, according to the command of either a host processor HS or an internal processor 3. Further, under a reset state, the host processor HS allocates the shared memory 1 to the reset vector area and down-loads a work program there. After the reset state is released, the internal processor 3 transfers the work program down-loaded in the vector area to a local memory 5, allocates the shared memory 1 to the I/O area, and uses the area for transmitting a high-level command/data from the host processor HS. Thus, the ROM to store the program can be eliminated, the space can be saved, and the maintenance facility can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a graphic display device that is effective for use as a man-machine interface device for process control, and more specifically, relates to a graphic display device that is connected to a host processor via a system bus, The present invention relates to a graphic display device that displays graphics according to commands from a host processor.

<Prior art> Graphic display devices used as man-machine interface devices for process control are
Display means are required to display various types of information for managing and controlling the entire plant effectively and at high speed.

Conventionally, this type of graphic display device has an internal structure that includes a processing device such as a microprocessor and a ROM that stores operating programs executed by the microprocessor.
It is configured to display graphics on a display means such as a CRT by interpreting and executing the data.

Here, the operating program executed by the microprocessor is
Increases in proportion to the processing capacity inside the device, usually from several KB to
Approximately several KB/O0KB are required.

<Problems to be Solved by the Invention> However, in a conventional device configured to have a ROM inside the device and store a microprocessor operating program therein, if a bug exists in the program stored in the ROM, , it is necessary to replace the internally installed ROM, circumvent bugs by programming from the host processor, and completely change the operation/O-gram including downloading a modification program from the host processor, making it difficult to maintain. There was a problem.

The present invention has been made in view of these problems, and its purpose is to omit the ROM that stores the operation (main body) program executed by the microprocessor inside the device, thereby saving space and maintenance. The objective is to realize a graphic display device with improved performance.

<Means for Solving the Problems> In FIG. 1, which is a block diagram showing the basic configuration of the present invention, H3 is a host processor, and GD is connected to the host processor H3 via a system bus BS. A graphic display device having a processor 3 therein is the object of the present invention.

In this graphic display device, 1 is a shared memory with the host processor, one connected to the system bus BS and the other connected to the internal bus, and the address space seen from the internal processor 3 is allocated to two types of spaces. It is configured so that it can be done. 2 is host processor 1
4 is an area selector for switching the allocation of two types of spaces in the shared memory 1 according to instructions from the host processor 1 and the internal processor 3; This is local memory connected to the internal bus.

Function> Shared memory 1 can be dynamically allocated to two types of space, the reset vector area and the I/O area, according to commands from the host gross system or internal processor. The processor allocates shared memory to the reset vector area, downloads the operating program there, and after the reset is released,
The internal processor transfers the operations/O-grams downloaded into the vector area to local memory, and also allocates shared memory 1 to the I/O area, which is used for communicating high-level commands/data from the host processor.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. The graphic display device GD is coupled via a shared memory 1 to a system bus BS to which a host processor H3 is connected. In addition to the shared memory 1, internal processor 3, and local memory 5, a drawing controller 6, a frame buffer 7 connected via the drawing controller 6, a color lookup table 8, and the like are connected to the internal bus. 9 is a CRT as a display means.

The shared memory 1 is configured such that its address space can be dynamically allocated to two types of spaces, a reset vector area and an I/O area, by switching a switch SW. That is, the switch SW is driven to either position a or b by the output of the area selection means 4, and selects either the address decoded by the address decoding means 41 that specifies the reset vector area from the internal processor 3, or the I/O area. The designated address is given to the shared memory 1 via the switch SW, and the address space is dynamically allocated to either the reset vector area or the I/O area.

With this configuration, the host processor H
As shown in Figure 3, the address space of the memory as seen from the side of the graphic display device from 3 is 2. As shown in Figure 3, the shared memory is located at a fixed address, and the address space of the memory as seen from the internal processor 3 of the graphic display device. is the switch SW by the area selection means 4.
When is placed in position a, the shared memory is allocated to the reset vector area ($0~) as shown in Figure 4(a), and when switch SW is placed in position b, ( As shown in b), it is allocated to the ■/d area.

Here, the local memory is also allocated to include the reset vector area, but when the switch SW is placed in position a, the overlapping portion is masked.

The operation of the apparatus configured in this way will be explained next.

FIG. 5 is a flowchart showing an example of operations performed by the host processor H3 and the internal processor 3.

First, the host processor H3 sends a command to the external reset means 2 to reset the internal processor 3 in the graphic display device GD. At the same time, a command is sent to the area selection means 4, the switch SW is placed in position a, and the shared memory 1 is mapped to the reset vector area (step 1).

Next, the host processor H3 downloads the program main body download program to the shared memory 1 (step 2).

Next, the host processor sends a command to the external reset means 2 to reset and start the internal processor 3 (step 3), whereby the program downloaded to the shared memory 1 is activated and starts running.

Subsequently, the internal processor 3 uses this program to copy the program itself into the local memory 5, and
Next, jump to the copied program and run the program for downloading the program itself (
Step 4).

In accordance with the program for downloading the main program, the internal processor 3 first sends a command to the area selection means 4 and places the switch SW in position b.
Remap shared memory 1 to the I/O area and use this memory area as a buffer to transfer local memory 5.
The main body of the program is downloaded from the host processor FTS (step 5).

At this time, the host processor H3 uses the shared memory 1 to download the program main body to the local memory 5 in cooperation with the program downloaded in step 5.

Subsequently, the internal processor 3 starts operating as a graphic display device according to the program downloaded to the local memory 5 (step 6).

The start of this operation may be performed by jumping from the program downloaded in step 5, but is usually performed by a reset signal from the external reset means 2 in response to an instruction from the host processor H3, which also serves as hardware initialization.

In subsequent operations, the internal processor 3 stores the shared memory 1 in response to high-level commands/commands from the host processor H3.
It is used for exchanging data, and takes over some of the operations of the host processor HS using a high-level command interface for graphics (for example, CGI).

In the above embodiment, the shared memory 1 is configured such that one side is connected to the system bus BS and the DAI Ref 1~. If you configure it so that it can be written to, there is no need to connect it directly to the system bus.

<Effects of the Invention> As explained in detail above, according to the present invention, the R
The OM can be omitted from the graphic display gray device, which saves space and eliminates the need to replace the ROM, improving maintainability.

Furthermore, even if the operation (main body) program has a large capacity, it is possible to boot up the system by providing enough capacity in the shared memory to download the minimum boot program.

In addition, since the operating program is executed after being transferred to local memory where access speed is faster, the speed is reduced due to bus access collision compared to storing the operating program in shared memory and executing the operating program. can be avoided and performance can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic configuration of the present invention, Figure 2 is a block diagram showing the basic configuration of the present invention.
3 is a conceptual diagram showing a memory address space as seen from the host processor to the graphic display device side. FIG. 4 is a conceptual diagram showing the memory address space as seen from the internal processor of the graphic display device. FIG. 5 is a conceptual diagram showing the address space of the memory, and FIG. 5 is a flowchart showing an example of its operation. H3...Host processor, BS...System bus GD...Graphic display gray device 1...Shared memory, 2...External reset means, 3...Internal processor, 4...Area selection means , 5...Local memory, Fig. 2, f, Fig. (α) Mo loss

Claims (1)

[Scope of Claims] A graphic display device having an internal processor that receives drawing commands/data sent from a host processor and displays graphics on a display means, wherein the address when viewed from the internal processor is a reset vector area. a shared memory with the host processor configured to be able to dynamically change the allocation to two types of spaces: and an I/O area; and an external reset means for resetting/releasing the device according to instructions from the host processor. , an area selector for switching allocation of two types of spaces in the shared memory according to instructions from a host processor and an internal processor, and a local memory connected to the internal processor and the shared memory via an internal bus, The host processor allocates the shared memory to the reset vector area and downloads the operating program therein in the reset state by the external reset means, and the internal processor downloads the operating program to the vector area of the shared memory after the reset is released by the external reset means. What is claimed is: 1. A graphic display device characterized in that a shared memory is allocated to an I/O area and used for transmitting high-level commands/data from a host processor.