JPH0210915A - Polarity unification circuit for pulse signal - Google Patents

Abstract

PURPOSE:To attain ease of circuit integration by measuring a pulse width of an input pulse signal and deciding its polarity so as to eliminate the need for any integration circuit and digitize the signal. CONSTITUTION:A pulse width measuring counter 1 is operated during L period of a positive pulse by utilizing the duty of an input synchronizing signal. A comparator circuit 2 outputs a pulse when the count is over the reference value. A misdecision prevention counter 3 outputs a pulse after counting the pulse for several number of times continuously. The pulse is given to a clock terminal C of an FF 5 and an output Q goes to an H level. Moreover, the output of the counter 3 resets a negative pulse decision counter 4 and its output goes to L. Thus, the FF 5 is active because its reset terminal R receives an L level and an exclusive OR circuit 9 outputs a negative pulse. When the input synchronizing signal is a negative pulse, no output of the counter 3 is generated and the FF 5 is reset by the output of the counter 4, then the circuit 9 outputs a negative pulse. Thus, an output synchronizing signal of a constant polarity is always obtained.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is applicable to horizontal synchronizing signals,
This is applied to devices that construct screens using pulsed signals with a constant frequency and different duty, such as vertical synchronization signals and composite synchronization signals, and outputs a signal with a constant polarity regardless of the input polarity of the pulsed signal. The present invention relates to a circuit for unifying the polarity of pulsed signals.

[Prior Art] FIG. 4 is a block diagram of a conventional polarity unification circuit for pulsed signals, in which (9) is an exclusive OR circuit, (12
) is an integrating circuit, and this integrating circuit (12) is a resistor (10)
and a capacitor (11) are configured to have an integral capacity suitable for the duty of the large-power pulse-like signal, and the polarity of the input pulse-like signal is determined, and the result is input to one side of the exclusive OR circuit (9) shown in L. By doing so, unification of polarity is achieved.

FIG. 2 explains the function of the exclusive OR circuit (9). It is a truth table showing the relationship between the two inputs (8), (B) and the output (Y). ) and (R) are both low level (hereinafter referred to as L level) and high level (hereinafter referred to as H level), output (Y) is at L level, and inputs (A) and (B) Either one of H
When the level is high, the output (Y) also becomes high level.

Next, the operation of the above configuration will be explained.

Note that the case where the signal is a pulsed signal or a synchronous signal will be described here.

As shown in Fig. 5(a), when the input synchronization signal is a positive pulse that projects upward, the capacitor (11) is not sufficiently charged at point X after passing through the integrating circuit (12), so that exclusive Since the level does not rise to the threshold value (SH) of the OR circuit (9), the exclusive OR circuit (9) determines that the L level is input, and from the function shown in the truth table in Figure 2, the The output synchronization signal is shown in Figure 5 (C
), the input synchronization signal is output as is.

- On the other hand, as shown in Fig. 6(a), when the input synchronization signal is a downwardly protruding negative pulse, the capacitor (II)
Since it is sufficiently charged and the discharge time is short, it is determined that the H level has been input without falling below the threshold value (SH) of the exclusive OR circuit (9).

Therefore, the exclusive OR circuit (9) has the function shown in the truth table in FIG. 2, and its output synchronization signal is as shown in FIG.
), the polarity of the input synchronization signal is reversed and becomes a positive pulse.

As described above, regardless of the polarity of the input synchronization signal,
Determine its polarity and achieve unification of polarity.

[Problems to be Solved by the Invention] Since the conventional polarity unifying circuit for pulsed signals is configured as described above, an integrating circuit consisting of a capacitor and a resistor must be used for polarity determination. Therefore, when this polarity unified circuit is integrated into an IC, an external capacitor is required, which increases the number of terminals, and it is difficult to ensure accuracy.

This invention was made in order to solve the above-mentioned problems, and it is possible to eliminate the use of an integrating circuit and to convert the pulse-like signal into an integrated circuit (IC) by digitizing the signal. The purpose is to provide a polarity unified circuit.

[Means for Solving the Problems] A pulse signal polarity unification circuit according to the present invention utilizes the duty of an input pulse signal to measure its pulse width, and compares the measured output value with a reference value. The present invention is characterized in that it is configured to determine the polarity of an input pulse-like signal, and to unify the polarity based on the determination result.

[Operation] According to the present invention, the polarity of the input pulse-like signal is determined by measuring the pulse width of the input pulse-like signal and determining whether the output value thereof exceeds a reference value. Furthermore, based on the determination result, a pulsed signal with unified polarity is output.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a synchronization signal polarity unification circuit according to an embodiment of the present invention.
1) changes the pulse width of the synchronization signal to the first clock pulse (C
A pulse width measurement counter that measures using 1) for L, (2
) is a comparison circuit that compares the count value obtained by the pulse width measurement counter (1) with a reference value, (3) is a false judgment prevention counter, (4) is a judgment counter at the time of negative pulse, (5)
) is a flip-flop for holding the output of polarity determination, and (9) is an exclusive OR circuit for unifying polarity.

Next, the operation of the above configuration will be explained.

Utilizing the duty of the input synchronization signal, for example, in the case of a positive pulse, the pulse width measurement counter (1) operates during the L level period, and the comparison circuit (2) compares the output value of the pulse width measurement counter (1) with the output value of the pulse width measurement counter (1). Compare with the standard value,
When the output value exceeds the reference value, an l pulse is output.

Therefore, in order to prevent misjudgment due to the vertical synchronization period of the composite synchronization signal or noise, the output pulse from the comparator circuit (2) is input to the misjudgment prevention counter (3) and counted several times in succession, and then one pulse is counted. Output. This output pulse causes the clock terminal (C) of the flip-flop (5) to
is struck, and from the function shown in the truth table in Figure 3, the output (
Q) becomes H level. In addition, at this time, the output pulse of the false judgment prevention counter (3) is output from the negative pulse judgment counter (3).
4) is reset, and its output becomes L level. Therefore, an L level is applied to the reset terminal (R) of the flip-flop (5) connected thereto, and the flip-flop (5) becomes active.

As described above, when the output (Q) of the flip-flop (5) is at H level, the exclusive OR circuit (9) receives the input synchronizing signal as shown in the truth table of FIG. The polarity of is reversed and a negative pulse is output.

On the other hand, when the input synchronization signal is a negative pulse, the pulse width measurement counter (1) operates during the L level period, but the comparison in the comparison circuit (2) does not meet the reference value, so no output pulse is generated. Therefore, the output pulse of the erroneous determination prevention counter (3) is not generated either. At this time, the false judgment prevention counter (3) is reset by the second clock pulse ((:LK2), and the negative pulse judgment counter (4) is activated to generate an output pulse after counting several times. This pulse resets the flip-flop (5), and as is clear from the function shown in the truth table in Figure 3, the output (Q) becomes L level.Therefore, the exclusive OR circuit (9) According to the function shown in the truth table of Fig. 2, the input synchronizing signal is output with the same polarity, that is, a negative polarity pulse is output.

As described above, it is possible to obtain an output synchronization signal of constant polarity regardless of the polarity of the input synchronization signal.

In addition, when the second clock pulse (CLK2) is a composite synchronization signal, it has an interval that is greater than the width of the vertical synchronization period, and the reference value of the comparison circuit (2) is greater than or equal to the pulse width of the horizontal synchronization signal. In addition, the count value of the output pulse of the false judgment prevention counter (3) is adjusted according to the number of notch pulses in the vertical synchronization period when the composite synchronization signal is input, so that no output pulse is generated due to the pulses in this period. It is set.

In the above embodiments, the polarity may be determined using a counter or by calculation using a CPU.

In addition, in the above embodiment, the synchronization signal has been explained.
Any pulsed signal may be used as long as there is a difference in duty and the frequency is constant, and the same effect as in the above embodiment can be achieved.

[Effects of the Invention] As shown in H below, according to the present invention, by measuring the pulse width of the input pulse-like signal and determining its polarity, it is possible to eliminate the need for an integrating circuit. By digitizing signals, the entire circuit can be easily integrated into an IC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a circuit for unifying the polarity of pulsed signals according to an embodiment of the present invention, and FIG.
Figure 3 is a truth table showing the function of the R circuit, Figure 3 is a truth table showing the function of a flip-flop, Figure 4 is a configuration diagram of a conventional polarity unified circuit, and Figures 5 and 6 are conventional polarity unified circuits. FIG. 3 is a signal waveform diagram illustrating the operation of FIG. (1), (:l), (,1)...Counter, (2)-
...Comparison circuit. (5)...Flip-flop, (9)...Exclusive O
R circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 2nd port

Claims (1)

[Claims] (1) a pulse width measuring means for measuring the pulse width of the input pulse-like signal; a polarity determining means for comparing the output value of the pulse-width measuring means with a reference value to determine the polarity of the input pulse-like signal; A polarity unification circuit for pulsed signals, comprising a polarity unification means for unifying the polarity based on the determination result of the polarity determination means.