JPH0210714A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0210714A
JPH0210714A JP63159210A JP15921088A JPH0210714A JP H0210714 A JPH0210714 A JP H0210714A JP 63159210 A JP63159210 A JP 63159210A JP 15921088 A JP15921088 A JP 15921088A JP H0210714 A JPH0210714 A JP H0210714A
Authority
JP
Japan
Prior art keywords
package
chip
brazed
corners
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63159210A
Other languages
Japanese (ja)
Inventor
Katsuro Hiraiwa
克朗 平岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63159210A priority Critical patent/JPH0210714A/en
Publication of JPH0210714A publication Critical patent/JPH0210714A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PURPOSE:To scatter the thermal stress caused by the difference between thermal expansion coefficients, for preventing a semiconductor chip and package from cracking, by providing stepped parts through half-etching at the four corners of a semiconductor chip surface brazed to a package and not brazing the parts. CONSTITUTION:Stepped parts 4 are provided through half-etching at the four corners of a surface of a semiconductor chip 1 brazed to a package 3, but the stepped parts 4 are not brazed to the package 3. By doing this, the longest length of the brazed parts becomes shorter and the angles of sharp corners become smaller, as the stepped parts 4 made at the four corners of the chip 1 are not brazed to the package 3. Accordingly, the thermal stress produced by the difference between the thermal expansion coefficients of the chip 1 and the package 3 at the time of brazing can be reduced or scattered. This makes it possible to prevent the chip 1 and package 3 from cracking.

Description

【発明の詳細な説明】 〔概　要〕 半導体チップがセラミックパッケージにダイス付けされ
た半導体装置に関し、 チップとパッケージの熱膨張率の差によるチップクラン
クやパッケージクランクの発生を防止することを目的と
し、 半導体チップがセラミックパッケージに低融点ろう材で
ダイス付けされた半導体装置において、上記半導体チッ
プは、そのろう付けされる面の四隅にハーフエツチング
による段差が設けられ核部はろう付けされないように構
成する。[Detailed Description of the Invention] [Summary] The present invention aims to prevent the occurrence of chip crank and package crank due to the difference in thermal expansion coefficient between the chip and the package in a semiconductor device in which a semiconductor chip is diced into a ceramic package. In a semiconductor device in which a semiconductor chip is dice-bonded to a ceramic package using a low-melting brazing material, the semiconductor chip is configured such that steps are provided at the four corners of the surface to be brazed by half-etching so that the core portion is not brazed. .

（産業上の利用分野〕 本発明は、半導体チップがセラミックパッケージにダイ
ス付けされた半導体装置に関する。(Industrial Application Field) The present invention relates to a semiconductor device in which a semiconductor chip is dice-attached to a ceramic package.

近年、半導体装置の集積度が上がるにつれて半導体チッ
プが大型化している。このため、半導体チップをセラミ
ックパッケージにダイス付けした場合、該半導体チップ
とパッケージの熱膨張率の違いによる応力がチップ内部
やパッケージ内部に生じ、極端な場合にはチップやパッ
ケージにクランクが発生し、半導体装置の信頬性を悪化
させていた。このためクランクの防止手段が要望されて
いる。In recent years, as the degree of integration of semiconductor devices has increased, semiconductor chips have become larger. For this reason, when a semiconductor chip is diced into a ceramic package, stress is generated inside the chip and package due to the difference in thermal expansion coefficient between the semiconductor chip and the package, and in extreme cases, a crank may occur in the chip or package. This worsened the reliability of semiconductor devices. Therefore, there is a need for a means to prevent cranking.

〔従来の技術〕[Conventional technology]

従来の半導体装置は、第４図に示すように、直方体にグ
イシングされた半導体チップ（シリコン、ＧａＡｓ等）
１をＡｕＳｉ共晶２を用いてパッケージ（アルミナセラ
ミック）３に接着している。A conventional semiconductor device is a semiconductor chip (silicon, GaAs, etc.) shaped into a rectangular parallelepiped, as shown in FIG.
1 is bonded to a package (alumina ceramic) 3 using AuSi eutectic 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来の半導体装置では、ダイス付は時の約４２０℃
の温度から室温に冷却すると、半導体チップｌの熱膨張
率とパッケージ３の熱膨張率の違いから、−ａ的にチッ
プｌには圧縮応力が、パッケージ３には引張応力が作用
し、その応力は接着の長さが最も長いチップｌの四隅で
最大となるため、そこを起点としてチップクラックやパ
ッケージクランクが発生するという問題があった。In the above conventional semiconductor device, the temperature with the die is approximately 420°C.
When it is cooled from the temperature of Since the bonding length is the longest at the four corners of the chip l, there is a problem in that chip cracks and package cranks occur starting from these corners.

本発明はチップとパッケージの熱膨張率の差によるチッ
プクランクやパッケージクランクの発生を防止した半導
体装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which chip cranks and package cranks are prevented from occurring due to the difference in coefficient of thermal expansion between the chip and the package.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明の半導体装置では、
半導体チップ１がセラミックパッケージ３に低融点ろう
材２でダイス付けされた半導体装置において、上記半導
体チップｌは、そのろう付けされる面の四隅にハーフエ
ツチングによる段差４が設けられ核部はろう付けされな
いように構成された半導体装置である。In order to achieve the above object, the semiconductor device of the present invention includes:
In a semiconductor device in which a semiconductor chip 1 is dice-bonded to a ceramic package 3 using a low melting point brazing material 2, the semiconductor chip 1 has steps 4 formed by half etching at the four corners of the surface to be brazed, and the core portion is brazed. This is a semiconductor device configured so that the

（作　用〕 チップ１の四隅にハーフエツチングによる段差４を設け
たことにより、ろう材２でパッケージ３にダイス付けし
たとき段差部４はろう付けされないため、チップの四隅
に作用する熱応力は低減分散され、チップクラックやパ
ッケージクランクの゛発生は防止される。(Function) By providing the steps 4 by half-etching at the four corners of the chip 1, when the package 3 is diced with the brazing material 2, the steps 4 are not brazed, so the thermal stress acting on the four corners of the chip is reduced. This prevents chip cracks and package cranks from occurring.

〔実施例〕〔Example〕

第１図は本発明の実施例を示す図であり、（ａ）は断面
図（ｂ）はａ図のＢ部拡大図である。FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) is a cross-sectional view and (b) is an enlarged view of part B in FIG.

本実施例は同図に示すように、シリコン又はＧａＡｓ等
の直方体の半導体チップ１がＡｕＳｉ共晶（又はＰｂ５
ｎ又はＡｕ５ｎ）　　２でセラミックパッケージ３にろ
う付けされていることは第４図で説明した従来例と同様
であり、本実施例の要点は半導体チップ１のパッケージ
３にろう付けされる方の面の四隅にハーフエツチングに
より段差部４を設けたもので、該段差部はパッケージに
ろう付けされないようになっている。なお段差部４の境
目は直線でなく第２図（ａ）（ｂ）の如く曲線であって
も良い。In this embodiment, as shown in the figure, a rectangular parallelepiped semiconductor chip 1 made of silicon or GaAs, etc. is made of AuSi eutectic (or Pb5
It is the same as the conventional example explained in FIG. Steps 4 are provided at the four corners of the package by half-etching, and the steps are not brazed to the package. Note that the boundary between the step portions 4 may not be a straight line but may be a curved line as shown in FIGS. 2(a) and 2(b).

またこの段差部は第３図に示すように、ダイシング前の
ウェハー５にハーフエツチングにより四角形又は円形等
の窪み６を形成しておき、その後各チップにダイシング
したとき、その四隅に窪み６の１／４が残り段差部がで
きるようにして形成することができる。Furthermore, as shown in FIG. 3, this stepped portion is formed by forming a rectangular or circular depression 6 in the wafer 5 before dicing by half etching, and then when each chip is diced, one of the depressions 6 is formed in the four corners of the wafer 5. /4 can be formed so that a stepped portion is formed.

以上の本実施例によれば半導体チップ１の四隅に形成し
た段差部４がパフケージ３にろう付けされないため、ろ
う付けの最長の長さが従来に比して短か（なり、またシ
ャープコーナーの角度がゆるくなるため、半導体チップ
ｌとパッケージ３との熱膨張率の差によりろう付は時に
生じた熱応力を減少及び分散させることができる。この
ためチップクラック及びパッケージクランクの発生は防
止される。According to this embodiment, the step portions 4 formed at the four corners of the semiconductor chip 1 are not brazed to the puff cage 3, so the longest length of the brazing is shorter than the conventional one (or the sharp corners are shortened). Due to the gentler angle, the brazing can reduce and disperse the thermal stress that sometimes occurs due to the difference in thermal expansion coefficient between the semiconductor chip l and the package 3. Therefore, the occurrence of chip cracks and package cranks is prevented. .

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明によれば、半導体チップの四
隅に設けた段差により、パッケージとの熱膨張率の差に
より作用する熱応力を分散することができ、チップクラ
ックやパッケージクラックを起こしにくい信頼性の高い
半導体装置を提供することが可能となる。As explained above, according to the present invention, the steps provided at the four corners of the semiconductor chip can disperse thermal stress caused by the difference in thermal expansion coefficient with the package, making it difficult to cause chip cracks or package cracks. It becomes possible to provide a highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示す図、 第２図は本発明の実施例の段差部の他の例を示す図、 第３図は本発明の実施例の半導体チップの形成方法を示
す図、 第４図は従来の半導体装置を示す図である。 図において、 ｌ・・・半導体チップ、　　２・・・ＡｕＳｉ共晶、３
・・・パッケージ、　　　４・・・段差部、を示す。FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing another example of the stepped portion in the embodiment of the present invention. FIG. 3 is a diagram showing a method for forming a semiconductor chip in the embodiment of the present invention. FIG. 4 is a diagram showing a conventional semiconductor device. In the figure, l... semiconductor chip, 2... AuSi eutectic, 3
. . . package, 4 . . . step portion.

Claims (1)

【特許請求の範囲】 １、半導体チップ（１）がセラミックパッケージ（３）
に低融点ろう材（２）でダイス付けされた半導体装置に
おいて、 上記半導体チップ（１）は、そのろう付けされる面の四
隅にハーフエッチングによる段差（４）が設けられ該部
はろう付けされないことを特徴とする半導体装置。[Claims] 1. The semiconductor chip (1) is a ceramic package (3)
In a semiconductor device dice-bonded with a low melting point brazing filler metal (2), the semiconductor chip (1) has steps (4) formed by half etching at the four corners of the surface to be brazed, and these portions are not brazed. A semiconductor device characterized by:
JP63159210A 1988-06-29 1988-06-29 Semiconductor device Pending JPH0210714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63159210A JPH0210714A (en) 1988-06-29 1988-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63159210A JPH0210714A (en) 1988-06-29 1988-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0210714A true JPH0210714A (en) 1990-01-16

Family

ID=15688729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63159210A Pending JPH0210714A (en) 1988-06-29 1988-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0210714A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5076260A (en) * 1989-09-14 1991-12-31 Bodysonic Kabushiki Kaisha Sensible body vibration
DE10042931A1 (en) * 2000-08-31 2002-03-28 Infineon Technologies Ag Process for fixing semiconductor chip to substrate comprises forming profile on the edge on the lower side of the chip to create larger distance between the chip and the substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5076260A (en) * 1989-09-14 1991-12-31 Bodysonic Kabushiki Kaisha Sensible body vibration
DE10042931A1 (en) * 2000-08-31 2002-03-28 Infineon Technologies Ag Process for fixing semiconductor chip to substrate comprises forming profile on the edge on the lower side of the chip to create larger distance between the chip and the substrate

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