JPH02105387A - Picture memory - Google Patents

Abstract

PURPOSE:To obtain a memory picture of a simple constitution that contains the decreased number of memories and a simplified external control mechanism by multiplexing a serial output buffer. CONSTITUTION:A multiplexed output buffer part 1 has the same function as the output buffer of a conventional picture memory. A transfer control circuit 2 receives the address information and the output cycle signal from an external circuit which controls a picture memory synchronously with a display action and controls the rewrite and the output of an output buffer. The circuit 2 functions to select each output buffer 1A of the part 1 and receives three types of output address information and the weight information on each display data from an external circuit for control. Then the circuit 2 controls a logical process circuit 3 for output data based on those received information. Thus the final output data is selectively produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image memory, and more particularly to an image memory that stores digital image data such as a terminal and has a serial output structure.

[Conventional technology]

Conventionally, the image memory of this nest consists of a boat that reads and writes display data for the purpose of increasing the drawing speed,
It is independently equipped with one port that outputs display data to a display mechanism. By having each of these bauds 1 to 1 independently, image data can be freely read and written even during the time period when display data needs to be output, improving drawing efficiency and increasing drawing speed.

[Problem to be solved by the invention]

The conventional image memory mentioned above has a single serial output, so when displaying multiple screens at the same time (hereinafter referred to as
Windows) have the following drawbacks whether they are implemented using hardware or software.

In other words, in the case of a pigeonware window, the position information (address) necessary for display is changed every time the screen is changed, so display information is frequently moved from the storage area to the display output data storage area ( It is necessary to transfer data to the output buffer). Therefore, the improvement in drawing efficiency is very small, and there is a drawback that this type of memory is not suitable for use.

Further, when the above-mentioned window is realized by a software window, the display data is always arranged continuously based on the principle that data necessary for display is arranged in an orderly manner. Therefore, the efficiency of transfer in this type of memory is the best. However, it is necessary to always secure a display area for continuously arranging display data, which has the disadvantage that the number of required memories increases. Furthermore, when a portion of the drawing data is combined and displayed, the cycle of image data drawing, transfer and display operations is repeated, resulting in a disadvantage that the speed at which the display data is changed becomes slow.

An object of the present invention is to provide an image memory that has a simple configuration and simplifies the number of memories and external control mechanism.

[Means to solve the problem]

The image memory of the present invention includes an image information storage section that stores image information based on image data and address information, a multiplex output buffer section that has a plurality of output buffers respectively connected to the image information storage section, and a multiplex output buffer section that stores image information based on image data and address information. The device is configured to include a serial output signal and a control section that controls the output signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of an image memory showing a first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, the input side receives address information, stored data, and control signals such as chip select signals sent from a processing device (not shown), etc.
The output side includes an image information storage section 5, a multiplex output buffer section 1 having a plurality of output buffers LA (three in this example), and a bus 6 on the input side in order to output image display data to a CRT or the like. a transfer control circuit unit 2 that receives part of the data and address information received via the chip select signal as a chip select signal, and controls data output from the image information storage unit 5 to each output buffer IA of the multiplexed output buffer unit 1; and a control section 4 having a logic processing circuit section 3 that performs logic operations on the output of each output buffer IA based on the logic operation processing information from the transfer control circuit section 2 and the output control signal from the input side and determines the output to a CRT or the like. It is equipped with The multiplexed output buffer section 1 has an output buffer and an editing function of a conventional image memory, respectively. The transfer control circuit unit 2 is intended to manage address information of data necessary for display, and is provided with address information and output cycle signals (hereinafter referred to as clocks) in synchronization with the display operation from an external circuit that manages the image memory. ), and controls rewriting of the output buffer and output. The transfer control circuit 2 described above is configured as a control circuit that selects each multiplexed output buffer IA, and transfers three types of output address information and weight information of each display data from an external control circuit. The data is captured each time, and the output data logic processing circuit section 3 is controlled based on the information. As a result, final output data is selectively generated.

By using such an image-dedicated memory, in order to generate a screen on which a window exists, an external circuit stores information of multiple screens in the memory and provides address information to the transfer control unit 2, and By giving priority weights to each output buffer IA, it becomes possible for the logic circuit 3 in the control section 4 to output the selected output data.

FIG. 2 is a functional block diagram of an image memory showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment includes a multiplexed (in this case, triplexed) output buffer section 1, a control section 4 having a transfer control circuit 2 and an output data logic processing circuit 3, and an image information storage section. 5 is similar to the first embodiment described above. Further, as in the first embodiment, the transfer control circuit section 2
The purpose is to manage the address information of the data required for display, and it receives address information and clock in synchronization with the display operation from the external circuit that manages the image memory.
Controls output buffer rewriting and output.

This embodiment differs from the first embodiment described above in that the transfer control circuit 2 is configured as a collection of independent control circuits corresponding to the individual output buffers IA multiplexed. That is, by adopting this configuration, it is possible to have a plurality of management addresses to transfer information from the same image information storage section 5 to the output buffer IA for display.

Therefore, by setting a plurality of display addresses, output data can be automatically (time-divisionally) transferred from the plurality of addresses to the output buffer IA.

In this case, when this type of image-dedicated memory is used, in order to generate a screen with a window, the external circuit stores information for multiple screens in the memory and gives address information to the transfer control unit 2. The image information storage section 5 may transfer necessary transfer data to the output buffer IA, and the logic processing circuit section 3 may perform logical operation processing on the transferred data.

〔Effect of the invention〕

As explained above, the image memory of the present invention provides address information for displaying the window function of digital image data on a terminal, etc. and the weight (priority order) of each screen by multiplexing serial output buffers. This has the advantage that it can be easily achieved by just doing this. In addition, the present invention eliminates the need for a data storage area only for display as in the software window method, and can reduce the number of memories. Since there is no need to input information, the external control mechanism is also relatively simple.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an image memory showing a first embodiment of the invention, and FIG. 2 is a functional block diagram of an image memory showing a second embodiment of the invention. ]...Multiplex output buffer unit, IA...Output buffer, 2...Transfer control circuit unit, 3...Logic processing circuit unit, 4...Control unit, 5...Image information storage unit , 6... bus.

Claims (1)

[Claims] an image information storage unit that stores image information based on image data and address information; a multiplex output buffer unit that has a plurality of output buffers respectively connected to the image information storage unit; and a multiplexed output buffer unit that stores multiplexed serial outputs and output signals thereof. An image memory characterized by having a control section that performs control.