JPH0210450A - Prefetch control system for cache memory - Google Patents

Abstract

PURPOSE:To increase the processing speed of a processor by taking actions of access such as direct increase and repetition into consideration and executing prefetch at the time of profiting from application of prefetch. CONSTITUTION:A processor 10 which controls and executes operation is provided with an instruction decoding part 13 which reads out an instruction to decode the meaning of the instruction and an instruction executing part 19 which executes the instruction in accordance with the decoded results. A cache memory 11 includes an address array 16, a data array 17, and a control logic 19, and the access type of a control logic 19 is detected by a signal which is outputted form the processor 10 and indicates the classification of access, and a prefetch start circuit 24 is started in accordance with the detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a block advance fetch method in an information processing apparatus having a processor, a cache memory, and a main storage device.

[Conventional technology]

Regarding cache memory, see Computer Survey, Vol. 14, No. 3, pp. 473-530.
r 5urveys, Vol, 14. &3. pp473
-530) is discussed in detail. Cache memory has a smaller capacity than main memory, but provides high-speed access (
A memory that can be read and written (read and write), and is placed inside or near the processor for the purpose of speeding up access by the processor. The data transfer time between main memory and the processor is several times the processor's internal processing time, so
Instructions required for processing.

If data is read every time it is executed, it is not possible to speed up processing. On the other hand, a processor accesses the entire main memory, but accesses are concentrated on a small portion of the main memory over a very short period of time. Therefore, by copying part of the information in the main memory to the cache memory and making most of the processor accesses to and from the cache memory, the average access time can be shortened.

Cache memory manages storage in units of appropriate size called blocks. Each block corresponds to a location in the main memory and holds a copy of the data at that location. This storage part is called a data array. In addition, it is of course possible to dynamically change which location in the main memory each block corresponds to, and this information is also held in the cache memory. This memory portion is called an address array.

In order for most of the processor's accesses to be made to and from cache memory, data that has been accessed frequently recently should be placed in the cache, and vice versa. Data does not necessarily have to be placed in the cache; the cache memory provides control to meet the above requirements. This can be explained using the example of reading as follows.

When data in the cache is accessed, the block to which the data belongs continues to be held; when data that is not in the cache is accessed, one block containing the data in main memory is transferred to the cache, and the block containing the data is transferred to the cache instead. Next, we will explain advance fetching, which is important for cache memory control. Advance fetching refers to a function in which the cache memory automatically transfers from the main memory the next block after the block to which the data accessed by the processor belongs. Generally, there is a high possibility that the processor will need the next block in the near future, so by anticipating the processor's request, the waiting time for data transfer with the main memory can be shortened, helping to increase speed.

[Problem to be solved by the invention]

This proactive fetching feature increases the probability that processor accesses will hit the cache.
The time delay caused by data transfer from main memory is reduced, but at the same time the bus around the data array becomes more congested, which can delay processor access and slow down the overall processing speed. . By the way, the behavior of the address accessed by the processor differs depending on whether it is an instruction or not. Specifically, while addresses for instruction accesses often increase linearly, addresses for accesses other than instructions do not necessarily increase monotonically. In such a case, there may be a request to perform advance fetch only for instruction access. As just mentioned, it is necessary to perform advance fetch in detail, but conventionally, when controlling advance fetch, different controls are used depending on the content of the processor's access, that is, whether it is an instruction access or a non-instruction (data) access. No method was provided.

[Means to solve the problem]

Therefore, the present invention utilizes the fact that the processor outputs the type of access from the processor using a signal line, the cache memory detects the signal, and determines whether to perform advance fetch processing based on the detection result. A mechanism has been established to select the

[Effect]

By taking the above-mentioned means, it has become possible to perform advance fetch only for instruction accesses, which was previously impossible, or, conversely, advance fetch only for accesses other than instructions.

〔Example〕

An example of realizing the present invention will be described below using figures.

FIG. 1 shows an overall diagram of this information processing apparatus. 10 is a processor that controls and executes calculations; 11 is a cache memory;
12 is a main storage device 6 The inside of the processor 10 can be roughly divided into an instruction interpreting section 13 that reads out an instruction and interprets the meaning of the instruction, and an instruction executing section 14 that executes the instruction according to the interpretation result of the instruction interpreting section 13. It is divided into Command interpretation section 13
and the instruction execution unit 14 perform access using address lines and data lines that are connected to each other.

The access type line 15 is a signal line indicating whether the entity that is accessing using the address line and data line at that time is the instruction interpreter 13 or the instruction execution unit 14.

To give an example of how the access type signal 15 has been used in the past, when the same address is used for dual meanings of instructions and data, and separate memories are implemented for each of the instructions and data to configure a system, There is a usage in which it is used as a signal line to select one of two types of memory.

Each internal portion of cache memory element 11 will be described below. The address array 16 is connected to the processor 10 via a processor side address line and to the main memory device 12 via a main memory side address line. The data array 17 is connected to the processor 10 via a processor side data line and to the main memory device 12 via a main memory side data line. The address array 16 and data array 17 are arranged in columns as shown in the figure, and the columns are configured to be selected by lower addresses. In particular, a control method in which the address array and data array specified by the lower address have multiple columns instead of one column is called a set associative method, and in this embodiment, a four column set associative method is used. At that time, if the address array has a total of N columns, the first column, (i + N / 4) column, (i + 2N / 4) column,
The (i+3N/4)th column is selected at the same time. Each column of the address array 16 consists of an upper address A and two types of 1-bit flags: a valid flag V and an update flag U.
Each column of data array 17 consists of a storage section for one block of data. For each column of the address array 16, one address can be specified by a combination of the upper address and the lower address, and one block of data starting from the corresponding address on the main memory is stored in the data array 17 of the corresponding column. The valid flag V is a flag that indicates that the information in the data array 17 is correct for the corresponding address, and the update flag U is a flag that indicates that the information in the data array 17 is correct for the corresponding address, but the information in the main memory 12 is incorrect. This is a flag indicating that

The block buffer 18 is a buffer memory that temporarily stores data when transferring data from the main memory device 12 to the data array 17, and has the effect of ensuring smooth access to the data array 17. The control logic 19 is connected to the processor 10 via a processor-side control line.

It is connected to the main memory device 12 via a main memory side control line. Here, an access type line 15 is included in the processor side control lines.

It is important that the access type line 15 is input to the control logic 19. Reference numeral 20 is a comparator for making a hit determination which will be described later, and reference numeral 21 is an address counter.

The inside of the control logic 19 will be explained.

Only those important for explaining the present invention are shown here. The access type detection unit 22 receives the access type signal 15 as input and detects the type of access by the processor 10 . The advance fetch activation control unit 23 is a circuit that controls the advance fetch request signal 28. The advance fetch activation circuit 24 is a circuit that activates the advance fetch operation, and receives the detection result 27 of the instruction access detection unit 22 and the advance fetch request signal 28 as input, and outputs the advance fetch activation signal 29 to the memory access control unit 25. do. The memory access control unit 25 is a circuit that controls access between the cache memory 11 and the main storage device 12.

The bit determination unit 26 inputs the comparison result of the comparator 20,
Advance fetch request control unit 2 for the result of hit determination
3 and the memory access control unit 25 is notified.

A method for realizing access from the processor 10 in this device will be described. When processor 10 issues an access request to cache memory 11, control logic 19 checks whether the data in question is held in data array 17.

At this time, if it is held, it is called a hit, and if it is not held, it is called a miss.The determination of whether or not it is a hit is done as follows.The address array 16 is searched using the lower address output by the processor 10. A column is determined, and in each column, the upper address A read from that column is compared with the upper address outputted by the processor 10. Also,
Check the validity flag V of each column. At this time, if the conditions that the upper addresses match and the valid flag V is 1 are satisfied in any one column, it becomes a hit. Comparison of upper addresses is performed by a comparator 20, and the result is sent to a hit determination unit 26.
to notify.

In devices using cache memory, there are two write methods: a write-through method and a copy pack method. The write-through method is a method in which data is always written to the main memory when writing, and the copy pack method is a method in which data is written to the data array 17 without being written to the main memory. In the copy pack method, data is not written to the main memory, so there is a temporary discrepancy in the stored contents, but it can be understood that by using the update flag U and following the processing steps described below, this discrepancy will eventually be resolved. In this embodiment, both the write-through method and the copy-back method can be used simultaneously, and both are separated by the address area.

The processing procedure when an access from the processor 10 occurs will be explained according to the flowchart in FIG. 2.

In FIG. 2, MPU is the processor 10, DA is the data array 17, BB is the block buffer 18, MM is the main memory bag [12, v, and u are the valid flag and update flag in the address array 16, respectively.

(Start): When an access from the processor 10 occurs, the process advances to the process 100.

Process 100 The address of the address line is taken into the near address counter 21. If the access is a read access, go to process 101.

If it is a write access, go to process 108.

Process 101: If the access hits the cache, proceed to process 102. If a mistake is made, go to process 103.

Process 102: Transfer the accessed data from the data array 17 to the processor 10 and end.

Process 103: Determine which block in the data array 17 must be evicted in order to bring the block containing the accessed data from the main memory 12. If the valid flag V and update flag U of the block are both 1, the process goes to process 104; otherwise, the process goes to process 105.

Process 104: 1 block to be evicted is transferred to data array 1
7 to the main storage device 12. Proceed to process 105.

Process 105: Transfer one block containing the accessed data from the main storage device 12 to the block buffer 18. The accessed data is transferred from the block buffer 18 to the processor 10.

1 block containing accessed data Deleting the block from block buffer 18 data array 17. data Corresponding to the transferred location of array 17 Valid flag of address array 16 Set ■ to 1 and update flag U to 0.

Go to process 106.

Process 106: If the advance fetch activation signal 29 is 1, go to process 107. If O, end.

Process 107: Increase the value of the address counter 21 by one block compared to the initial access address, and proceed to process 101.

Process 108: If the access hits the cache, proceed to process 109. If a mistake is made, go to process 112.

Process 109: If the accessed area is a copy pack area, go to process 110. If not, go to process 111.

Process 110: Write data from the processor 10 to the hit location of the data array 17. Then, the update flag U of the address array 16 corresponding to the corresponding location is set to 1, and the process ends.

Process 111: Write data from the processor IO to the hit location of the data array 17 and the main memory 12, and end.

Process 112: If the accessed area is a copy pack area, proceed to process 113; otherwise, proceed to process 116.

Process 113: In order to select one block containing the accessed data from the main memory bag [12], one block in the data array 17 that must be evicted is determined instead. If the valid flag V and update flag U of the block are both 1, go to process 114; otherwise, go to process 1158.

Process 114: 1 block to be evicted is transferred to data array 1
7 to the main storage device 12. Proceed to process 115.

Process 115: Transfer one block containing the accessed data from the main storage device 12 to the block buffer 18. One block containing the accessed data is transferred from block buffer 18 to data array 17. Data is written to the location transferred from the processor 10 to the data array 17. Then, both the valid flag V and update flag U of the address array 16 corresponding to the corresponding location are set to 1, and the process ends.

Process 116: Write data from the processor 10 to the main storage device 12, and end.

Note that since the pre-fetch data is not data directly requested by the processor 10, no data is transferred to the processor 10 in processing 102 and processing 105 after processing 107 is performed.

The internal operation of the control logic 19 from the time when a read error occurs to the advance fetch operation will be explained. In process 101, upon receiving information from the hit determination unit 26 that a read error has occurred, the advance fetch request control unit 23 prepares to output the advance fetch request signal 28. Then, when the process 105 is completed, the advance fetch request control unit 23 sends the advance fetch request signal 2.
Assert 8 (set the signal to 1).

The pre-fetch operation is activated by a pre-fetch activation signal in process 106. FIG. 3 shows a circuit diagram of the advance fetch activation circuit 24 that generates the advance fetch activation signal in the present invention. Reference numerals 30 and 31 are registers that designate advance fetching for instruction access and non-instruction access, respectively, and the contents of these registers can be set from the processor 10. The access type detection result 27 is 1 while the access currently being processed is an instruction access. 32°33,. 34
is a two-manpower AND gate, and its output value is the logical product of the two manpower. 35 is an OR gate operated by two operators, and its output value is the logical sum of the two operators. 36 is a NOT gate, the output value of which is the inverted value of the logic of the input.

When the access being processed is an instruction access, assertion of the advance fetch request signal 28 is transmitted to the advance fetch activation signal 29 only when the value of the register 30 is 1. When the access being processed is not an instruction access, assertion of the advance fetch request signal 28 is transmitted to the advance fetch activation signal 29 only when the value of the register 31 is 1.

Then, the memory access control unit 25 enters the advance fetch operation in response to the advance fetch activation signal 29 (processing 106→107), performs a hit determination for the next block (processing 101), and receives information from the hit determination unit 26 that the next block has missed. When received, advance fetch access to the main storage device 12 is started (process 104 or 105).

As described above, it has been explained that the activation of advance fetch can be set independently depending on whether the processor access is an instruction access or not.

〔Effect of the invention〕

By using this information processing device, command access and non-command access can be controlled from the software side.
Considering access behavior such as direct increase and repeatability,
Pre-fetching is performed when there is a gain by applying pre-fetching for each, thereby making it possible to increase the processing speed of the processor by one layer.

[Brief explanation of the drawing]

FIG. 1 is an overall diagram of the apparatus used in the present invention, FIG. 2 is a processing procedure for access from a processor, and FIG. 3 is a circuit diagram of the advance fetch activation circuit in FIG. 1. DESCRIPTION OF SYMBOLS 10... Processor element, 11... Cache memory element, 12... Main memory device, 13... Instruction interpreter, 14... Instruction execution unit, 15... Access type signal. 16... Address array, 17... Data array,
18...Block buffer, 19...Control logic, 20...Comparator, 21...Address counter, 22...Access type detection section, 23...Advanced fetish request control section, 24...・Advanced fetch activation circuit, 25...Memory access control unit, 26...Bit judgment unit, 27...Access type detection result, 28...Advanced fetch request signal, 29...
- Advance fetch activation signal, 30... register for selecting execution of advance fetch for instruction access, 31
...Register for selecting advance fetch for accesses other than instructions, 32, 33°34...AN
D gate, 35...OR gate, 36th... concave

Claims (1)

[Claims] 1. In an information processing device that has a cache memory that exchanges information with the main memory in block units, when the block next to the block to which the data accessed by the processor belongs does not exist in the cache memory, the next block is used as the main memory. When a pre-fetch function that transfers data from memory is provided, information regarding the type of access output by the processor is detected using a signal line, and the selection of whether or not to perform pre-fetch is made based on whether the processor's request is an instruction access or not. A block advance fetch method characterized by having a function to independently set two types of accesses, one for accesses other than instructions.